JPH0326550B2 - - Google Patents
Info
- Publication number
- JPH0326550B2 JPH0326550B2 JP58082075A JP8207583A JPH0326550B2 JP H0326550 B2 JPH0326550 B2 JP H0326550B2 JP 58082075 A JP58082075 A JP 58082075A JP 8207583 A JP8207583 A JP 8207583A JP H0326550 B2 JPH0326550 B2 JP H0326550B2
- Authority
- JP
- Japan
- Prior art keywords
- thick film
- resistor
- width
- conductor
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004020 conductor Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 7
- 238000007493 shaping process Methods 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 238000007639 printing Methods 0.000 description 4
- 238000010304 firing Methods 0.000 description 3
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- 230000000740 bleeding effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Description
【発明の詳細な説明】
本発明は膜回路基板の製造方法で、特に厚膜回
路基板の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a film circuit board, and particularly to a method for manufacturing a thick film circuit board.
従来の厚膜回路基板の製造方法は、例えば絶縁
性基板上に厚膜導体ペーストおよび厚膜抵抗体ペ
ースト等を印刷する工程と、印刷された各々のペ
ーストを焼成する工程とを組合せていた。 A conventional method for manufacturing a thick film circuit board combines, for example, a step of printing a thick film conductor paste, a thick film resistor paste, etc. on an insulating substrate, and a step of firing each of the printed pastes.
しかしながら、この製造方法により形成された
厚膜回路は、絶縁性基板上に各々のペーストを印
刷用スクリーンを用いて印刷する時、スクリーン
がメツシユ状で25〜50μの厚さがあるため印刷さ
れた各々のペーストの印刷精度は悪く、その上印
刷されたペーストを焼成する時にいわゆる「にじ
み現象」によりペーストが更に拡がるため、焼成
後の厚膜回路の寸法精度は50〜100μとなる。従
つて、この方法では厚膜回路として50μ以下の微
細パターンを製造することができなかつた。この
欠点を除去する方法としては、前述の製造工程に
ホトレジストを用いたホトエツチング工程を加え
ることが考えられるが、レジスト材料やエツチン
グ液の制限や複雑なホトエツチング工程の付加に
よりコスト高を招くことになりかねない。 However, when printing each paste on an insulating substrate using a printing screen, the thick film circuit formed by this manufacturing method is difficult to print because the screen is mesh-shaped and has a thickness of 25 to 50μ. The printing accuracy of each paste is poor, and furthermore, when the printed paste is fired, the paste spreads further due to the so-called "bleeding phenomenon", so the dimensional accuracy of the thick film circuit after firing is 50 to 100 microns. Therefore, with this method, it was not possible to produce a fine pattern of 50 μm or less as a thick film circuit. One possible way to eliminate this drawback is to add a photoetching process using photoresist to the above-mentioned manufacturing process, but this increases costs due to restrictions on resist materials and etching solutions, and the addition of a complicated photoetching process. It's possible.
本発明の目的は精度の良い膜回路を簡単に製造
する方法を提供することにある。 An object of the present invention is to provide a method for easily manufacturing a highly accurate membrane circuit.
即ち、本発明の膜回路基板の製造方法は、絶縁
性基板上に膜回路を製造する工程において、膜回
路を製造する工程内に膜導体または膜抵抗体の所
望の部分をレーザー光線の照射により整形または
形成する工程とを含むことを特徴とする。 That is, the method for manufacturing a film circuit board of the present invention includes shaping a desired portion of a film conductor or film resistor by irradiation with a laser beam during the process of manufacturing a film circuit on an insulating substrate. or a step of forming.
次に本発明の詳細を一実施例を挙げて具体的に
説明する。 Next, details of the present invention will be specifically explained by giving an example.
第１図ａ，ｂ乃至第３図ａ，ｂは本発明による
厚膜回路基板の完成までの各工程図を示し、ａは
表面図、ｂは断面図を夫々示す。 1A and 3B to FIGS. 3A and 3B show each process step up to the completion of the thick film circuit board according to the present invention, where a shows a surface view and b shows a cross-sectional view, respectively.
まず第１図のように絶縁性基板となるアルミナ
板１上に厚膜導体ペースト（パラジユムと銀の混
合ペースト）を所望の形状になるよう印刷し、焼
成用電気炉等により焼成しアルミナ板１上に所望
の銀パラジユームの厚膜導体２を形成する。次に
第１図の銀パラジユームの厚膜導体上に目合せを
行ない厚膜抵抗体ペースト（酸化ルテニウム）を
スクリーン印刷し、厚膜導体と同様に焼成し所望
の厚膜抵抗体３を形成する。次に、レーザートリ
ミング装置の如くレーザー光を発生する装置で、
第２図の厚膜回路の厚膜導体２、厚膜抵抗体３の
不必要部分をレーザー光線の照射により焼き飛ば
し、厚膜導体インダクタ２′、厚膜抵抗体３を整
形する。この場合厚膜抵抗体３に整形し次に抵抗
体の抵抗値をレーザートリミングすることも可能
である。なお一般には厚膜抵抗体３の両端の厚膜
導体２の幅が抵抗体３の幅より広いのが通常であ
る。これは厚膜導体２に目合せを行い厚膜抵抗体
３をスクリーン印刷する際、位置ずれが生じるた
め、位置ずれによる厚膜抵抗体３の両端が厚膜導
体からはみ出さないようにするためである。とく
に導体のパターンずれよりも抵抗体のパターンず
れの方が回路定数に直接影響するため抵抗体の方
を精度よく作らなければならない。しかしながら
このような厚膜導体と抵抗体のパターン設計法で
は厚膜回路の高密度化、微細パターン化は困難で
ある。厚膜回路の高密度、微細パターンを実現す
るには、抵抗体の両端の導体の幅と合わせ、無駄
な導体幅を削除し、全体を高密度にレイアウトす
ることが必要であることは言うまでもない。従つ
て、本発明の厚膜基板の製造方法では、厚膜抵抗
体の両端の厚膜導体は、あらかじめ第１図におい
て厚膜抵抗体に必要な設計幅に等しい幅で印刷し
ておき、第２図の抵抗体のスクリーン印刷におい
て低抗体の幅は、抵抗体に必要な設計幅＋位置ず
れ幅となるように従来とは逆に幅広く印刷、焼成
し、第３図において、レーザー光線の照射によ
り、位置ずれ部分を焼き飛ばし抵抗体の最終的な
設計幅に整形するようにしている。同様に、第２
図の厚膜導体２の右側の部分では、レーザー光線
の照射により、導体の不必要部分を焼き飛ばして
微細な導体インダクタ回路素子を形成している。 First, as shown in Figure 1, a thick film conductor paste (mixed paste of palladium and silver) is printed on an alumina plate 1 that will serve as an insulating substrate in a desired shape, and is fired in an electric furnace for firing. A desired thick film conductor 2 of silver palladium is formed thereon. Next, a thick film resistor paste (ruthenium oxide) is screen printed on the silver palladium thick film conductor shown in FIG. 1 and fired in the same manner as the thick film conductor to form the desired thick film resistor 3. . Next, a device that generates laser light, such as a laser trimming device,
Unnecessary portions of the thick film conductor 2 and thick film resistor 3 of the thick film circuit shown in FIG. 2 are burned off by laser beam irradiation, and the thick film conductor inductor 2' and thick film resistor 3 are shaped. In this case, it is also possible to shape the thick film resistor 3 and then laser trim the resistance value of the resistor. In general, the width of the thick film conductor 2 at both ends of the thick film resistor 3 is usually wider than the width of the resistor 3. This is to prevent both ends of the thick film resistor 3 from protruding from the thick film conductor due to misalignment that occurs when aligning the thick film conductor 2 and screen printing the thick film resistor 3. It is. In particular, resistor pattern misalignment has a more direct effect on circuit constants than conductor pattern misalignment, so the resistor must be made with greater precision. However, with such pattern design methods for thick film conductors and resistors, it is difficult to achieve high density and fine patterning of thick film circuits. It goes without saying that in order to achieve high-density, fine patterns for thick-film circuits, it is necessary to match the width of the conductors at both ends of the resistor, eliminate unnecessary conductor width, and lay out the entire circuit with high density. . Therefore, in the thick film substrate manufacturing method of the present invention, the thick film conductors at both ends of the thick film resistor are printed in advance with a width equal to the design width required for the thick film resistor in FIG. In the screen printing of the resistor shown in Figure 2, the width of the low antibody was printed and baked to be wider than the conventional method so that the width corresponded to the design width + misalignment width required for the resistor. , the misaligned portions are burned off and shaped to the final design width of the resistor. Similarly, the second
On the right side of the thick film conductor 2 in the figure, unnecessary portions of the conductor are burned off by laser beam irradiation to form a fine conductor inductor circuit element.
本発明の説明では、厚膜導体２と厚膜抵抗体３
の各々をレーザー光線の照射により、整形、パタ
ーンニングすることを述べたが、厚膜導体または
低抗体のどちらか一方をレーザー光線の照射によ
り整形したりまたは形成する方法においても効果
があることは明らかである。 In the description of the present invention, a thick film conductor 2 and a thick film resistor 3 will be described.
Although we have described shaping and patterning each of these materials by irradiating them with laser beams, it is clear that shaping or patterning either the thick film conductor or the low antibody by irradiating them with laser beams is also effective. be.
以上説明したように、本発明の厚膜回路基板の
製造方法によれば、高密度微細な厚膜回路パター
ンを形成するのに、必要に応じてレーザー光線の
照射法を用いて抵抗体や導体の位置ずれの修正、
寸法精度の向上、インダクター、ギヤツプキヤパ
シターの形成などが可能となり、しかも、複雑で
高価なホトエツチングの工程を余分に追加するこ
となく、従来より行なわれている抵抗値修正のた
めのレーザー抵抗トリミング工程のプログラムを
変更するのみで可能となる。従つて、安価で高歩
留、高位置精度の微細な厚膜回路基板の製造方法
を提供することができ、その効果は大きい。 As explained above, according to the method for manufacturing a thick film circuit board of the present invention, a laser beam irradiation method is used as needed to form a high-density, fine thick film circuit pattern. Correction of misalignment,
It is now possible to improve dimensional accuracy and form inductors and gap capacitors, without adding an extra complicated and expensive photo-etching process. This can be done by simply changing the program for the resistor trimming process. Therefore, it is possible to provide a method for manufacturing a fine thick film circuit board at low cost, with high yield, and with high positional accuracy, and its effects are significant.
第１図、第２図、第３図は本発明の厚膜回路基
板の製造方法の一実施例を説明するための各工程
図を示し、ａはその表面図、ｂはその断面図を
各々示す。
１……絶縁性アルミナ基板、２……銀パラジユ
ーム厚膜導体、２′……厚膜導体インダクタ、３
……酸化ルテニウム厚膜抵抗体、３′……整形さ
れた厚膜抵抗体。
1, 2, and 3 show process diagrams for explaining one embodiment of the method for manufacturing a thick film circuit board of the present invention, in which a is a surface view thereof and b is a cross-sectional view thereof. show. 1...Insulating alumina substrate, 2...Silver palladium thick film conductor, 2'...Thick film conductor inductor, 3
...Ruthenium oxide thick film resistor, 3'...Shaped thick film resistor.
Claims (1)
厚膜抵抗体の両端に形成された第１及び第２の厚
膜導体を有する膜回路基板の形成方法において、
前記第１及び第２の厚膜導体を前記抵抗体に必要
な設計幅に等しい幅で形成する工程と、その後、
前記抵抗体に必要な設計幅に位置ずれ幅を加えた
幅を有する前記抵抗体を前記第１及び第２の厚膜
導体の間に設ける工程と、その後、レーザ光線の
照射により前記抵抗体の前記位置ずれ部分を焼き
飛ばし、前記抵抗体の最終的な設計幅に整形する
工程とを有することを特徴とする膜回路基板の製
造方法。1. A method for forming a film circuit board having a thick film resistor formed on an insulating substrate and first and second thick film conductors formed at both ends of the thick film resistor,
forming the first and second thick film conductors with a width equal to the design width necessary for the resistor;
a step of providing the resistor having a width equal to the design width required for the resistor plus a misalignment width between the first and second thick film conductors, and then irradiating the resistor with a laser beam to A method for manufacturing a film circuit board, comprising the step of burning off the misaligned portion and shaping the resistor to the final design width.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58082075A JPS59207651A (en) | 1983-05-11 | 1983-05-11 | Manufacture of filmy circuit substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58082075A JPS59207651A (en) | 1983-05-11 | 1983-05-11 | Manufacture of filmy circuit substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59207651A JPS59207651A (en) | 1984-11-24 |
| JPH0326550B2 true JPH0326550B2 (en) | 1991-04-11 |
Family
ID=13764351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58082075A Granted JPS59207651A (en) | 1983-05-11 | 1983-05-11 | Manufacture of filmy circuit substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59207651A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2695000B2 (en) * | 1989-04-11 | 1997-12-24 | 住友電気工業株式会社 | Thermistor and manufacturing method thereof |
| US5922514A (en) * | 1997-09-17 | 1999-07-13 | Dale Electronics, Inc. | Thick film low value high frequency inductor, and method of making the same |
| KR100324209B1 (en) * | 2000-01-28 | 2002-02-16 | 오길록 | Fabrication method of silver inductors |
| JP2002111222A (en) * | 2000-10-02 | 2002-04-12 | Matsushita Electric Ind Co Ltd | Multilayer substrate |
| JP2007165932A (en) * | 2007-02-22 | 2007-06-28 | Matsushita Electric Ind Co Ltd | Multilayer substrate |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50139357A (en) * | 1974-04-25 | 1975-11-07 | ||
| JPS5871647A (en) * | 1981-10-23 | 1983-04-28 | Omron Tateisi Electronics Co | Trimming method for reactance |
-
1983
- 1983-05-11 JP JP58082075A patent/JPS59207651A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50139357A (en) * | 1974-04-25 | 1975-11-07 | ||
| JPS5871647A (en) * | 1981-10-23 | 1983-04-28 | Omron Tateisi Electronics Co | Trimming method for reactance |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59207651A (en) | 1984-11-24 |
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