JPH0514542Y2 - - Google Patents
Info
- Publication number
- JPH0514542Y2 JPH0514542Y2 JP1986154993U JP15499386U JPH0514542Y2 JP H0514542 Y2 JPH0514542 Y2 JP H0514542Y2 JP 1986154993 U JP1986154993 U JP 1986154993U JP 15499386 U JP15499386 U JP 15499386U JP H0514542 Y2 JPH0514542 Y2 JP H0514542Y2
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- conductive resin
- resin
- insulating substrate
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000011347 resin Substances 0.000 claims description 24
- 229920005989 resin Polymers 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 239000002245 particle Substances 0.000 claims description 3
- 230000006335 response to radiation Effects 0.000 claims 1
- 238000000034 method Methods 0.000 description 4
- 239000002253 acid Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Description
【考案の詳細な説明】
［考案の技術分野］
この考案は、表面に配線パターンを設けた回路
基板に関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a circuit board having a wiring pattern on its surface.
［従来技術とその問題点］
従来、回路基板に形成される配線パターンは、
絶縁基板の面に接着された金属膜（例えば銅箔）
の表面に、耐酸性感光剤（絶縁物）からなるフオ
トレジストを塗布し、露光、現像するか、また
は、前記金属膜の表面に耐酸インキで形成される
パターン印刷を施し、次いで、前記金属膜をエツ
チング処理したのち、前記金属板の表面に形成さ
れている前記フオトレジストまたは前記耐酸イン
キを除去して、導電性の配線パターンを形成させ
ている。[Prior art and its problems] Conventionally, the wiring pattern formed on the circuit board is
A metal film (e.g. copper foil) bonded to the surface of an insulating substrate
A photoresist made of an acid-resistant photosensitive agent (insulator) is coated on the surface of the metal film, exposed and developed, or a pattern formed with acid-resistant ink is printed on the surface of the metal film, and then After etching, the photoresist or the acid-resistant ink formed on the surface of the metal plate is removed to form a conductive wiring pattern.
このため、絶縁基板の面に導電性の配線パター
ンを形成するためのプロセスが、複雑になるとい
う問題点があつた。 Therefore, there was a problem in that the process for forming a conductive wiring pattern on the surface of the insulating substrate became complicated.
［考案の目的］
この考案は上述した事情に鑑みてなされたもの
で、その目的とするところは、配線パターンの形
成プロセスを容易にした回路基板を提供しようと
するものである。[Purpose of the invention] This invention was made in view of the above-mentioned circumstances, and its purpose is to provide a circuit board that facilitates the process of forming a wiring pattern.
［考案の要点］
この考案は上述した目的を達成するために、
光、電子ビーム、エツクス線等の放射エネルギー
に感応して硬化される樹脂に導電性粒子を混入さ
せた導電性樹脂を用いて、絶縁基板等の面に配線
パターンを形成したことを特徴とするものであ
る。[Main points of the invention] In order to achieve the above-mentioned purpose, this invention
A wiring pattern is formed on the surface of an insulating substrate, etc. using a conductive resin in which conductive particles are mixed into a resin that hardens in response to radiant energy such as light, electron beams, and X-rays. It is something.
［考案の実施例］
以下、この考案を図面に示す実施例に基づいて
説明する。[Example of the invention] This invention will be described below based on an example shown in the drawings.
［第１実施例］
第１図は第１の実施例を示し、１は絶縁基板
で、この絶縁基板１の表面に金属膜（例えば銅
箔）２で形成された配線パターン２ａが形成され
ていて、この配線パターン２ａの表面に更に導電
性樹脂３で形成されている配線パターン３ａが積
層されている。この配線パターン３ａを形成する
導電性樹脂３は、光に感応して硬化する樹脂に導
電性粒子を混入させた光硬化型の導電性樹脂であ
る。そして、第１図に示される回路基板４は、以
下のようにして製造される。[First Embodiment] FIG. 1 shows a first embodiment, in which 1 is an insulating substrate, and a wiring pattern 2a made of a metal film (for example, copper foil) 2 is formed on the surface of the insulating substrate 1. A wiring pattern 3a made of conductive resin 3 is further laminated on the surface of this wiring pattern 2a. The conductive resin 3 forming the wiring pattern 3a is a photocurable conductive resin in which conductive particles are mixed into a resin that hardens in response to light. The circuit board 4 shown in FIG. 1 is manufactured as follows.
即ち、第２図に示すように絶縁基板１の上面に被
着された金属膜２の表面全体に前記導電性樹脂３
を塗布したのち、その導電性樹脂３の表面に所望
のパターンを形成した光学マスク（図示せず）を
介して光を照射し、この光学マスクのパターン形
状に対応させて前記導電性樹脂３を硬化させ、未
硬化の導電性樹脂３ｂの領域を現像処理によつて
除去し、導電性樹脂３で形成される配線パターン
３ａを形成する。That is, as shown in FIG.
After coating the conductive resin 3, light is irradiated through an optical mask (not shown) having a desired pattern formed on the surface of the conductive resin 3, and the conductive resin 3 is coated in a manner corresponding to the pattern shape of the optical mask. The conductive resin 3b is cured, and a region of the uncured conductive resin 3b is removed by a development process, thereby forming a wiring pattern 3a formed of the conductive resin 3.
このようにして、導電性樹脂３を用いて前記配
線パターン３ａが第２図に示す如く表面に形成さ
れた金属膜２は、次に前記配線パターン３ａをレ
ジストに用いて前記金属板２をエツチング処理
し、前記配線パターン３ａに同じパターン形状で
前記金属膜２で形成された配線パターン２ａを同
位置において前記絶縁基板１上に形成する。この
状態を示すのが第１図である。したがつて、この
配線パターン２ａは前記導電性樹脂３をレジスト
として形成されたが、このレジストは導電性を有
しているので、前記導電性樹脂３を前記配線パタ
ーン２ａの表面に残したままの状態で他の部品と
電気的に接続させることができる。よつて、前記
導電性樹脂３の除去工程が不用になる。 In this way, the wiring pattern 3a is formed on the surface of the metal film 2 using the conductive resin 3 as shown in FIG. 2. Next, the metal plate 2 is etched using the wiring pattern 3a as a resist. A wiring pattern 2a formed of the metal film 2 and having the same pattern shape as the wiring pattern 3a is formed on the insulating substrate 1 at the same position. FIG. 1 shows this state. Therefore, this wiring pattern 2a is formed using the conductive resin 3 as a resist, but since this resist has conductivity, the conductive resin 3 is left on the surface of the wiring pattern 2a. It can be electrically connected to other parts in this state. Therefore, the step of removing the conductive resin 3 becomes unnecessary.
なお、前記導電性樹脂３に用いられる樹脂とし
ては、光に感応して硬化する樹脂に限らず、例え
ば電子ビームあるいはエツクス線などの放射エネ
ルギーに感応して硬化する樹脂を用いることがで
きる。 Note that the resin used for the conductive resin 3 is not limited to a resin that cures in response to light, but may also be a resin that cures in response to radiant energy such as an electron beam or an X-ray.
［考案の効果］
この考案は以上詳細に説明したように、絶縁基
板の表面に形成される配線パターンを、放射エネ
ルギーに感応して硬化する導電性樹脂をフオトレ
ジストとして用いて形成させたことにより、この
導電性樹脂で形成されるパターン自体が導電体で
あるので、絶縁基板に形成される配線パターンの
形成プロセスがきわめて簡略化できる。[Effects of the invention] As explained in detail above, this invention is based on the fact that the wiring pattern formed on the surface of the insulating substrate is formed using a conductive resin that hardens in response to radiant energy as a photoresist. Since the pattern formed from this conductive resin is itself a conductor, the process for forming the wiring pattern on the insulating substrate can be extremely simplified.
第１図及び第２図は第１実施例を示し、第１図
は第２図に示す金属膜をエツチングした状態の回
路基板の断面図、第２図は金属膜の表面に導電性
樹脂をパターニングした状態の断面図である。
１，５……絶縁基板、３……導電性レジスト、
２ａ，３ａ……配線パターン。
1 and 2 show the first embodiment, FIG. 1 is a cross-sectional view of the circuit board with the metal film etched as shown in FIG. 2, and FIG. FIG. 3 is a cross-sectional view of a patterned state. 1, 5... Insulating substrate, 3... Conductive resist,
2a, 3a... Wiring pattern.
Claims (1)
樹脂に導電性粒子が混入され、電気部品を電気的
に接続する導電性樹脂とが積層された配線パター
ンが、絶縁基板の表面に形成されていることを特
徴とする回路基板。 A wiring pattern is formed on the surface of an insulating substrate, in which a metal film and a conductive resin, which is made by mixing conductive particles into a resin that hardens in response to radiation energy and electrically connects electrical components, are laminated. A circuit board characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986154993U JPH0514542Y2 (en) | 1986-10-09 | 1986-10-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986154993U JPH0514542Y2 (en) | 1986-10-09 | 1986-10-09 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6361176U JPS6361176U (en) | 1988-04-22 |
| JPH0514542Y2 true JPH0514542Y2 (en) | 1993-04-19 |
Family
ID=31075291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986154993U Expired - Lifetime JPH0514542Y2 (en) | 1986-10-09 | 1986-10-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0514542Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009302581A (en) * | 2009-09-28 | 2009-12-24 | Kyocera Corp | Multilayer wiring board |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50112764A (en) * | 1974-02-18 | 1975-09-04 | ||
| JPS59114889A (en) * | 1982-12-21 | 1984-07-03 | 富士通株式会社 | Method of forming conductor pattern |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58164130U (en) * | 1982-04-27 | 1983-11-01 | 帝国通信工業株式会社 | switch circuit board |
-
1986
- 1986-10-09 JP JP1986154993U patent/JPH0514542Y2/ja not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50112764A (en) * | 1974-02-18 | 1975-09-04 | ||
| JPS59114889A (en) * | 1982-12-21 | 1984-07-03 | 富士通株式会社 | Method of forming conductor pattern |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6361176U (en) | 1988-04-22 |
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