JPH0413841B2 - - Google Patents
Info
- Publication number
- JPH0413841B2 JPH0413841B2 JP60204747A JP20474785A JPH0413841B2 JP H0413841 B2 JPH0413841 B2 JP H0413841B2 JP 60204747 A JP60204747 A JP 60204747A JP 20474785 A JP20474785 A JP 20474785A JP H0413841 B2 JPH0413841 B2 JP H0413841B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- conductors
- independent resistance
- fine pitch
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004020 conductor Substances 0.000 claims description 70
- 239000000758 substrate Substances 0.000 claims description 30
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 238000009966 trimming Methods 0.000 claims description 6
- 239000000523 sample Substances 0.000 claims description 3
- 239000011295 pitch Substances 0.000 description 26
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Non-Adjustable Resistors (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、各種電子機器に使用される複数個の
独立抵抗回路を1ブロツク化した独立抵抗ネツト
ワークに関するものであり、微細ピツチ独立抵抗
回路の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an independent resistance network in which a plurality of independent resistance circuits used in various electronic devices are combined into one block, and relates to the production of fine pitch independent resistance circuits. It is about the method.
従来の技術
近年、各種電子機器の軽薄短小化の動きは著し
いものがあり、受動素子としての抵抗について
も、チツプ化や複合ネツトワーク化によつて、実
装密度が大幅に向上している。特に、複数個の抵
抗を同一絶縁基板上に形成した抵抗ネツトワーク
については、端子間ピツチ2.54mm、1.78mm、1.27
mmピツチへと縮少化すると共に、チツプ形多端子
抵抗ネツトワークやミニフラツトパツケージなど
低背化された製品が求められている。BACKGROUND ART In recent years, there has been a remarkable movement towards making various electronic devices lighter, thinner, shorter and smaller, and the packaging density of resistors as passive elements has also been greatly improved due to the use of chips and complex networks. In particular, for resistor networks in which multiple resistors are formed on the same insulating substrate, the pitch between terminals is 2.54mm, 1.78mm, 1.27mm.
With the shrinking of the pitch to mm, there is a demand for products with lower profile such as chip-type multi-terminal resistor networks and mini-flat packages.
以下、図面を参照しながら、上述したような従
来の抵抗ネツトワークにおける独立抵抗回路パタ
ーンについて説明を行う。 The independent resistor circuit pattern in the conventional resistor network as described above will be explained below with reference to the drawings.
第4図は従来の独立抵抗回路パターンを示すも
のである。第4図において、1は絶縁基板、2は
絶縁基板1上に複数個形成された導体、3は相対
する前記導体2間に形成された抵抗体である。 FIG. 4 shows a conventional independent resistance circuit pattern. In FIG. 4, 1 is an insulating substrate, 2 is a plurality of conductors formed on the insulating substrate 1, and 3 is a resistor formed between the conductors 2 facing each other.
以上のように構成された独立抵抗回路パターン
は、必要に応じて導体2に検針を立てることによ
り、両端の抵抗値を測定しながら、レーザートリ
ミングを行うものである。さらに、導体2部には
リード端子(図示せず)を挿入した後、半田付け
を施すことによつて、プリント基板との接続を行
うものである。 The independent resistance circuit pattern configured as described above is used for laser trimming while measuring the resistance value at both ends by setting a probe on the conductor 2 as necessary. Further, a lead terminal (not shown) is inserted into the conductor 2 portion and then soldered to connect it to the printed circuit board.
発明が解決しようとする問題点
しかしながら、このような構成では、ピツチ間
隔の微細化を図るためには、第4図において導体
2、抵抗体3の幅寸法及びそれらの間隔を縮める
以外に方法はなく、下記の理由により、量産化が
困難であつた。すなわち、第1に導体2の幅寸法
を縮小した場合、レーザー検針ランドのスペース
が充分にとれず、レーザー検針の接触不良が発生
する。第2に抵抗体3の幅寸法及びその間隔を縮
小した場合、パターン形成時の印刷ズレ及びレー
ザー修正時のレーザービーム照射位置の寸法余裕
がなく、隣接する抵抗体にレーザービームが照射
され、所望のトリミング抵抗値が得られなくな
る。Problems to be Solved by the Invention However, in such a configuration, in order to make the pitch spacing finer, there is no other way than shortening the width dimensions of the conductor 2 and the resistor 3 and the spacing between them as shown in FIG. However, mass production was difficult for the following reasons. That is, firstly, when the width dimension of the conductor 2 is reduced, there is not enough space for the laser meter reading land, resulting in poor contact of the laser meter reading. Second, when the width dimension of the resistor 3 and the interval between them are reduced, there is no dimensional margin for the laser beam irradiation position during printing misalignment during pattern formation and laser correction, and the laser beam is irradiated onto adjacent resistors, resulting in the desired trimming resistance value cannot be obtained.
前記のように、従来の構成では導体、抵抗体の
幅寸法及び間隔寸法を単に縮めるだけでは、ピツ
チ間隔の小さいものを得ることは、非常に困難で
あるという問題点を有していた。 As mentioned above, the conventional configuration has the problem that it is very difficult to obtain small pitch intervals by simply reducing the width and spacing of the conductor and resistor.
本発明は前記欠点に鑑み、レーザー修正検針用
の導体電極ランドのスペースが充分に得られ、か
つレーザービームの照射位置の寸法余裕が確保で
きる微細ピツチ独立抵抗回路の製造方法を提供す
ることを目的とするものである。 In view of the above-mentioned drawbacks, an object of the present invention is to provide a method for manufacturing a fine pitch independent resistance circuit, which can provide sufficient space for conductor electrode land for laser correction meter reading and ensure dimensional margin for the laser beam irradiation position. That is.
問題点を解決するための手段
この目的を達成するために本発明の微細ピツチ
独立抵抗回路の製造方法は、絶縁基板上に抵抗体
の両端電極を結ぶ方向と同一方向となるように複
数個の導体を設けるとともに、その導体に複数個
の抵抗体の両端電極を接続して複数個の独立抵抗
回路を構成し、この独立抵抗回路間で互いに最近
傍に位置する抵抗体が千鳥状となるようにかつ各
導体が絶縁基板の相対向する両端部に引き出され
るように独立抵抗回路を多段に配置して微細ピツ
チ独立抵抗回路部を構成し、かつ分割用スリツト
を介して前記絶縁基板と隣接した第1、第2のダ
ミー絶縁基板上に前記導体にそれぞれ接続するよ
うに第1、第2のコモン導体及びレーザー修正検
針用の第1、第2の導体電極ランド群とを有する
ダミーランド部を設け、前記微細ピツチ独立抵抗
回路部の各導体のうち端から奇数番目の導体は第
1のコモン導体及び第2の導体電極ランド群に接
続し、偶数番目の導体は第1の導体電極ランド群
及び第2のコモン導体に接続することにより微細
ピツチ独立抵抗回路パターンを構成し、この微細
ピツチ独立抵抗回路パターンにおいて、前記第
1、第2のコモン導体と第1、第2の導体電極ラ
ンド群に検針を当てて前記抵抗体の抵抗値が所望
の値となるようにレーザートリミングを行つた後
に、前記分割用スリツトで分割することを特徴と
するものである。Means for Solving the Problems In order to achieve this object, the method for manufacturing a fine pitch independent resistor circuit of the present invention involves forming a plurality of resistors on an insulating substrate in the same direction as connecting the electrodes at both ends of the resistor. A conductor is provided, and the electrodes at both ends of a plurality of resistors are connected to the conductor to form a plurality of independent resistance circuits, and the resistors located closest to each other are staggered between the independent resistance circuits. In addition, independent resistance circuits are arranged in multiple stages so that each conductor is drawn out to opposite ends of the insulating substrate to constitute a fine pitch independent resistance circuit section, and the conductor is connected to the insulating substrate adjacent to the insulating substrate through a dividing slit. A dummy land portion having first and second common conductors and first and second conductor electrode land groups for laser correction meter reading is provided on the first and second dummy insulating substrates so as to be connected to the conductor, respectively. Among the conductors of the fine pitch independent resistance circuit section, the odd-numbered conductors from the end are connected to the first common conductor and the second conductor electrode land group, and the even-numbered conductors are connected to the first conductor electrode land group. and a second common conductor to form a fine pitch independent resistance circuit pattern, and in this fine pitch independent resistance circuit pattern, the first and second common conductors and the first and second conductor electrode land groups are connected to each other. The resistor is laser trimmed so that the resistance value of the resistor becomes a desired value by applying a probe to the resistor, and then the resistor is divided by the dividing slit.
作 用
この方法によれば、各独立抵抗回路を千鳥状に
多段に配置構成しておりかつ抵抗体のレーザー修
正は抵抗体の電極方向に対して交差する方向に行
うので、隣接する抵抗体をレーザービームで切断
することなく、レーザービームの寸法精度余裕を
充分に確保した上で、微細ピツチの独立抵抗回路
を形成することができる。また、ダミー絶縁基板
上にコモン導体とレーザー修正検針用の導体電極
ランド群を設けることにより、ダミー絶縁基板上
において導体電極ランドの数が抵抗体の個数の半
分で済むため微細ピツチであるにもかかわらず、
レーザー修正検針用の導体電極ランドのスペース
が充分に得られ、レーザー検針の接触不良が発生
するといつたことはなくなることとなる。Operation According to this method, each independent resistance circuit is arranged in multiple stages in a staggered manner, and the laser correction of the resistor is performed in a direction crossing the electrode direction of the resistor, so that adjacent resistors are Without cutting with a laser beam, it is possible to form an independent resistance circuit with fine pitches while ensuring a sufficient dimensional accuracy margin of the laser beam. In addition, by providing a common conductor and a group of conductor electrode lands for laser correction meter reading on the dummy insulating board, the number of conductor electrode lands on the dummy insulating board can be half the number of resistors, making it possible to achieve fine pitch. regardless of,
Sufficient space is provided for the conductive electrode land for laser corrected meter reading, and contact failures in laser meter reading will no longer occur.
実施例
以下本発明の一実施例について、図面を参照し
ながら説明する。Embodiment An embodiment of the present invention will be described below with reference to the drawings.
第1図は、本発明の一実施例における微細ピツ
チ独立抵抗回路パターンを示すものである。第1
図において、4は絶縁基板、5は絶縁基板4上に
複数個形成された導体、6は相対する前記導体5
間に形成された抵抗体である。ここで、抵抗体6
の両端電極を結ぶ方向と同一方向となるように導
体5は接続されている。これらの抵抗体6と導体
5から構成された複数個の独立抵抗回路は3段構
造の千鳥状に配列されており、最近傍に位置する
抵抗体6が千鳥状となつており、微細ピツチ独立
抵抗回路部を構成している。7a,7bは絶縁基
板4に隣接した第1、第2のダミー絶縁基板、8
a,8bはダミー絶縁基板7上に形成された第
1、第2のコモン導体で、各独立抵抗回路の導体
5の両端のうちどちらか一方が第1、第2のコモ
ン導体8a,8bのいずれかに共通に接続されて
いる。9a,9bは第1、第2のダミー絶縁基板
7a,7b上に形成されたレーザー修正検針用の
第1、第2の導体電極ランドであり、各独立抵抗
回路の導体5の残りの端部が個々に接続形成され
ており、ダミーランド部を構成している。10は
前記微細ピツチ独立抵抗回路部を備えた絶縁基板
4と前記ダミーランド部を備えたダミー絶縁基板
7a,7bとを隔てている分割用スリツトであ
る。さらに詳しく記載すると、前記微細ピツチ独
立抵抗回路の各導体5のうち端から奇数番目の導
体5は第1のコモン導体8a及び第2の導体電極
ランド7bに接続し、偶数番目の導体は第1の導
体電極ランド7a及び第2のコモン導体8bに接
続するように構成されている。 FIG. 1 shows a fine pitch independent resistor circuit pattern in one embodiment of the present invention. 1st
In the figure, 4 is an insulating substrate, 5 is a plurality of conductors formed on the insulating substrate 4, and 6 is the opposing conductor 5.
A resistor is formed between the two. Here, resistor 6
The conductor 5 is connected in the same direction as the direction in which the electrodes at both ends of the conductor 5 are connected. A plurality of independent resistance circuits constituted by these resistors 6 and conductors 5 are arranged in a staggered three-stage structure, and the resistors 6 located closest to each other are arranged in a staggered manner, so that minute pitches are independent. It constitutes a resistance circuit section. 7a and 7b are first and second dummy insulating substrates adjacent to the insulating substrate 4;
a and 8b are first and second common conductors formed on the dummy insulating substrate 7, and one of the ends of the conductor 5 of each independent resistance circuit is connected to the first and second common conductors 8a and 8b. Commonly connected to either. 9a and 9b are first and second conductive electrode lands for laser correction meter reading formed on the first and second dummy insulating substrates 7a and 7b, and the remaining ends of the conductor 5 of each independent resistance circuit are individually connected and form a dummy land portion. Reference numeral 10 denotes a dividing slit which separates the insulating substrate 4 provided with the fine pitch independent resistance circuit section from the dummy insulating substrates 7a and 7b provided with the dummy land sections. More specifically, among the conductors 5 of the fine pitch independent resistance circuit, the odd-numbered conductors 5 from the end are connected to the first common conductor 8a and the second conductor electrode land 7b, and the even-numbered conductors are connected to the first common conductor 8a and the second conductor electrode land 7b. The conductor electrode land 7a and the second common conductor 8b are connected to each other.
以上のように構成された微細ピツチ独立抵抗回
路パターンは、第1、第2のコモン導体8a,8
b及びレーザー修正検針用の第1、第2の導体電
極ランド9a,9bに検針を立てることにより、
抵抗値を測定しながら、所望の抵抗値を得るため
に抵抗体6にレーザートリミングを行うものであ
る。このトリミングの方向は、抵抗体6の電極方
向に対して交差する方向である。よつてトリミン
グの際、その方向に隣接するように抵抗体6は配
置されていないため、レーザービームにより抵抗
体6を切断してしまうことはない。次に、分割用
スリツト10部において基板分割を行い第1、第
2のダミー絶縁基板7a,7bを除去し、微細ピ
ツチ独立抵抗回路を形成する。 The fine pitch independent resistor circuit pattern configured as described above includes the first and second common conductors 8a and 8.
b, and by placing meter readings on the first and second conductive electrode lands 9a and 9b for laser correction meter reading,
While measuring the resistance value, laser trimming is performed on the resistor 6 in order to obtain a desired resistance value. The direction of this trimming is a direction that intersects with the direction of the electrodes of the resistor 6. Therefore, during trimming, the resistor 6 is not placed adjacent to the trimmer in that direction, so the resistor 6 is not cut by the laser beam. Next, the substrate is divided at the dividing slit 10, the first and second dummy insulating substrates 7a and 7b are removed, and fine pitch independent resistance circuits are formed.
第2図は、第1、第2のダミー絶縁基板7a,
7bを除去して得られた微細ピツチ独立抵抗回路
である。また、第1図及び第2図において、11
は前記導体5から延長された外部信号取出し用電
極であり、実装時の端子部としての役割を果たす
ものである。 FIG. 2 shows first and second dummy insulating substrates 7a,
This is a fine pitch independent resistance circuit obtained by removing 7b. In addition, in Figures 1 and 2, 11
is an electrode for taking out an external signal extending from the conductor 5, and serves as a terminal portion during mounting.
第3図は本発明による微細ピツチ独立抵抗回路
の実装方法の一例を示すものである。第3図にお
いて、12はプリント基板を示し、13は前記プ
リント基板12上に形成された銅箔である。14
はプリント基板12に取付けられた半田付け部で
ある。 FIG. 3 shows an example of a method for mounting a fine pitch independent resistance circuit according to the present invention. In FIG. 3, 12 represents a printed circuit board, and 13 represents a copper foil formed on the printed circuit board 12. In FIG. 14
is a soldered part attached to the printed circuit board 12.
なお、本実施例において、独立抵抗回路は3段
構造の千鳥状の配列としたが、部品寸法の許す限
り、4段千鳥、5段千鳥状配列としてもよいこと
は言うまでもない。 In this embodiment, the independent resistance circuits are arranged in a staggered three-stage structure, but it goes without saying that a four-stage staggered or five-stage staggered arrangement may be used as long as the component dimensions permit.
発明の効果
以上のように本発明は、絶縁基板上の導体と前
記導体間に形成された抵抗体とを備えた独立抵抗
回路を、千鳥状に多段に配置構成することによ
り、隣接する抵抗体をレーザービームで切断する
ことなく、レーザービーム照射位置の寸法精度余
裕を充分に確保した上で、微細ピツチ独立抵抗回
路を形成することができる。また、分割用スリツ
トで前記絶縁基板と隔てられたダミー絶縁基板上
に、コモン導体とレーザー修正検針用の導体電極
ランドを設けることにより、微細ピツチにかかわ
らず、レーザー修正検針用の導体電極ランドのス
ペースが充分に得られ、絶縁基板上の導体のピツ
チの2倍の寸法余裕でレーザー修正検針用の導体
電極ランドが構成できる。このためレーザー検針
の接触不良が発生するといつたことはなくなるも
のである。Effects of the Invention As described above, the present invention has an arrangement in which independent resistance circuits each including a conductor on an insulating substrate and a resistor formed between the conductors are arranged in multiple stages in a staggered manner. It is possible to form a fine pitch independent resistance circuit without cutting with a laser beam, while ensuring a sufficient dimensional accuracy margin for the laser beam irradiation position. In addition, by providing a common conductor and a conductor electrode land for laser correction meter reading on a dummy insulating substrate separated from the insulating substrate by a dividing slit, it is possible to make the conductor electrode land for laser correction meter reading independent of minute pitches. Sufficient space is obtained, and a conductor electrode land for laser correction meter reading can be configured with a dimensional margin twice the pitch of the conductor on the insulating substrate. For this reason, the occurrence of contact failure in laser meter reading will no longer occur.
このように本発明の製造方法により、その実用
的効果は大なるものがある。 As described above, the manufacturing method of the present invention has great practical effects.
第1図は本発明の一実施例における微細ピツチ
独立抵抗回路パターンを説明する拡大平面図、第
2図は同抵抗回路パターンのダミー絶縁基板を除
去した後の構成を示す平面図、第3図は本発明に
よつて得られる微細ピツチ独立抵抗回路の実装例
を示す断面図、第4図は従来の独立抵抗パターン
の平面図である。
4……絶縁基板、5……導体、6……抵抗体、
7a,7b……第1、第2のダミー絶縁基板、8
a,7b……第1、第2のコモン導体、9……7
a,7bレーザー修正検針用の第1、第2の導体
電極ランド、10……分割用スリツト、11……
外部信号取出し用電極、12……プリント基板、
13……銅箔、14……半田付け部。
FIG. 1 is an enlarged plan view illustrating a fine pitch independent resistor circuit pattern according to an embodiment of the present invention, FIG. 2 is a plan view showing the configuration of the same resistor circuit pattern after removing the dummy insulating substrate, and FIG. 4 is a sectional view showing an example of mounting a fine pitch independent resistance circuit obtained by the present invention, and FIG. 4 is a plan view of a conventional independent resistance pattern. 4... Insulating substrate, 5... Conductor, 6... Resistor,
7a, 7b...first and second dummy insulating substrates, 8
a, 7b...first, second common conductor, 9...7
a, 7b First and second conductive electrode lands for laser correction meter reading, 10... slit for division, 11...
External signal extraction electrode, 12... printed circuit board,
13...Copper foil, 14...Soldering part.
Claims (1)
同一方向となるように複数個の導体を設けるとと
もに、その導体に複数個の抵抗体の両端電極を接
続して複数個の独立抵抗回路を構成し、この独立
抵抗回路間で互いに最近傍に位置する抵抗体が千
鳥状となるようにかつ各導体が絶縁基板の相対向
する両端部に引き出されるように独立抵抗回路を
多段に配置して微細ピツチ独立抵抗回路部を構成
し、かつ分割用スリツトを介して前記絶縁基板と
隣接した第1、第2のダミー絶縁基板上に前記導
体にそれぞれ接続するように第1、第2のコモン
導体及びレーザー修正検針用の第1、第2の導体
電極ランド群とを有するダミーランド部を設け、
前記微細ピツチ独立抵抗回路部の各導体のうち端
から奇数番目の導体は第1のコモン導体及び第2
の導体電極ランド群に接続し、偶数番目の導体は
第1の導体電極ランド群及び第2のコモン導体に
接続することにより微細ピツチ独立抵抗回路パタ
ーンを構成し、この微細ピツチ独立抵抗回路パタ
ーンにおいて、前記第1、第2のコモン導体と第
1、第2の導体電極ランド群に検針を当てて前記
抵抗体の抵抗値が所望の値となるようにレーザー
トリミングを行つた後に、前記分割用スリツトで
分割することを特徴とする微細ピツチ独立抵抗回
路の製造方法。1. A plurality of conductors are provided on an insulating substrate in the same direction as the direction in which the electrodes at both ends of the resistor are connected, and the electrodes at both ends of the plurality of resistors are connected to the conductors to form a plurality of independent resistance circuits. The independent resistance circuits are arranged in multiple stages so that the resistors located closest to each other between the independent resistance circuits are staggered and each conductor is drawn out to opposite ends of the insulating substrate. First and second common conductors constituting a fine pitch independent resistance circuit section and connected to the conductor on first and second dummy insulating substrates adjacent to the insulating substrate through dividing slits, respectively. and a dummy land portion having first and second conductive electrode land groups for laser correction meter reading,
Among the conductors of the fine pitch independent resistance circuit section, the odd-numbered conductors from the end are the first common conductor and the second common conductor.
The even-numbered conductors are connected to the first conductor electrode land group and the second common conductor to form a fine pitch independent resistance circuit pattern, and in this fine pitch independent resistance circuit pattern, , after applying a probe to the first and second common conductors and the first and second conductor electrode land groups and performing laser trimming so that the resistance value of the resistor becomes a desired value, the dividing A method for manufacturing a fine pitch independent resistance circuit characterized by dividing it with slits.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60204747A JPS6265306A (en) | 1985-09-17 | 1985-09-17 | Fine pitch independent resistance circuit pattern |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60204747A JPS6265306A (en) | 1985-09-17 | 1985-09-17 | Fine pitch independent resistance circuit pattern |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3098787A Division JPH04226002A (en) | 1991-04-30 | 1991-04-30 | Fine pitch independent resistance circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6265306A JPS6265306A (en) | 1987-03-24 |
JPH0413841B2 true JPH0413841B2 (en) | 1992-03-11 |
Family
ID=16495657
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60204747A Granted JPS6265306A (en) | 1985-09-17 | 1985-09-17 | Fine pitch independent resistance circuit pattern |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6265306A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10938303B2 (en) | 2007-08-10 | 2021-03-02 | Rohm Co., Ltd. | Driving device |
JP2009044081A (en) | 2007-08-10 | 2009-02-26 | Rohm Co Ltd | Driver |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50129960A (en) * | 1974-03-20 | 1975-10-14 |
-
1985
- 1985-09-17 JP JP60204747A patent/JPS6265306A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50129960A (en) * | 1974-03-20 | 1975-10-14 |
Also Published As
Publication number | Publication date |
---|---|
JPS6265306A (en) | 1987-03-24 |
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