JPH01179389A - Manufacture of circuit wiring board - Google Patents
Manufacture of circuit wiring boardInfo
- Publication number
- JPH01179389A JPH01179389A JP62336427A JP33642787A JPH01179389A JP H01179389 A JPH01179389 A JP H01179389A JP 62336427 A JP62336427 A JP 62336427A JP 33642787 A JP33642787 A JP 33642787A JP H01179389 A JPH01179389 A JP H01179389A
- Authority
- JP
- Japan
- Prior art keywords
- holes
- hole
- circuit
- wiring board
- dividing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000010304 firing Methods 0.000 claims description 3
- 238000007639 printing Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 16
- 238000005192 partition Methods 0.000 abstract 4
- 229910000679 solder Inorganic materials 0.000 abstract 1
- 238000000034 method Methods 0.000 description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 239000012466 permeate Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002003 electrode paste Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は厚膜回路基板の製造方法乞こ関し、特に、複数
のスルーホールを直線上に形成し、回路基板の完成後、
これらスルーホールに沿って形成された分割溝によって
回路基板を分割する回路配線基板の製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a thick film circuit board, and in particular, a method for manufacturing a thick film circuit board, in which a plurality of through holes are formed in a straight line, and after the circuit board is completed.
The present invention relates to a method of manufacturing a circuit wiring board in which the circuit board is divided by dividing grooves formed along these through holes.
［従来の技術］
従来、その上にチップ部品等を搭載していわゆるハイブ
リッドＩＣ等を構成するための厚膜回路基板は、アルミ
ナなどの絶縁基板上にスクリーン印刷等によって導体パ
ターンを形成し、次いで抵抗体やパッシベーション膜の
形成を行い、この回路基板を完成する。また、この様な
厚膜基板の小形化、さらにはハイブリッドＩＣの小形化
を進めるため、基板の両生面に各々形成された導体を接
続する、いわゆるスルーホールが利用される。この場合
の一手法として、例えばこれらのスルーホールを、厚膜
基板の完成後に分割する為に用いる、いわゆる分割用溝
に沿って形成すること多い。[Prior Art] Conventionally, thick film circuit boards on which chip components and the like are mounted to form so-called hybrid ICs, etc., are produced by forming a conductor pattern on an insulating substrate such as alumina by screen printing or the like. A resistor and a passivation film are formed to complete this circuit board. Further, in order to advance the miniaturization of such thick film substrates and further miniaturization of hybrid ICs, so-called through holes are used to connect conductors formed on both sides of the substrate. As one method in this case, for example, these through holes are often formed along so-called dividing grooves used to divide the thick film substrate after completion.
［発明が解決しようとする問題点］
しかしながら、前記従来の方法では、分割用溝がスルー
ホールを連絡するよう、連続して形成されており、この
スルーホール部に電極用ペーストを用いて印刷する場合
、その印刷時にペーストが毛細管現象により前記分割用
溝に沿って浸透し、隣接するスルーホール電極にまで達
してしまい、隣接するスルーホール間がショートしてし
まう。これを避けるため、前記の従来の方法においては
、スルーホールのピッチを小さくできず、基板の小形化
が図れないという問題点があった。すなわち、ショート
を避けるためには、前記スルーホールのピッチを広げる
必要があるが、そうした場合、回路基板の小形化が不可
能であるという問題点を有していた。[Problems to be Solved by the Invention] However, in the conventional method, the dividing grooves are continuously formed so as to connect the through holes, and the electrode paste is printed on the through holes. In this case, during printing, the paste permeates along the dividing groove due to capillary action and reaches adjacent through-hole electrodes, resulting in a short circuit between adjacent through-holes. In order to avoid this, the conventional method described above has the problem that the pitch of the through holes cannot be reduced, and the size of the substrate cannot be reduced. That is, in order to avoid short circuits, it is necessary to widen the pitch of the through holes, but in such a case, there is a problem in that it is impossible to downsize the circuit board.
そこで、本発明は、前記の従来技術における問題点に鑑
み、基板を分割するための分割用溝上に複数形成したス
ルーホール間のピッチを狭め、もって回路基板の小形化
が可能で、しかも回路の信頼性の高い回路配線基板の製
造方法を提供することにある。Therefore, in view of the problems in the prior art described above, the present invention narrows the pitch between the plurality of through holes formed on the dividing grooves for dividing the board, thereby making it possible to downsize the circuit board and making it possible to reduce the size of the circuit. An object of the present invention is to provide a method for manufacturing a highly reliable circuit wiring board.
［問題を解決するための手段］
即ち、前記本発明の目的は、グリーンシート１′の所定
の直線上に複数のスルーホール４を設け、該スルーホー
ル４を結ぶ前記直線上に分割溝３を形成し、前記グリー
ンシートｂ導電ペーストを印刷し、同シート１′を焼成
した後、これを前記分割溝３に沿って分割する回路配線
基板の製造方法において、前記グリーンシート１′に形
成される分割溝３を、隣接する前記スルーホール４．１
４の間で一部分断したことを特徴とする回路配線基板の
製造方法によって達成される。[Means for Solving the Problem] That is, the object of the present invention is to provide a plurality of through holes 4 on a predetermined straight line of the green sheet 1', and to form dividing grooves 3 on the straight line connecting the through holes 4. In the method for manufacturing a circuit wiring board, the conductive paste is formed on the green sheet 1', the conductive paste is printed on the green sheet 1', the sheet 1' is fired, and then the same is divided along the dividing groove 3. The dividing groove 3 is connected to the adjacent through hole 4.1.
This is achieved by a method of manufacturing a circuit wiring board characterized in that the circuit wiring board is partially divided between four parts.
［作 用コ
すなわち、前記本発明の回路配線基板の製造方法によれ
ば、回路基板を形成するグリーンシートの主面上に形成
される分割溝３は、隣接する前記スルーホール４の間で
、その一部が分断されていることにより、スルーホール
４に導電ペーストを用いてスルーホール電極を印刷する
場合に、毛細管現象により前記分割用溝３．１３に沿っ
て浸透するペーストの進行が分割溝の端部で停止する。[Function] That is, according to the method for manufacturing a circuit wiring board of the present invention, the dividing grooves 3 formed on the main surface of the green sheet forming the circuit board are formed between the adjacent through holes 4. Because the part is divided, when printing a through-hole electrode using conductive paste in the through-hole 4, the progress of the paste that permeates along the dividing groove 3.13 due to capillary action is prevented. Stop at the end.
従って、隣接するスルーホール電極が互いにつながって
、ショートするようなことがない。Therefore, there is no possibility that adjacent through-hole electrodes will be connected to each other and cause a short circuit.
［実 施 例］
以下、本発明の実施例について、添付の図面を参照しな
がら説明する。[Examples] Examples of the present invention will be described below with reference to the accompanying drawings.
まず、第２図において、アルミナ等の絶縁材を所定の形
状に成型し、焼成前のいわゆるグリーンシート１°を形
成する。この主面上の上端辺付近には、小形化するため
に、配線電極パターンや厚膜抵抗体等を形成した後、そ
の端辺２９を切り取るための、いわゆる分割用溝３が形
成され、さらにこの分割用溝３に沿って複数のスルーホ
ール４が形成されている。そして、図からも明らかなよ
うに、この分割用溝３は、隣接するスルーホール４の間
に形成されており、さらにその中間部において分断され
ている。First, in FIG. 2, an insulating material such as alumina is molded into a predetermined shape to form a so-called green sheet 1° before firing. A so-called dividing groove 3 is formed near the upper edge of the main surface to cut the edge 29 after forming a wiring electrode pattern, a thick film resistor, etc. in order to reduce the size. A plurality of through holes 4 are formed along this dividing groove 3. As is clear from the figure, this dividing groove 3 is formed between adjacent through holes 4, and is further divided at an intermediate portion thereof.
このように形成された前記グリーンシート１′は、乾燥
し、焼成され、さらにその主面上に例えば導電性ペース
トを所定の配線パターンや厚膜抵抗あるいはパッシベー
ション膜などを印刷し、これを乾燥し、焼成して回路配
線基板を完成する。The green sheet 1' thus formed is dried and fired, and further, a conductive paste is printed on its main surface with a predetermined wiring pattern, a thick film resistor, a passivation film, etc., and this is dried. , and bake to complete the circuit wiring board.
第１図は、前記グリーンシート１′の乾燥、焼成後の回
路基板１の上端辺付近にスルーホール４を複数個形成し
、この周面に導電性ペーストを印刷してスルーホール電
極を形成した状態を示している。この図にも示すように
、スルーホール電極のスルーホールパッド部４１は、前
記分割用溝３が設けられた部分にまで形成され、前記溝
３の分断部会には形成されていない。この様にその途中
が分断された前記分割用溝２により、前記スルーホール
４の周辺に印刷される導電性ペーストは、既述の毛細管
現象により、前記分割用溝３に沿って浸透し、隣接する
スルーホール電極がショートしてしまうことがない。FIG. 1 shows that a plurality of through holes 4 are formed near the upper edge of a circuit board 1 after drying and firing the green sheet 1', and a conductive paste is printed on the periphery of the through holes 4 to form through hole electrodes. It shows the condition. As shown in this figure, the through-hole pad portion 41 of the through-hole electrode is formed up to the portion where the dividing groove 3 is provided, and is not formed in the dividing portion of the groove 3. The conductive paste printed around the through-hole 4 by the dividing groove 2 which is divided in the middle in this way permeates along the dividing groove 3 due to the above-mentioned capillary phenomenon, and The through-hole electrode will not be short-circuited.
また、これにより回路基板１の分別用溝３の上に形成さ
れるスルーホール４のピッチを十分に狭くすることが出
来る。もって、電極間の距離の短縮が出来、回路基板１
の小形化が可能になる。また、スルーホール電極のショ
ートの危険性が大きく低減される。Furthermore, this allows the pitch of the through holes 4 formed above the sorting grooves 3 of the circuit board 1 to be sufficiently narrow. As a result, the distance between the electrodes can be shortened, and the circuit board 1
can be made smaller. Also, the risk of short circuiting the through-hole electrodes is greatly reduced.
以下、本発明のより具体的な実施例について説明する。More specific examples of the present invention will be described below.
まず、前記回路基板１は、板厚が０．６３５ｍｍ、基板
上端辺付近に形成した前記分割用溝３の堝深さは０．２
５ｍｍであった。一方、上記回路基板１の上端辺付近に
複数個形成した上記スルーホール４の径は０．５ｍｍφ
、スルーホール４のピッチ（Ｕ１４ ｊ妾するスルーホ
ール４の中心間の距離）は１．３ｍｍであり、さらに、
スルーホール部に形成されるスルーホールパッド４１は
縦横１．０ｍｍ、その隣接するパッド間隔は０．３ｍｍ
であった。そして、分断された前記分割用溝３の距離は
前記パッド間隔と同様に、０．３ｍｍであった。First, the circuit board 1 has a board thickness of 0.635 mm, and the depth of the dividing groove 3 formed near the top edge of the board is 0.2 mm.
It was 5 mm. On the other hand, the diameter of the plurality of through holes 4 formed near the upper edge of the circuit board 1 is 0.5 mmφ.
, the pitch of the through holes 4 (the distance between the centers of the through holes 4) is 1.3 mm, and further,
The through-hole pad 41 formed in the through-hole part has a length and width of 1.0 mm, and an interval between adjacent pads is 0.3 mm.
Met. The distance between the divided dividing grooves 3 was 0.3 mm, similar to the pad spacing.
以上の寸法と条件にて作られたアルミナ基板１の上に、
スルーホールパッド４１を印刷し、これを焼成した。こ
の結果、前記スルーホールパッド４１の間隔は０．２６
ｍｍと、ショートの危険性が極めて低い間隔が得られた
。なおここで、スルーホールパッド４１の間隔は０．２
６ｍｍと、前記隣接するパッド間隔０．３ｍｍよりも小
さくなるのは、前記導体パターンを前記基板１上に印刷
する場合に生じるいわゆるペーストダレと呼ばれる現象
による。On the alumina substrate 1 made with the above dimensions and conditions,
A through-hole pad 41 was printed and fired. As a result, the spacing between the through-hole pads 41 is 0.26
A spacing of 1 mm was obtained with an extremely low risk of short-circuiting. Note that the interval between the through-hole pads 41 is 0.2
The reason why the spacing between adjacent pads is 6 mm, which is smaller than the spacing between adjacent pads of 0.3 mm, is due to a phenomenon called paste sag that occurs when the conductive pattern is printed on the substrate 1.
他方、この比較例を第３図に示す。すなわち、既述の従
来技術と同様にアルミナ基板１上に、途中を中断しない
連続的な分割用溝３”を設け、この分割用溝３′上にス
ルーホール４を複数設けた。そして、スルーホールパッ
ド４１をやはり前記と同様の寸法、条件にてアルミナ基
板１の上に印刷し、その後これを焼成して回路基板を得
た。しかしながら、この様にして作られた回路基板では
、隣接するスルーホールパッド４１間が、その間に形成
された前記分割用溝３′によってショートしてしまう。On the other hand, this comparative example is shown in FIG. That is, as in the prior art described above, a continuous dividing groove 3'' with no interruption in the middle is provided on the alumina substrate 1, and a plurality of through holes 4 are provided on this dividing groove 3'. Hole pads 41 were printed on the alumina substrate 1 with the same dimensions and conditions as above, and then fired to obtain a circuit board.However, in the circuit board made in this way, the adjacent A short circuit occurs between the through-hole pads 41 due to the dividing groove 3' formed therebetween.
すなわち、アルミナ基板１上に導体印刷パターンを用い
てスルーホールパッド４１の印刷を行なう場合、印刷さ
れた導電性ペーストが毛細管現象によって浸透し、隣接
するスルーホールパッド４１がつながってしまう。That is, when through-hole pads 41 are printed on alumina substrate 1 using a printed conductor pattern, the printed conductive paste permeates through capillary action and adjacent through-hole pads 41 are connected.
次に、本発明をさらに積層型混成集積回路装置の製造方
法に適用した例を示す。第４図（ａ）にも示すように、
基板１１上には複数に分割するための分割用溝１３が形
成されており、この分割用溝１３上に複数のスルーホー
ル１４が形成されており、このスルーホール１４にはス
ルーホールパッド１４１が設けられている。この他の実
施例では、相隣接するスルーホール１４の間隔は前記の
実施例に比べて大きく、その為、前記第１図に示す実施
例とは異なり、前記分割用溝１３は隣接するスルーホー
ルパット１４１の中間部に設けられる。言い換えれは、
前記分割用溝１３は基板上の複数箇所で分断されて形成
されている。Next, an example will be shown in which the present invention is further applied to a method for manufacturing a stacked hybrid integrated circuit device. As shown in Figure 4(a),
A dividing groove 13 for dividing the substrate 11 into a plurality of parts is formed on the substrate 11. A plurality of through holes 14 are formed on the dividing groove 13, and a through hole pad 141 is formed in the through hole 14. It is provided. In this other embodiment, the distance between adjacent through holes 14 is larger than in the above embodiment, and therefore, unlike the embodiment shown in FIG. It is provided in the middle part of the pad 141. In other words,
The dividing groove 13 is divided and formed at a plurality of locations on the substrate.
この様にして製造された回路基板１１は、その後、第４
図（ｂ）に示すように、前記の分別用溝１３に沿って分
割される。そして、これを重ね合わせ、コの字状の接続
部材１５により、分割されたスルーホールパッド１４１
を半田などによって互いに接続する。The circuit board 11 manufactured in this way is then
As shown in Figure (b), it is divided along the aforementioned separation groove 13. Then, the through-hole pads 141 are overlapped and divided by the U-shaped connecting member 15.
are connected to each other by soldering or the like.
［発明の効果コ
以上の説明からも明らかなようζこ１９本発明に成る回
路配線基板の製造方法によれは、回路基板の分割用溝に
沿って形成されるスルーホール電極のピッチを小さくす
ることが出来ることから、より小形化が可能な回路配線
基板が提供できる。また、隣接するスルーホール電極の
ショートが低減され、回路の信頼性の向上を図ることが
できる。[Effects of the Invention] As is clear from the above explanation, the method for manufacturing a circuit wiring board according to the present invention reduces the pitch of through-hole electrodes formed along the dividing grooves of the circuit board. Therefore, a circuit wiring board that can be further miniaturized can be provided. Furthermore, short circuits between adjacent through-hole electrodes are reduced, and the reliability of the circuit can be improved.
第１図及び第２図は本発明の一実施例である回路配線基
板の製造過程を示すための基板の一部平面図であり、第
３図は本発明になる回路配線基板を従来技術に比較する
ための前記従来技術の回路配線基板を示す一部平面図で
あり、そして第４図（ａ）及び（ｂ）は本発明を前記の
他にさらに積層型混成集積回路装置に適用した例を示す
図である。
１・・・基板 １′・・・グリーンシート ３・・・分
割用溝 ４・・・スルーホール ４１・・・スルーホー
ルパッド1 and 2 are partial plan views of a circuit wiring board according to an embodiment of the present invention to show the manufacturing process, and FIG. 3 is a partial plan view of a circuit wiring board according to the present invention according to the prior art. 4 is a partial plan view showing the circuit wiring board of the prior art for comparison, and FIGS. 4(a) and 4(b) show an example in which the present invention is applied to a stacked hybrid integrated circuit device in addition to the above. FIG. 1... Board 1'... Green sheet 3... Dividing groove 4... Through hole 41... Through hole pad
Claims (1)
ールを設け、該スルーホールを結ぶ前記直線上に分割溝
を形成し、前記グリーンシート上に導電ペーストを印刷
し、同シートを焼成した後、これを前記分割溝に沿って
分割する回路配線基板の製造方法において、前記グリー
ンシートに形成される分割溝を、隣接する前記スルーホ
ールの間で一部分断したことを特徴とする回路配線基板
の製造方法。(1) After providing a plurality of through holes on a predetermined straight line of a green sheet, forming dividing grooves on the straight line connecting the through holes, printing a conductive paste on the green sheet, and firing the sheet. , a method of manufacturing a circuit wiring board in which the green sheet is divided along the dividing groove, wherein the dividing groove formed in the green sheet is partially divided between the adjacent through holes. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62336427A JPH01179389A (en) | 1987-12-30 | 1987-12-30 | Manufacture of circuit wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62336427A JPH01179389A (en) | 1987-12-30 | 1987-12-30 | Manufacture of circuit wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01179389A true JPH01179389A (en) | 1989-07-17 |
Family
ID=18299017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62336427A Pending JPH01179389A (en) | 1987-12-30 | 1987-12-30 | Manufacture of circuit wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01179389A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03116890A (en) * | 1989-09-29 | 1991-05-17 | Nippon Dempa Kogyo Co Ltd | Printed wiring board |
| US6221193B1 (en) | 1999-01-20 | 2001-04-24 | International Business Machines Corporation | Defect reduction method for screened greensheets and article produced therefrom |
| JP2007165516A (en) * | 2005-12-13 | 2007-06-28 | Matsushita Electric Ind Co Ltd | Method of manufacturing chip type network electronic component |
| JP2007173867A (en) * | 2007-03-20 | 2007-07-05 | Koa Corp | Substrate for electronic component, and method for manufacturing electronic component |
-
1987
- 1987-12-30 JP JP62336427A patent/JPH01179389A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03116890A (en) * | 1989-09-29 | 1991-05-17 | Nippon Dempa Kogyo Co Ltd | Printed wiring board |
| US6221193B1 (en) | 1999-01-20 | 2001-04-24 | International Business Machines Corporation | Defect reduction method for screened greensheets and article produced therefrom |
| JP2007165516A (en) * | 2005-12-13 | 2007-06-28 | Matsushita Electric Ind Co Ltd | Method of manufacturing chip type network electronic component |
| JP2007173867A (en) * | 2007-03-20 | 2007-07-05 | Koa Corp | Substrate for electronic component, and method for manufacturing electronic component |
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