JPS6215688A - Memory device for frequency distribution - Google Patents

Abstract

PURPOSE:To attain the statistic processing of data at a high speed and with small memory capacity by combining a memory device with a counter circuit and regarding an input signal as an address signal of the memory device. CONSTITUTION:A memory device 1 loads the data on the corresponding address to a counter circuit 3 with a reading signal (c) sent from a timing generating circuit 2. Then the counter circuit 3 counts up data by one with count-up pulses (e) sent from the circuit 2. The counted-up data is written on the device 1 with a writing signal (a) sent from the circuit 2. Thus the input data is redarded as an address signal and the data on the address same as that used in the reading mode of the device 1 is counted up. This count-up action is repeated until a desired number of samples are obtained. Thus the frequency distribution of the input data is stored in the device 1.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a frequency distribution memory device for measuring the distribution of input data.

BACKGROUND OF THE INVENTION In recent years, with remarkable advances in computer technology, the signals handled have become faster, and peripheral circuits such as signal processing circuits are also required to have faster processing speeds. Conventionally, when measuring the frequency distribution of input data with variations (for example, pulse width measured by a counter circuit) and performing statistical processing, a CPU 21 as shown in FIG.
Input buffer 22. In a computer device configured with the memory device 23, the input buffer 722
There is a method of calculating statistical values such as maximum value, minimum value, average value and two variance values by sequentially performing arithmetic processing on the data taken into U21. However, since this processing method takes time to perform arithmetic processing, the input data must be slower than the arithmetic processing time. A second method for handling data at higher speeds is to use the computer shown in Figure 3 to temporarily store all input data in the memory device and process it after data collection is completed. (For a similar example, data collection from analog-to-digital converters, see Transistor Technology, February 1984, 319-3.
(page 22).

Problems to be Solved by the Invention The first conventional method requires a small memory capacity, but because statistical processing is performed each time data is input, it cannot handle data faster than the processing time as described above. The second method can handle data faster than the first method, but requires memory capacity equal to the number of data to be sampled.
This had the problem of requiring a huge amount of memory.

The present invention has been made in view of the above, and an object of the present invention is to provide a frequency distribution memory device that enables high-speed statistical processing of data with a small memory capacity.

Means for Solving the Problems In order to solve the above problems, the present invention treats an input signal as an address signal of a memory device and reads data at a corresponding address of the memory device to a counter circuit every time an input control signal is input. It counts up and writes to the corresponding address in the memory device again.

Operation According to the above-described configuration, the present invention has a small memory capacity of (input data length) x (maximum degree quantity), and since it accesses the memory device in a node-like manner, the access of the memory device is It is possible to handle data at speeds equivalent to the speed.

Embodiment FIG. 1 is a block diagram showing an embodiment of the frequency distribution memory device of the present invention. In FIG. 1, 1 is a memory device;
2 is a timing generation circuit for generating a timing signal in response to input of an input control signal; 3 is a counter circuit for counting up data read from the memory device; and 4 is a circuit for converting an address signal to the memory device into input data. 5 is a signal switching circuit for the data signal of the memory device; 6 is a signal switching circuit for the read control signal and write control signal of the memory device; 11 is the memory device. 12 is a data bus of the memory device; a is a write control signal from the timing circuit; b is a write control signal to the memory device; C is a read control signal from the timing circuit; d is a read control signal to the memory device. The control signal e is a count up signal.

The operation of this embodiment configured as above will be described below. The signal switching circuits 4, 5, and 6 are circuits that switch access to the memory device 1 between the data input side and the data output side (for example, a computer device) using signal control signals. To explain the data storage operation of the memory device 1, first, the control of the memory device 1 is set to the data output side to clear all data in the memory device 1, and then the control of the memory device 1 is transferred to the data input side. , the frequency distribution of data at that point in time is recorded on the memory device 1 each time an input control signal is input.

FIG. 2 shows timing pulses generated by the timing generation circuit 2. In FIG. When the input control signal is input, the timing generation circuit 2 sends a read signal C to the memory device 1. At this time, since the input data is an address signal for the memory device 1, the memory device 1 outputs data at the corresponding address to the data bus 12 by inputting the read signal C.

The read signal C also serves as a load signal for the counter circuit 3, and the data of the memory device 1 output to the data bus 12 is loaded into the counter circuit 3 at the same time. Next, the timing circuit 2 sends a count up pulse e to the counter circuit 3. This pulse causes the counter circuit 3 to count up the data by one. Subsequently, the timing circuit 2 sends a write signal a to the memory device 1 and the counter circuit 3,
The data counted up by the counter circuit 3 is written into the memory device 1. By holding the input data from data read to data write, the input data is regarded as an address signal, and the data at the same address as when it was read from the memory device 1 is counted up. By repeating this for the required number of samples, the frequency distribution of the input data is stored in the memory device 1. As described above, memory device 1
The frequency distribution of input data stored in can be read out by a computer device or the like by switching the control of the memory device 1 to the data output side using a signal control signal, and can be subjected to statistical processing or the like.

Effects of the Invention As described above, the present invention includes a memory device, a counter circuit, a timing generation circuit, and a signal switching circuit, and when collecting data, input data is regarded as an address signal of the memory device, and the memory device is switched every time an input control signal is input. By configuring the data at the corresponding address to be read out to a counter circuit, counted up, and then written to the corresponding address in the memory device again, the capacity of the memory device can be reduced to (input data length) x (maximum count). Since the memory device is accessed by hardware, it is possible to collect data at a speed equivalent to the access speed of the memory device, and obtain the excellent effect of being able to obtain a frequency distribution on the memory device. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a frequency distribution memory device in one embodiment of the present invention, FIG. 2 is a timing diagram of a timing generation circuit, and FIG. 3 is a block diagram of a general computer device showing a conventional example. be. 1... Memory device, 2... Timing generation circuit, 3... Counter circuit, 4, 5.6...
... Signal switching circuit, 11 ... Address bus of memory device, 12 ... Data bus of memory device, a, b ... Write control signal, c, d. ...
...Read control signal, e...Count up signal. Name of agent: Patent attorney Toshio Nakao (1st person)
Figure II 2

Claims (3)

[Claims] (1) A memory device that writes or reads data in an area according to an address signal, and a counter circuit that inputs and counts up the data of the memory device, and includes an input data line and an address signal line of the memory device. The data input from the input data line is regarded as an address signal of the memory device, and each time an input control signal is input, the data at the corresponding address of the memory device is read out to the counter circuit and counted up, and the data is read out from the memory device again. A frequency distribution memory device characterized by writing to a corresponding address of the device. (2) Reading and counting up data in the memory device,
Regarding writing, the present invention is characterized by comprising a timing generation circuit for reading and writing data from a memory device, inputting/outputting data to a counter circuit, and generating a count-up control signal. The frequency distribution memory device according to item 1. (3) The frequency distribution memory device according to claim 1, further comprising a switching circuit for switching the input/output destination of data regarding reading and writing of data in the memory device.