JPH0227487A - Circuit for counting/storing data number - Google Patents

Abstract

PURPOSE:To easily count and store the number of data by successively reading the respective data in a data memory means when a data line is connected to an address line, applying them to a counting result memory means, reading number data from an address, and updating and storing them. CONSTITUTION:A data line 106 is switching-connected to an address line 107 by a switching means 101, and the respective data stored into a data memory means 102 are given to a counting result memory means 103 as address information. The number data are read from the said address at every given address, a counting means 104 updates them, and an updating result is stored into the said address of the counting result memory means 103. Thus, when the multibit pattern data typically such as picture data and voice data are processed, the existing number of arbitrary bit patterns can be promptly and easily counted.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a circuit that counts and stores the number of pieces of data, and is particularly applicable to an image memory device that A/D converts a video signal and stores it in a memory tC. The present invention relates to a circuit that counts and stores the number of data stored in a memory IC.

[Prior Art] Image binarization is often performed to separate an object and a background from a grayscale image. Conventional binarization methods include, for example, creating a histogram of the gradations of the original image, setting thresholds at the valleys or inflection points of the histogram, and performing binarization based on the magnitude relationship with the threshold. There is.

FIG. 3 is a diagram showing a conventional circuit configuration used for creating a histogram. In FIG. 3, data line 205
and address lines 206 are clearly separated, and each of these lines includes CPO 201, program memory 202 . Data memory 203 and counting result memory 20
4 are connected. The CPU 201 performs a series of operations described below in accordance with a processing procedure stored in advance in the program memory 202. That is, data memory 203
, bit pattern data indicating the degree of shading of the image for each pixel is stored, and the CPU 201 transfers desired data in the data memory 203 to the address line 20.
6 and taken by data line 205. The CPU 201 compares and determines the size of the bit pattern of the imported data with the previously imported bit pattern, and stores the currently imported data in the counting result memory 204 that stores count data in ascending or descending order of bit pattern data. Add 1 to the number data stored at the address to be processed. Transfer the above data to data memory 2
By performing this on all data within 03, a histogram is obtained.

[Problems to be Solved by the Invention] As mentioned above, in the conventional method, a comparative judgment is made for each bit pattern data, so it takes time to process, so there is a problem that the processing speed is slow, and the comparative judgment is slow. There was a problem in that the processing was complicated.

Therefore, the main object of the present invention is to provide a circuit that counts and stores the number of pieces of data without comparing and determining bit pattern data.

[Means for Solving the Problems] A circuit for counting and storing the number of data according to the present invention includes a data storage means connected to a data line and storing data to be counted, and a counter for counting the number of data. counting result storage means connected to the address line for storing the counting results of the counting means; and counting result storage means for connecting the data line connected to the data storage means to the address line connected to the counting result storage means. When the data line and the address line are connected by the switching means, each data stored in the data storage means is sequentially given to the counting result storage means as address information, and for each given address, the corresponding address is and counting control means for reading out the number data from the counting means, updating it by giving it to the counting means, and storing the updated result at the corresponding address of the counting result storage means.

[Operation] In this invention, when the data line and the address line are connected by the switching means, each data stored in the data storage means is sequentially read out and given as address information to the number result storage means. For each address, the number data is read from that address and updated by the counting means,
The updated result is stored at the corresponding address in the counting result storage means.

[Embodiment of the Invention] FIG. 1 is a diagram showing a circuit configuration of an embodiment of the invention. In FIG. 1, an address line 106 and a data line 107, each used for external output, are connected to one end of a switching circuit 101 and a data memory 102. The other end of the switching circuit 101, the counting result memory 1
Internal buses 108 and 109 are connected to 03 and counter circuit 104. In the normal operation mode, the switching circuit 101 connects the address line 106 to the internal bus 108.
and the data line 107 is connected to the internal bus 109
In the data counting mode, a switching operation is performed so that the data line 107 is connected to the internal bus 108. The data memory 102 stores bit pattern data to be counted.

The counter circuit 104 counts bit pattern data stored in the data memory 102. The count result memory 103 stores the count results of the counter circuit 104. Internal buses 108 and 109 are buses having a number of lines defined by the capacity and bit width of data memory 102. address line 10
6 and data line 107 are connected to a timing signal generation circuit 105 that controls the output of data.

Moreover, the above-mentioned switching circuit 101. Data memory 102, count result memory 103, and counter circuit 104 are controlled by a control signal from timing signal generation circuit 105.

FIG. 2 is a diagram for explaining various signals. In particular, FIG. 2(a) shows the signal 30 appearing on the address line 106.
1, FIG. 2B shows the signal 302 appearing on the data line 107, and FIG. 2C shows the signal 303 appearing on the internal bus 109.

Next, the operation of an embodiment of the present invention will be described with reference to FIGS. 1 and 2. In the circuit shown in FIG. 1, it is assumed that the data memory 102 stores bit pattern data and groups to be counted, and each area of the counting result memory 103 has 0 as an initial value. Assume that it has been written.

When performing a counting operation, switching circuit 101 switches in response to a predetermined control signal from timing signal generating circuit 105, and connects data line 107 and internal bus 108. Next, one bit pattern data of the data memory 102 is read out using the address information 304 applied to the address line 106. Data 305 read from data memory 102 is applied to address lines of count result memory 103 via data line 107 and internal bus 108. Next, the data in the count result memory 103 is read out based on the signal 305 currently applied to the address line. The data 306 read from the counting result memory 103 is sent to the counter circuit 10 via an internal bus 109.
given to 4.

The counter circuit 104 takes in the applied data 306, adds 1 to it, and sends it out again to the internal bus 109. Since 0 is stored in the counting result memory 103 as an initial value, the data sent out is data representing 1. Data to be sent out is indicated by 307.

Data 307 sent from the counter circuit 104 is written into the count result memory 103 based on the signal 305 currently applied to the address line. That is, the updated count data is written into the count result memory 103 at the same address as the one read last time. For example, regarding the data X in the data memory 102, the number data is stored at the address X in the count result memory 103.

By repeating the above-described series of operations for all data in the data memory 102 without duplication, the number of bit pattern data stored in the data memory 102 can be counted and stored for each bit pattern.

When reading the counting results from the outside, the switching circuit 101 connects the address line 106 and the internal bus 108, and connects the data line 107 and the internal bus 109. Thereby, the number data stored in the counting result memory 103 can be read out to the outside as in the conventional case.

[Effects of the Invention] As described above, according to the present invention, the data line and the address line are switched and connected by the switching means, and each data stored in the data storage means is stored in the counting result storage means as address information. At the same time, for each given address, the number data is read from the address and updated by the counting means, and the updated result is stored in the corresponding address of the counting result storage means. When handling a large number of bit pattern data, it is possible to quickly count the number of existing bit patterns, and the program can be simplified because there is no need to compare and discriminate as in the past. can.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention. FIG. 2 is a diagram for explaining various signals in FIG. 1. FIG. 3 is a diagram showing a conventional circuit configuration used for creating a histogram. In the figure, 101 is a switching circuit, 102 is a data memory, 103 is a counting result memory, 104 is a counter circuit, 1
05 is a timing signal generation circuit, 106 is an address line, 107 is a data line, 108 and 109 are internal buses, 301 is a signal appearing on the address line, 302
is a signal appearing on the data line, 303 is a signal appearing on the internal bus, 304 is address information, 305 is data read from the data memory, 306 is data given to the counter circuit, 307 is given from the counter circuit to the counting result memory Show data. Figure 2 1 Figure 3 Figure 206: Address level line

Claims (1)

[Claims] Data storage means connected to a data line and storing data to be counted; counting means for counting the number of pieces of data; and connected to an address line and storing counting results of the counting means. counting result storage means for connecting the data line connected to the data storage means to the address line connected to the counting result storage means; switching means for connecting the data line and the address line connected to the counting result storage means; When the address line is connected, each piece of data stored in the data storage means is sequentially given to the counting result storage means as address information, and count data is read from the address for each given address to A circuit for counting and storing the number of pieces of data, comprising a counting control means for updating the data by applying it to the counting means and storing the updated result at the corresponding address of the counting result storage means.