JPH05197778A - Logical simulation system - Google Patents

Abstract

PURPOSE:To provide a means for rapidly executing the simulation of a large scale logical device by storing logical circuit information in an external storage device, dividing the logical circuit information into logical blocks to store the divided information in a main storage device and executing simulation in each logical block. CONSTITUTION:This logical simulation system consists of the external storage for collectively storing a logical circuit, the main storage for executing the simulation of the logical circuit in each of logical blocks BL1 to BL5 and logical simulation softwares such as a map table 302 to be used for the simulation of each logical block in the main storage, an inter-block event table, an input signal value event table, and an output signal value table. Since the external storage device is used, the simulation of a large scale logical circuit exceeding the capacity of the main storage can be executed, the number of accesses to the external storage device can be reduced by independently managing the variable information of the blocks BL1 to BL5 to be simulated and rapid simulation can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has logic circuit information in an external storage device, stores the logic circuit information in a main storage device by dividing it into logical block units, and executes a simulation in each logical block unit. By doing so, the present invention relates to a method for executing simulation of a large-scale logic device at high speed.

[0002]

2. Description of the Related Art In the conventional logic simulation method, logic to be simulated is collectively expanded on a main storage device to perform logic simulation. Regarding an external storage device, there is an example in which it is used as a means for storing change signal information of an execution result during simulation.

Further, a method is used in which the target logic is divided into the number of processors that execute the simulation, is assigned to each processor, and the simulation is advanced in synchronization with other processors. As a method of this, there is a method in which the logic to be simulated is divided into the number of storage devices, and the divided logic is simulated by a smaller number of processors than the number of storage devices. As an example of this method, Japanese Patent Laid-Open No.
There is a logic simulation method as described in Japanese Patent No. 184176.

[0004]

In the above-mentioned prior art, when handling large-scale logic in which the logic circuit information to be simulated exceeds the capacity of the main memory device, the main memory device is expanded in mounting and the memory device is sized. It may be necessary to increase the number of units, but the cost required for these will increase. Therefore, it is necessary to use an external storage device capable of collectively storing large-scale logic circuit information, and to provide means for simulating the logic block units. However, since the access time of a magnetic disk or the like used as the external storage is much longer than that of the main storage, it is important to reduce the number of accesses to reduce the cause of performance degradation. In order to solve the above problems, an object of the present invention is to provide a logic simulation method that enables high-speed simulation of a large-scale logic device by using an external storage device having a huge capacity. That is.

[0005]

According to the present invention, in order to achieve the above object, logic circuit information to be simulated is divided by a parameter card or the like designated from the outside using the amount of logic information, and further, By associating the connection information and the signal value information with each other, it is decided to divide the portion in which the simulation result changes and the portion in which the change does not occur. further,
A portion in which stored information such as signal value change information for propagating a signal change between the respective logic elements at the time of executing the logic simulation is arranged to be resident in the main storage device, and the portion of the divided logical information is changed. The connection information that does not occur is stored in the external storage device, and the connection information of the logical blocks divided from the external storage device at each simulation unit time is fetched into the main memory for simulation, and the signal that has changed is generated. When the value in the main memory is updated for the value, the next logical block is loaded after the simulation of one logical block is completed, and the simulation is performed sequentially, the event (signal change) at the simulation unit time disappears. , A method of advancing the simulation unit time and repeating the simulation.

[0006]

In this case, since the information of the logic block to be simulated is not changed in the connection contents itself by separately managing the signal value, it is necessary to return it to the external memory at the end of the simulation of the logic block. Therefore, the number of accesses to the external storage device can be reduced.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a flow chart of the logic simulation execution procedure of the present invention.

In process 101, the capacity of the logical information that can be stored in the main memory designated by the parameter card and the simulation end time are read, and the amount of logical information that can be stored in the main memory is calculated. In step 103, the logical information is read, the logical information is divided into main storage capacity units to create a map table, and in step 104 each logical block is output to the external storage device. Process 103
The map table created in (1) is a table for managing the address conversion of the logical block, which occurs when the logical circuit information is loaded from the external storage device to the main storage device in logical block units.

Next, the simulation execution phase is entered. In step 105, the simulation execution time is set to 0.
In step 106, signal value input information from the outside of the simulation target logic circuit set by test data or the like is input to the input signal value event table before the simulation of all logic blocks at each time. Event information corresponding to each logical block is registered in each map table.

In step 107, the simulation target block is fetched from the external storage device to the main storage device in accordance with the map table. At this time, when an event from another logic block or a logic block having no input signal value event is detected on the map table, those logic blocks are not loaded.

After the logic block to be simulated is stored in the main memory device, in step 108, another logic block is changed to the simulation target logic block by using the map table and the event table between logic blocks. The propagating event is extracted, the process 109 extracts the input signal value event to be input to the simulation target logic block, and the process 110 extracts the event.
8. The event extracted in the process 109 is read out as the simulation target event.

In step 111, a signal change between logic blocks and an input signal value from the outside are used to perform a simulation for each logic block. In step 112, an event to a logic block other than the logic block being processed is detected. Whether or not it has occurred is determined from the logical information address of the map table. If an event has occurred in a region other than the logical block being processed, the process proceeds to step 113. If not, the process proceeds to step 114.

In step 113, the simulation of each logic element is performed.
The signal change propagation information other than the simulation target logic block generated as a result of the simulation is calculated as the inter-block event from the map table, and the inter-block event table is calculated as the event of the relevant logic block. Register with.

In process 114, the output value of the simulation result performed in process 111 is stored in the output signal value table corresponding to each logic information, and at the same time, each logic element for outputting the simulation result is output. The output change signal value is output to external storage.

Next, in process 115, processes 110 to 114 are repeated for the logic block designated by the map table until there are no events in the simulation target logic block.

In step 116, when the simulation of one logical block to be simulated is completed, the simulation unit time simulation is performed for all the logical blocks registered in the map table to process the next logical block. The process 107 to the process 116 are repeated until the end of the process.

Steps 106 to 117 are repeated until the designated simulation end time. Finally,
In process 119, the simulation result registered in the external storage is edited and output.

According to the above procedure, the simulation is executed for each divided logical block.

FIG. 2 shows a logic expression table having logic information of the simulation target device.

The function 201 holds the function of the element, and the signal value information 202 has the relative address of the signal value table having the signal value of the element. The element connection information 203 has information on an element to which an event of the element should be propagated, that is, an event propagation destination relative address. By this table, when the signal value changes, that is, when an event occurs, the event of the element can be propagated to another element.
Further, it is possible to determine whether the event is in the same logical block or an event to another logical block by the relative address of the event propagation destination.

FIG. 3 is a diagram for explaining the address conversion of the divided logical blocks in order to realize the simulation in logical block units.

Logical block 30 stored in an external storage device
The map table 302 having the relative address and data length of each logical block of 1 and the address in the main memory when the logical block is stored in the main memory is set in the descending order with the data length as a key. Sort. The order of the logical blocks loaded to the main memory is determined as follows.

A logical block designated to be resident in the main memory is arranged in the resident area by the parameter card.

Logical blocks for which main memory resident is not designated by the parameter card are arranged in the non-resident area in order from the longest data length.

As described above, the order of the logical blocks loaded in the main memory is determined.

FIG. 4 shows the map table 3 described with reference to FIG.
This is a detailed description of the operation of 02 on the main memory. In order to enable the simulation in logical block units,
The function of the map table 402 existing in the main memory 401 is represented by the relationship between a certain simulation time and another table.

The map table 402 stores the logical circuit information existing in the external storage by the method described with reference to FIG. 3 in units of logical blocks, the relative address of all logical blocks and the data length, and the data length. It was sorted in descending order.

The map table 402 has the contents of data including the external storage address 403 and the data length 404, a main storage address 405, a resident flag 406, an event table address 407 between logical blocks, and an input signal. It has a value event table address 408 and an output signal value table address 409, which correspond to respective logic blocks.
The contents of each map table will be described below.

In the main memory address 405, the head address of the logical block expanded in the main memory is registered.

The resident flag 406 indicates a logical block resident in the main memory, and distinguishes between a logical block arranged in the resident area and a logical block loaded in the non-resident area.

If there is an event propagation from another logical block, the inter-logical block event table address 407 corresponds to the event group corresponding to the relevant logical block in the event addresses stored in the inter-logical block event table 411. Stores the address of the first record. Set to zero if there is no event from another logic block.

Input signal value Event table address 41
2 indicates the address of the first record of the event group corresponding to the corresponding logical block in the event address stored in the input signal value event table 412 when there is signal value input information given by test data or the like. Store. Set to zero if there are no input signal value events. The output signal value table address 409 is the address of the head record of the output signal value group corresponding to the relevant logic block among the output values of the elements of all the logic blocks stored in the output value table 413. Store.

[0034]

According to the present invention, it is possible to divide the logic circuit information in the external storage device into a certain logical unit and load it into the main storage device for logic simulation. It is possible to realize a logic simulation of logic that exceeds the storage capacity of memory.

Furthermore, by making the information updated during the execution of the logic simulation resident in the main storage device, it becomes unnecessary to store the logical information after the execution of the logic simulation in the external storage device. Since the number of accesses to such an external storage device can be halved, there is an effect that the entire logic simulation time is significantly shortened.

Further, by using the semiconductor memory device as the external memory device, a higher speed simulation can be realized.

[Brief description of drawings]

FIG. 1 is a processing flow chart of the present invention.

[Fig. 2] Structure of logical expression table

FIG. 3 is a method for managing the load of logical blocks from external storage to main storage.

[Figure 4] Map table related diagram during simulation execution

[Explanation of symbols]

BLn: Indicates the allocation address of the logical block in the external storage in order from 1. MSBLn: Indicates the allocation address of the logical block in the internal storage in order from 1. BLEVTn: Indicates the allocation address of inter-block event table in order from 1. ISEVTn: Indicates the allocation address of the input signal value event table in order from 1. OSIGn: Indicates the allocation address of the output signal value table in order from 1.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Tomita 1 Horiyamashita, Hadano City, Kanagawa Prefecture Hitachi Computer Engineering Co., Ltd. (72) Yoshito Mizoue 1 Horiyamashita, Hadano City, Kanagawa Prefecture At the Tate Manufacturing Kanagawa Plant (72) Inventor Yoshiaki Kinoshita 1 Horiyamashita, Hadano City, Kanagawa Prefecture Inside the Hitate Manufacturing Kanagawa Plant

Claims (3)

[Claims] 1. A logic simulation method of using circuit description information of a logic circuit, simulating its operation, and outputting a result, means for dividing the logic circuit information into specific logic block units, and logic circuit information. Is stored in the external storage device, and means for storing the data from the external storage device to the main storage device in units of logical blocks divided in advance, and the simulation is performed in the logical block unit stored in the main storage device. A characteristic logic simulation method. 2. The simulation system according to claim 1, wherein the logical block information is divided into two pieces, information in which a value changes according to a result of simulation and information in which a value does not change, and information in which a value changes. A logic simulation characterized in that the logic circuit information of the simulated logic block is not stored in the external storage device at the end of the simulation for each logic block by resident only the main memory device. method. 3. The logic simulation system according to claim 1, wherein the simulation is performed by using an extended storage device using a memory element as an external storage device.