JPS6214953B2 - - Google Patents
Info
- Publication number
- JPS6214953B2 JPS6214953B2 JP10195179A JP10195179A JPS6214953B2 JP S6214953 B2 JPS6214953 B2 JP S6214953B2 JP 10195179 A JP10195179 A JP 10195179A JP 10195179 A JP10195179 A JP 10195179A JP S6214953 B2 JPS6214953 B2 JP S6214953B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon
- polycrystalline silicon
- gate electrode
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 27
- 230000005669 field effect Effects 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 4
- 239000003795 chemical substances by application Substances 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 34
- 235000012239 silicon dioxide Nutrition 0.000 description 17
- 239000000377 silicon dioxide Substances 0.000 description 17
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 239000000758 substrate Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 239000013078 crystal Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 238000001947 vapour-phase growth Methods 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
Description
【発明の詳細な説明】
本発明はシリコンゲート型電界効果トランジス
タに関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a silicon gate field effect transistor.
従来のシリコンゲート型電界効果トランジスタ
は、シリコン単結晶基板に熱酸化を施して得られ
る二酸化硅素膜をゲート絶縁膜とし、この絶縁膜
上には、気相成長法で被着させた多結晶シリコン
膜に３価あるいは５価の不純物を熱拡散等で浸入
させたゲート電極があり、また、ゲート電極は熱
拡散後に施す熱酸化で生成される二酸化硅素、あ
るいはガラス質の二酸化硅素で覆われているのが
一般的であつた。 In conventional silicon gate field effect transistors, the gate insulating film is a silicon dioxide film obtained by thermally oxidizing a silicon single crystal substrate, and polycrystalline silicon deposited by vapor phase growth is deposited on this insulating film. There is a gate electrode in which trivalent or pentavalent impurities are infiltrated into the film by thermal diffusion, etc., and the gate electrode is covered with silicon dioxide produced by thermal oxidation after thermal diffusion, or glassy silicon dioxide. It was common for there to be.
一方、金属（たとえばアルミニユーム）と上記
ゲート電極を、オーミツク接続をするために、ゲ
ート絶縁膜上の多結晶シリコンを覆う二酸化硅素
に写真蝕刻で開孔を設けることは、次の理由から
不可能であつた。 On the other hand, in order to make an ohmic connection between a metal (for example, aluminum) and the gate electrode, it is impossible to make holes by photolithography in the silicon dioxide covering the polycrystalline silicon on the gate insulating film for the following reasons. It was hot.
すなわち、上記多結晶シリコンの結晶粒径は、
熱拡散・熱酸化の熱処理で処理条件にも依存する
が、成長時の粒径より数倍から数十倍大きくな
り、結晶粒間に空隙が生じる。そのために上記開
孔を開けるための二酸化硅素のエツチング液（ガ
ス）が上記空隙から浸入して、ゲート絶縁膜をも
除去し、ゲート電極と基板を短絡させるからであ
る。 That is, the crystal grain size of the polycrystalline silicon is
Although it depends on the processing conditions during heat treatment such as thermal diffusion and thermal oxidation, the grain size becomes several to several tens of times larger than when grown, and voids are created between the crystal grains. This is because the silicon dioxide etching solution (gas) used to open the openings enters through the gaps, removing the gate insulating film and causing a short circuit between the gate electrode and the substrate.
そこで、ゲート電極をアルミニユーム等の金属
でオーミツク接続するためには、ゲート電極を形
成する多結晶シリコンをゲート絶縁膜外まで延長
してオーミツク接続用の領域を設ける必要があ
り、モノリシツク集積回路の集積度向上の妨げと
なつていた。 Therefore, in order to connect the gate electrode ohmicly with a metal such as aluminum, it is necessary to extend the polycrystalline silicon that forms the gate electrode to the outside of the gate insulating film to provide an area for the ohmic connection. This was an impediment to improving performance.
本発明の目的は従来のこの種のトランジスタの
上記欠点を除いた集積度の大きい電界効果トラン
ジスタを提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a highly integrated field effect transistor which eliminates the above-mentioned drawbacks of conventional transistors of this type.
本発明による電界効果トランジスタは、ゲート
電極を第１の多結晶シリコン膜−ゲート絶縁膜の
エツチング材でエツチングされない物質−第２の
多結晶シリコン膜の順で積層する領域と、第１の
多結晶シリコン膜−多結晶第２のシリコン膜で積
層される領域で構成することを特徴とし、ゲート
絶縁膜上のゲート電極からオーミツク導出を可能
ならしめて、半導体モノリシツク集積回路の集積
度を向上させることが可能となる。 The field effect transistor according to the present invention includes a region in which a gate electrode is laminated in the order of a first polycrystalline silicon film, a material that is not etched by the etching agent for the gate insulating film, and a second polycrystalline silicon film, and a first polycrystalline silicon film. It is characterized by being composed of a region laminated with a silicon film and a polycrystalline second silicon film, and enables ohmic derivation from the gate electrode on the gate insulating film, thereby improving the degree of integration of semiconductor monolithic integrated circuits. It becomes possible.
以下、本発明の一実施例について、製造工程を
示し乍ら、特徴を詳しく説明する。 Hereinafter, the features of an embodiment of the present invention will be described in detail while showing the manufacturing process.
Ｐ導電型単結晶基板１に熱酸化を施して厚さ１
μ程度の二酸化硅素膜２を全面に生成させた後、
写真蝕刻によつて短形状に基板面を露出させる。
（第１図）。再び、熱酸化を施して厚さ800(A)゜程
度のゲート絶縁膜となる二酸化硅素膜３を形成す
る。次に気相成長法によつて、厚さ2000(A)゜程度
の多結晶シリコン膜４、厚さ500Å程度の窒化硅
素膜５、厚さ500Å程度の二酸化硅素膜６を被着
する。（第２図）
写真蝕刻によつて、二酸化硅素膜６の一部７を
除いて除去し、二酸化硅素膜片７をマスクとし
て、沸点近くまで温めたリン酸液中で窒化硅素膜
５を除去し、多結晶シリコン面４を露出させる
と、窒化硅素膜片８を得る（第３，４図）。次
に、弗酸水溶液にて二酸化硅素膜片７を除去す
る。この際、多結晶シリコン膜４は、気相成長時
の結晶粒径を大きくする程の熱処理工程を経てお
らず、同膜４がマスクの働きをして二酸化硅素膜
３はエツチングされない。 A P conductivity type single crystal substrate 1 is thermally oxidized to a thickness of 1
After forming a silicon dioxide film 2 of about μ on the entire surface,
The substrate surface is exposed in a rectangular shape by photolithography.
(Figure 1). Thermal oxidation is performed again to form a silicon dioxide film 3 having a thickness of about 800 (A) and serving as a gate insulating film. Next, by vapor phase growth, a polycrystalline silicon film 4 with a thickness of about 2000 (A) degrees, a silicon nitride film 5 with a thickness of about 500 Å, and a silicon dioxide film 6 with a thickness of about 500 Å are deposited. (Fig. 2) The silicon dioxide film 6 is removed except for a part 7 by photolithography, and the silicon nitride film 5 is removed in a phosphoric acid solution heated to near its boiling point using the silicon dioxide film piece 7 as a mask. Then, by exposing the polycrystalline silicon surface 4, a silicon nitride film piece 8 is obtained (FIGS. 3 and 4). Next, the silicon dioxide film piece 7 is removed using a hydrofluoric acid aqueous solution. At this time, the polycrystalline silicon film 4 has not been subjected to a heat treatment process sufficient to increase the crystal grain size during vapor phase growth, and the silicon dioxide film 3 is not etched because the polycrystalline silicon film 4 acts as a mask.
再び、気相成長法に因つて厚さ4000（Å）程度
の多結晶シリコン膜９を全面に被着する。このと
き、窒化シリコン膜片８で覆われる領域外の多結
晶シリコン膜４の面は同膜９と接触する。（第５
図）
次に写真蝕刻を施して、ゲート電極となる領域
にPR膜１０を残す。プラズマエツチング法で多
結晶シリコン膜４，９を除去し、ゲート電極１
１，１２を得る（第６，７図）。プラズマエツチ
ング法では多結晶シリコンだけでなく、窒化硅素
も腐蝕できるから、PR膜１０は必ずしも窒化硅
素膜片７を第７図に見られる如く、包合する必要
はない。 Again, a polycrystalline silicon film 9 having a thickness of about 4000 (Å) is deposited over the entire surface using the vapor growth method. At this time, the surface of the polycrystalline silicon film 4 outside the region covered by the silicon nitride film piece 8 comes into contact with the same film 9. (5th
(Figure) Next, photolithography is performed to leave the PR film 10 in the area that will become the gate electrode. Polycrystalline silicon films 4 and 9 are removed by plasma etching, and gate electrode 1 is removed.
1 and 12 are obtained (Figures 6 and 7). Since the plasma etching method can corrode not only polycrystalline silicon but also silicon nitride, the PR film 10 does not necessarily need to encapsulate the silicon nitride film pieces 7 as shown in FIG.
次に、PR膜を除去した後、熱拡散（950℃、１
時間）で、リンを基板１中に浸入させた後、スチ
ーム雰囲気中で950℃、10分の熱酸化を施す。こ
のとき、基板中にＮ型半導体層のドレイン領域１
３、ソース領域１４が形成され、これらの領域は
厚さ5000Å程度の二酸化硅素膜１５，１６で覆わ
れる。また前述の熱拡散熱酸化の熱処理で、多結
晶シリコン片１１，１２にも、リンが拡散されて
全てＮ型半導体となると同時に、同片１１，１２
の境界はなくなり、ゲート電極１７を形成する。
尚、上記熱処理条件は、窒化硅素膜片８上の多結
晶シリコンが厚さ1000Å程度Ｎ型半導体として残
るように選択する。また、窒化膜片８直下にある
多結晶シリコン片１１の領域をより抵抗率の低い
Ｎ型半導体にするために、更に窒化ガス雰囲気中
で1000℃20分の熱処理を追加して、リンを多結晶
シリコン中で再拡散させてもよい（第８図）。 Next, after removing the PR film, thermal diffusion (950℃, 1
After infiltrating phosphorus into the substrate 1 (time), thermal oxidation is performed at 950° C. for 10 minutes in a steam atmosphere. At this time, the drain region 1 of the N-type semiconductor layer is placed in the substrate.
3. Source regions 14 are formed, and these regions are covered with silicon dioxide films 15 and 16 having a thickness of about 5000 Å. In addition, in the thermal diffusion thermal oxidation heat treatment described above, phosphorus is also diffused into the polycrystalline silicon pieces 11 and 12, and at the same time, the same pieces 11 and 12 become all N-type semiconductors.
The boundary of the gate electrode 17 is eliminated and the gate electrode 17 is formed.
The above heat treatment conditions are selected so that the polycrystalline silicon on the silicon nitride film piece 8 remains as an N-type semiconductor with a thickness of about 1000 Å. In addition, in order to make the region of the polycrystalline silicon piece 11 directly under the nitride film piece 8 into an N-type semiconductor with lower resistivity, heat treatment was additionally performed at 1000°C for 20 minutes in a nitride gas atmosphere to increase the amount of phosphorus. It may also be re-diffused in crystalline silicon (FIG. 8).
次に、写真蝕刻によつてドレイン領域１３、ソ
ース領域１４、ゲート電極１７上にある二酸化硅
素にコンタクト孔１８，１９，２０を設ける（第
９図）。 Next, contact holes 18, 19, and 20 are formed in the silicon dioxide on the drain region 13, source region 14, and gate electrode 17 by photolithography (FIG. 9).
最後に、ドレイン電極、ソース電極、ゲート電
極からアルミ配線２１，２２，２３を引き出せ
ば、第１０図を平面図とし、第１１図、第１２図
が第１０図のAA，BB′の断面図である所望のＮ
チヤンネル型のシリコンゲート型電界効果トラン
ジスタが得られる。 Finally, if the aluminum wirings 21, 22, and 23 are drawn out from the drain electrode, source electrode, and gate electrode, Fig. 10 is a plan view, and Figs. 11 and 12 are cross-sectional views of AA and BB' in Fig. 10. the desired N
A channel type silicon gate field effect transistor is obtained.
尚、ゲート電極１７のコンタクト孔２０は、第
１０図に見られる如く、窒化硅素膜片８に含まれ
る様にしてあるから、開孔２０を設ける際、二酸
化硅素のエツチング液は、窒化硅素膜片８で浸入
（弗酸：水＝１：10）
を阻まれ、ゲート絶縁膜の二酸化硅素３はエツチ
ングされない。従つて、ゲート電極１７と基板１
７と基板１が短絡することが防止できる。また、
窒化シリコン膜片８は、ゲート電極であるＮ型多
結晶シリコン中に埋没させてあるために、電荷蓄
積現象等を惹起することはなく、本発明によるト
ランジスタの閾値電圧は、従来のシリコンゲート
型電界効果トランジスタと同程度の安定性を有す
る。 The contact hole 20 of the gate electrode 17 is included in the silicon nitride film piece 8 as shown in FIG. The silicon dioxide 3 of the gate insulating film is not etched because the penetration is blocked by the piece 8 (hydrofluoric acid:water = 1:10). Therefore, the gate electrode 17 and the substrate 1
7 and the substrate 1 can be prevented from being short-circuited. Also,
Since the silicon nitride film piece 8 is buried in the N-type polycrystalline silicon that is the gate electrode, it does not cause any charge accumulation phenomenon, and the threshold voltage of the transistor according to the present invention is lower than that of the conventional silicon gate type. It has stability comparable to that of field effect transistors.
本実施例での多結晶シリコン膜中に埋めた絶縁
膜８の代りとして、絶縁膜に限らず、ゲート絶縁
膜１のエツチング液（ガス）で腐蝕されない物質
層を少なくとも一層含む多重層を用いてもよいこ
とは明らかであろう。 In place of the insulating film 8 buried in the polycrystalline silicon film in this embodiment, it is possible to use not only an insulating film but also a multilayer including at least one material layer that is not corroded by the etching solution (gas) of the gate insulating film 1. It is obvious that this is a good thing.
本発明は、シリコンゲート型電界効果トランジ
スタにおけるチヤンネル領域上の多結晶シリコン
によるゲート電機から直接、金属配線を施せるか
らこの種のトランジスタによる半導体モノリシツ
ク集積回路のパターン設計の自由度が増し、集積
度向上に寄与する。 The present invention allows metal wiring to be applied directly from the polycrystalline silicon gate circuit on the channel region of a silicon gate field effect transistor, increasing the degree of freedom in pattern design of semiconductor monolithic integrated circuits using this type of transistor, and improving the degree of integration. Contribute to
第１図〜第３図、第５図〜第６図、第８図〜第
９図、および第１１図は本発明の実施例を説明す
るための工程順の断面図であり、第４図、第７図
および第１０図は、夫々第３図、第６図および第
１１図の平面図である。第１１図、第１２図は、
第１０図の夫々AA′，BB′における断面図であ
る。
１……Ｐ型単結晶基板、２・１５・１６，３…
…熱酸化による二酸化硅素膜、同膜のゲート絶縁
膜、４・９，１１・１２……気相成長法による多
結晶シリコン膜、同膜片、５，８……気相成長法
による窒化硅素膜、同膜片、６，７……気相成長
法による二酸化硅素膜、同膜片、１０……PR
膜、１３，１４……Ｎ導電型ドレイン拡散層、同
ソース層、１７……ゲート電極、１８，１９，２
０……ドレイン、ソース、ゲートコンタクト孔、
２１，２２，２３……ドレイン、ソース、ゲート
電極引出し用アルミ配線。
1 to 3, 5 to 6, 8 to 9, and 11 are cross-sectional views in the order of steps for explaining embodiments of the present invention, and FIG. , 7 and 10 are plan views of FIGS. 3, 6 and 11, respectively. Figures 11 and 12 are
10 are cross-sectional views at AA' and BB', respectively; FIG. 1...P-type single crystal substrate, 2, 15, 16, 3...
...Silicon dioxide film by thermal oxidation, gate insulating film of the same film, 4, 9, 11, 12... Polycrystalline silicon film, piece of the same film by vapor phase growth method, 5, 8... Silicon nitride film by vapor phase growth method Film, piece of the same film, 6, 7...Silicon dioxide film by vapor phase growth method, piece of the same film, 10...PR
Film, 13, 14... N conductivity type drain diffusion layer, same source layer, 17... Gate electrode, 18, 19, 2
0...Drain, source, gate contact hole,
21, 22, 23... Aluminum wiring for leading out drain, source, and gate electrodes.
Claims (1)
ト絶縁膜のエツチング材でエツチングされない物
質および第２の多結晶シリコン膜の順で積層され
る領域と、該第１の多結晶シリコン膜および該第
２の多結晶シリコン膜の順で積層される領域とを
有することを特徴とする電界効果トランジスタ。1. A region in which a gate electrode is laminated in this order of a first polycrystalline silicon film, a substance that is not etched with the gate insulating film etching agent, and a second polycrystalline silicon film, and a region in which the first polycrystalline silicon film and the second polycrystalline silicon film 1. A field effect transistor comprising a region in which two polycrystalline silicon films are stacked in this order.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10195179A JPS5626469A (en) | 1979-08-10 | 1979-08-10 | Field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10195179A JPS5626469A (en) | 1979-08-10 | 1979-08-10 | Field-effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5626469A JPS5626469A (en) | 1981-03-14 |
| JPS6214953B2 true JPS6214953B2 (en) | 1987-04-04 |
Family
ID=14314191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10195179A Granted JPS5626469A (en) | 1979-08-10 | 1979-08-10 | Field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5626469A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03501319A (en) * | 1988-04-19 | 1991-03-22 | エス・ベー・エフ・アウト ‐ エレクトリツク・ゲー・エムベーハー | Electric motor for wiper motors to drive windshield wiper devices in automobiles |
| JPH087803Y2 (en) * | 1989-09-14 | 1996-03-04 | 自動車電機工業株式会社 | Motor with reduction mechanism |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4789883A (en) * | 1985-12-17 | 1988-12-06 | Advanced Micro Devices, Inc. | Integrated circuit structure having gate electrode and underlying oxide and method of making same |
-
1979
- 1979-08-10 JP JP10195179A patent/JPS5626469A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03501319A (en) * | 1988-04-19 | 1991-03-22 | エス・ベー・エフ・アウト ‐ エレクトリツク・ゲー・エムベーハー | Electric motor for wiper motors to drive windshield wiper devices in automobiles |
| JPH087803Y2 (en) * | 1989-09-14 | 1996-03-04 | 自動車電機工業株式会社 | Motor with reduction mechanism |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5626469A (en) | 1981-03-14 |
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