JPS6214469A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the over-etching of the first gate insulation film in the side direction by a method wherein an insulative film is selectively formed only on the first gate electrode's side wall section beforehand when the first gate insulation film is etched with the first gate electrode as a mask. CONSTITUTION:The first insulation film 12 that will be the first gate insulation film is formed on the whole surface of a semiconductor substrate 1, and the first gate electrodes 131 and 132 are formed on it. The second insulation film 14 is deposited on the whole surface of the substrate on which the first gate electrode is formed, and the film 14 is etched by anisotropy etching to left only the side wall of the first gate electrode. Then, first layer insulative film 12 is etched with the first gate electrodes 131 and 132 as masks to expose the surface of the substrate, and the third insulative film 15 to be the second gate electrode film is formed on the exposed surface of the substrate and the surface of the first gate electrode. Then, the second gate electrodes 161 and 162 whose one part laps on the first gate electrode are formed on the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device having a multi-II pole structure in which a second gate electrode is formed to partially overlap a first gate electrode.

[Technical background of the invention and its problems]

With advances in semiconductor technology, various semiconductor devices with multi@electrode structures are being manufactured. A CCD (Charge Coupled [)
evice) is well known. Such a multilayer gate w1 layer structure is usually formed using polycrystalline silicon.

FIG. 3 shows an example of a conventional CCD 9A manufacturing process. First of all (a
), a first gate insulating layer 22 is formed on the Si substrate 21 by thermal oxidation, and a second @ polycrystalline silicon film 25 is deposited thereon. 1st Fl! I polycrystalline silicon belly 23
In order to lower the resistance, phosphorus or the like is introduced by diffusion or ion implantation. After this, as shown in (b),
The polycrystalline silicon film 23 is etched through a PEP process to form second gate electrodes 23+, 232, . . . , and the first gates 1123+, 232, . Remove I22 by etching. In this etching step, a wet etching method using \H+F or the like is normally used so as not to damage the substrate 21. Next, as shown in (C), a second gate insulator 24 is formed by thermal oxidation, and a second polycrystalline silicon layer 25 is deposited thereon.

Phosphorus or the like is also introduced into this 21i1F polycrystalline silicon layer 25 in order to lower the resistance. Then, as shown in (d), this second@polycrystalline silicon film 25 is erected, and the first gate 1! +25+, 252 to the second gate electrodes that partially overlap the poles 23+, 232, .

... to form. A two-tiered gate that partially overlaps like this! ! The poles are used as transfer electrodes.

When two-layer gate electrodes that overlap each other are formed using the conventional process, the following problems arise. In FIG. 3(b), the first gate electrodes 23+, 232, . . .
When etching the insulation 111I22 into the first goo 1 using . as a mask, wet etching using N84F liquid or the like is used so as not to damage the substrate 21 as in the previous case. Since this etching is isotropic, the first gate dielectric 22 is laterally over-etched and the first gate dielectrics 23+, 232, . . .
・An overhang is formed. This state is enlarged and shown in FIG. 4(a). When the second goo 1 to insulator 24 are then formed by thermal oxidation in such a state, the oxidation at the overhang portion will occur on the substrate 2] side and the first gate 1! pole 231゜2
Since it advances from both sides, the first gate voltage t4
The ends of 23+, 232, . . . are lifted up. As a result, the second gate electrodes 251, 252...
As shown in FIG. 4(b), the first gate electrode 23+,
232, ... is formed in a state that it bites into the lower part. In such a state, electric field concentration tends to occur at the part where the second gate electrode digs into the first gate under one electrode, and the goo 8
This may cause electrostatic damage between the electrodes 144 or between the gate electrode and the substrate, or cause deterioration of the withstand voltage. Furthermore, if the end of the first gate electrode serving as a transfer IF pole is raised as shown in FIG. 2, the depth of the potential well formed below becomes non-uniform. For example, in a surface channel type CCD, the potential well becomes shallower as the gate oxide thickness becomes thicker, whereas in a buried channel COD, the potential well becomes deeper. When a potential barrier or pocket is formed in the substrate at the end of the first gate electrode in this way, charge is left behind, causing deterioration in COD transfer efficiency.

[Object of the Invention] An object of the present invention is to provide a method for manufacturing a semiconductor device having a multilayer gate bridge structure, which solves the above two problems.

[Summary of the invention]

In the present invention, when etching the first gate insulating film using the first gate electrode as a mask, the first gate insulating film is etched in advance in order to prevent over-etching of the first gate insulating film in the lateral direction. A step of selectively forming an insulating antinode only on the quadrupole side wall portion is provided. This step is performed by depositing an insulating film by, for example, CVD on the substrate on which the first gate electrode is formed, and etching this by anisotropic etching.

(Effects of the Invention) According to the present invention, since the first gate insulating film is etched with the side wall of the first gate electrode covered with the insulating film formed by CVD, etching is performed from the end of the first gate electrode as in the conventional method. Over-etching in the lateral direction is prevented. Therefore, when a second gate insulating film is formed next and a second gate electrode is formed, the second gate electrode does not dig under the first gate electrode at the gate electrode overlap part, resulting in a highly reliable second gate electrode. A layered gate structure is obtained. Especially Honkoen
When applied to CO, there is no possibility of non-uniformity in the depth of the potential well under the transfer electrode, and the transfer efficiency is improved.

(Example of the invention) The present invention will be explained in detail below.

FIGS. 1(a) to 1(g) are manufacturing process diagrams of an embodiment in which the present invention is applied to COD. First, as shown in (a), 5r
The first gate insulating film 12 (first
A first polycrystalline silicon film 13 is deposited thereon. First layer polycrystalline silicon It! In order to lower the resistance value of the semiconductor layer 113, an appropriate impurity is introduced by diffusion or ion implantation. Next, through a PEP process, the first@polycrystalline silicon III 13 is etched by an anisotropic etching method such as reactive ion etching (RIE), and the first gate electrode ff is etched as shown in (b).
113+, 1.32, . . . are formed. First gate electrodes 131, 132. The side walls of ... are almost vertical because anisotropic etching is used.

Next, first gate electrodes 131, 132. As shown in (C), a silicon oxide film 14 (21st film insulating film) is deposited on the entire surface of the substrate on which .

This oxide 1114 is deposited to have a thickness equal to or greater than that of the first gate insulating film 12. Then, this oxide film 14 is etched by an amount corresponding to its film thickness by anisotropic etching such as RIE, and the first gate electrodes 13x, 132 . Leave it only on the side wall of... As a result, the first gate electrodes 131, 132.・・・
・The side! The portion is covered with an oxide film 14. After this, the first gate insulating film 12 is wet-treated using NH4F or the like.
Etching is performed to expose the surface of the substrate 11 as shown in (e). At this time, the oxide film 14 prevents the etching from digging into the bottom of the first gate electrodes 131, 132°, . . . .

Thereafter, as shown in <f), the second gate insulating film 1015 (third layer insulating film) is coated on the surface of the substrate 11 and the first gate electrodes 131, 132, . . . by thermal oxidation. ... is formed on the surface of the second
11! ! Deposit polycrystalline silicon 116. Appropriate impurities are also introduced into the second layer polycrystalline silicon film 16 in order to lower the resistance. And this 21st polycrystalline silicon film 1
6 to form second gate electrodes 161, 162, . . . , partially overlapping the first gate electrodes 131, 132, .

Note that Fig. 1 (C) shows oxide 1114 deposited by CVD.
state or this oxidation 1114 to the first gate electrode 131
, 132. It is effective to perform high-temperature heat treatment in the state shown in FIG. 1(d) left on the side wall portion of . As a result, the CVD oxidation 1114 becomes dense and has an etching rate comparable to that of the first gate insulating film 1112 formed by thermal oxidation, thereby improving the lateral etching performance in the etching process of the first gate insulating film 12. be able to.

The structure of this embodiment, which corresponds to the conventional structure shown in FIGS. 4(a) and 4(b), is shown in FIGS. 2(a) and 2(b). As is clear from the figure, according to the embodiment, the second gate electrodes 161, 162. ...
is prevented from digging under the first gate electrodes 131, 132, . . . , and a highly reliable two-layer gate structure is obtained. Moreover, the first gate electrodes 131, 132. Since there is no lifting of the end portion of .

Further, in COD, it is necessary to maintain the substrate potentials under the first gate electrode and the second gate electrode at predetermined potentials, respectively. Assuming that the potential below the second gate electrode has already been set to a predetermined potential by ion implantation, etc., ion implantation will be performed to set the substrate potential below the second gate electrode to a predetermined value in FIG. 1(d). . In this case, in the conventional method, since there is no oxide film 14, the implanted impurity under the second gate electrode diffuses laterally and enters under the first gate electrode in the subsequent thermal process, and as a result, the first gate 1!
The potential distribution at the bottom collapses. This causes a deterioration in charge transfer efficiency. On the other hand, in this embodiment, the oxide film 1
4 serves as a stopper in this ion implantation step, and even if implanted impurities are diffused laterally in a subsequent thermal step, they are prevented from penetrating below the first gate electrode, thereby preventing deterioration in transfer efficiency.

The present invention is not limited to the above embodiments. For example, in the above embodiment, the first. Although polycrystalline silicon was used as the second gate electrode, metal silicides such as molybdenum silicide or titanium silicide, or a laminated structure of polycrystalline silicon and these metal silicides may also be used. The present invention is effective. Further, in the above embodiment, a silicon oxide film formed by CVD is used as the insulating film selectively formed on the side wall portion of the first gate electrode, but sputtering, vapor deposition, or the like may be used as a method for forming this oxide film. Further, this insulating film is not limited to a silicon oxide film, and for example, a silicon nitride film or a resist can also be used.

Further, the present invention is useful not only for COD but also for any semiconductor device having a multilayer gate electrode structure stacked in a -city pattern.

[Brief explanation of drawings]

1(a) to (Q) are diagrams showing the bridge forming process of a CCD gate 1 according to an embodiment of the present invention; FIGS. 2(a) and 2(b) are diagrams showing the main parts enlarged; 3(a) to (d) are diagrams showing the conventional COD gate electrode forming process, and FIG. 4(a) to (b)
) is an enlarged view of the main part. DESCRIPTION OF SYMBOLS 11... Si substrate, 12... First gate insulating film (first layer insulating film), 13... First layer polycrystalline silicon substrate, 1
31.132... First gate electrode, l4-Cv silicon acid oxidation (second layer insulating film), 15... Second gate insulating film (first layer insulating film l), 16... 21st layer Crystal silicon, 161.162... second gate electrode. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 1

Claims (5)

[Claims] (1) A first gate insulating film is formed on the entire surface of the semiconductor substrate.
A step of forming a layer insulating film, and a step of forming a first layer insulating film on the first layer insulating film.
A step of forming a gate electrode, and depositing a second layer insulating film on the entire surface of the substrate on which the first gate electrode is formed, and etching it by anisotropic etching to leave it only on the side walls of the first gate electrode. a step of etching the first layer insulating film using the first gate electrode as a mask to expose the substrate surface; and a third step of etching the first layer insulating film using the first gate electrode as a mask to form a second gate insulating film on the exposed substrate surface and the first gate electrode surface. A semiconductor device comprising the steps of forming a layer insulating film, and forming a second gate electrode partially overlapping the first gate electrode on the substrate on which the third layer insulating film is formed. manufacturing method. (2) The first layer insulating film and the third layer insulating film are thermal oxide films, the second layer insulating film is a CVD oxide film, and the first gate electrode and the second gate electrode are polycrystalline silicon films. or a metal silicide film, the method for manufacturing a semiconductor device according to claim 1. (3) The method for manufacturing a semiconductor device according to claim 1, wherein the second layer insulating film has a thickness equal to or greater than that of the first layer insulating film. (4) The method for manufacturing a semiconductor device according to claim 1, wherein heat treatment is performed after depositing the second layer insulating film and before etching it. (5) After etching the second layer insulating film and leaving it only on the side wall of the first gate electrode, heat treatment is performed before etching the first layer insulating film. A method for manufacturing a semiconductor device.