JPH04155842A - Manufacture of charge transfer device - Google Patents

Manufacture of charge transfer device

Info

Publication number
JPH04155842A
JPH04155842A JP28074190A JP28074190A JPH04155842A JP H04155842 A JPH04155842 A JP H04155842A JP 28074190 A JP28074190 A JP 28074190A JP 28074190 A JP28074190 A JP 28074190A JP H04155842 A JPH04155842 A JP H04155842A
Authority
JP
Japan
Prior art keywords
electrodes
layers
electrode
charge transfer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28074190A
Other languages
Japanese (ja)
Inventor
Yuji Matsuda
祐二 松田
Wataru Kamisaka
上坂 渡
Takao Kuroda
黒田 隆男
Hiroyuki Okada
裕幸 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP28074190A priority Critical patent/JPH04155842A/en
Publication of JPH04155842A publication Critical patent/JPH04155842A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To contrive to effectively inhibit the extent that the regions of impurity layers spread up to the lower parts of first electrodes by a method wherein the first electrodes are formed at prescribed positions on a first insulating film and the impurity layers are selectively formed using the first electrodes and second insulating films, which are positioned on the sidewalls of the first electrodes, as masks. CONSTITUTION:A first oxide film layer 4 is formed on a semiconductor substrate, which is constituted of a P-type substrate 1 and an N-type buried layer 2, as a first insulating film and thereafter, first electrodes 5, 5... are formed at prescribed regions on the layer 4. Second oxide film layers 6 which are used as second insulating layers are formed in such a way as to cover the whole of the sidewalls and upper surfaces of the electrodes 5. A P-type impurity is implanted using the layers 6 as masks to form selectively P-type impurity layers 3 and second electrodes 7, 7... are formed between the layers 6. A high-temperature heat treatment is not applied to the P-type impurity and the diffusion and lateral spread of the layers 3 are inhibited. The extent of the layers 3 to the lower parts of the electrodes 5 is reduced. At the time of ion implantation of the P-type impurity, the P-type impurity layer 3 implanted regions are far off from the end parts of the electrodes 5 and the diffusion and intrusion of the layers 3 into the lower parts of the electrodes 5 are further inhibited.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は一体型ビデオカメラ等に利用できる固体撮像素
子などに関して適用する電荷転送装置の製造方法に関す
る。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a charge transfer device applied to a solid-state image pickup device that can be used in an integrated video camera or the like.

(従来の技術) 近年、電荷転送装置は一体型ビデオカメラの撮像部など
に広く実用化されている。中でも埋め込みチャンネル型
CCD (charge coupled devic
e )は低雑音特性を有するため精力的な開発が進めら
れている。
(Prior Art) In recent years, charge transfer devices have been widely put into practical use in imaging units of integrated video cameras and the like. Among them, embedded channel CCD (charge coupled device)
e) has low noise characteristics and is therefore being actively developed.

以下、従来の電荷転送装置について図面を参照しながら
説明する。
A conventional charge transfer device will be described below with reference to the drawings.

第5図及び第6図は各々従来の電荷転送装置の製造過程
及び構成を示す模式図である。第6図の構成図において
、1はP型基板、2はn型埋め込み層、3はP型不純物
層、4は第1酸化膜層、5は第1電極、6は第2酸化膜
層、7は第2電極である。また、同図(a)において、
G1は第1電極5の奇数列と第2電極7の奇数列とを接
続した第1入力端子、G2は第1電極5の偶数列と第2
電極7の偶数列とを接続した第2入力端子である。
FIGS. 5 and 6 are schematic diagrams showing the manufacturing process and structure of a conventional charge transfer device, respectively. In the configuration diagram of FIG. 6, 1 is a P-type substrate, 2 is an n-type buried layer, 3 is a P-type impurity layer, 4 is a first oxide film layer, 5 is a first electrode, 6 is a second oxide film layer, 7 is a second electrode. In addition, in the same figure (a),
G1 is a first input terminal that connects the odd numbered rows of the first electrodes 5 and the odd numbered rows of the second electrodes 7; G2 is the first input terminal that connects the even numbered rows of the first electrodes 5 and the second
This is a second input terminal connected to the even numbered rows of electrodes 7.

同図(b)において、φ1は上記第1入力端子G1に印
加入力されるパルス波形、φ2は第2入力端子G2に印
加入力されるパルス波形である。各パルス波形φ1.φ
2はハイレベルの時に正電圧を各々入力端子Gl、G2
に印加する。
In the figure (b), φ1 is a pulse waveform applied to the first input terminal G1, and φ2 is a pulse waveform applied to the second input terminal G2. Each pulse waveform φ1. φ
2 are input terminals Gl and G2, respectively, which receive positive voltage when at high level.
to be applied.

第6図(a)の下図は、同図(b)における時間tのと
きの電位分布を示す図である。QSは信号電荷、QLは
転送損失により発生した残留電荷である。
The lower diagram of FIG. 6(a) is a diagram showing the potential distribution at time t in FIG. 6(b). QS is a signal charge, and QL is a residual charge generated due to transfer loss.

以上のように構成された従来の電荷転送装置について、
以下その製造方法と動作を説明する。
Regarding the conventional charge transfer device configured as described above,
The manufacturing method and operation thereof will be explained below.

第5図は上記従来の電荷転送装置の製造過程を示す図で
あって、先ず、同図(a)のとき、第1酸化膜層4を形
成した後、第1電極5を形成する。
FIG. 5 is a diagram showing the manufacturing process of the conventional charge transfer device. First, in the case of FIG. 5(a), the first oxide film layer 4 is formed, and then the first electrode 5 is formed.

次に同図(b)のとき第1電極5をマスクとしてP型不
純物層3を注入する。続いて同図(C)のとき第2酸化
膜層6を形成し、同図(d)のとき第2電極7を形成す
る。
Next, as shown in FIG. 4B, a P-type impurity layer 3 is implanted using the first electrode 5 as a mask. Subsequently, a second oxide film layer 6 is formed in the case shown in FIG. 5C, and a second electrode 7 is formed in the case shown in FIG.

(発明が解決しようとする課題) しかしながら、上記従来の電荷転送装置の製造方法では
、P型不純物層3か、第2酸化膜層6を形成する時又は
その他の熱処理工程に起因して、その不純物層の領域が
第1電極5の下にまで広かり、その影響で第1電極5の
下に形成される埋め込みチャンネルの空乏化電圧が部分
的に低下する。
(Problems to be Solved by the Invention) However, in the above-described conventional method for manufacturing a charge transfer device, due to the formation of the P-type impurity layer 3 or the second oxide film layer 6 or other heat treatment steps, The region of the impurity layer expands below the first electrode 5, and as a result, the depletion voltage of the buried channel formed below the first electrode 5 is partially lowered.

また、空乏化電圧の低下した部分が障壁となって残留電
荷か発生し、電荷転送装置の特性を著しく低下させると
いう問題点を有していた。
Further, there is a problem in that the portion where the depletion voltage has decreased acts as a barrier and residual charges are generated, which significantly deteriorates the characteristics of the charge transfer device.

本発明は斯かる点に鑑みてなされたものであり、その目
的は、不純物層の領域が第1電極の下方にまで広がる程
度を有効に抑制することにある。
The present invention has been made in view of this point, and its purpose is to effectively suppress the extent to which the region of the impurity layer extends below the first electrode.

(課題を解決するための手段) 上記目的を達成するために、本発明では、半導体領域上
に絶縁膜を介して複数の転送電極を有する電荷転送装置
を製造する際に、高温度の熱処理を行う第2酸化膜層等
を形成した後に、不純物層を形成することとする。
(Means for Solving the Problems) In order to achieve the above object, the present invention includes high-temperature heat treatment when manufacturing a charge transfer device having a plurality of transfer electrodes on a semiconductor region via an insulating film. After forming the second oxide film layer and the like, the impurity layer is formed.

つまり、本発明の具体的な解決手段は、半導体基板上に
第1の絶縁膜を形成した後、該第1の絶縁膜の所定領域
に第1の電極を形成し、その後、前記第1の電極の側壁
を少なくとも覆う第2の絶縁膜を形成した後、前記第1
の電極及び該第1の電極の側壁に位置する前記第2の絶
縁膜をマスクとして選択的に不純物層を形成する構成と
している。
In other words, the specific solution of the present invention is to form a first insulating film on a semiconductor substrate, then form a first electrode in a predetermined region of the first insulating film, and then After forming the second insulating film that covers at least the side walls of the electrode, the first
The impurity layer is selectively formed using the electrode and the second insulating film located on the side wall of the first electrode as a mask.

さらに、不純物層の形成は電荷の転送方向に対して10
″から45″の傾斜角度を持たせてイオン注入により形
成する構成としている。
Furthermore, the formation of the impurity layer is 10° in the direction of charge transfer.
The structure is such that it is formed by ion implantation with an inclination angle of 45" to 45".

(作用) 上記構成により、高温度の熱処理を行う第2の絶縁膜の
形成後に不純物層か形成される。このことにより、不純
物層の形成後は高温度の熱処理工程かなくなって、不純
物層が第1の電極の下方にまで広がる程度を低減できる
ので、転送損失を大幅に改善することかできる。
(Function) With the above structure, the impurity layer is formed after the second insulating film is formed, which is subjected to high-temperature heat treatment. This eliminates the need for a high-temperature heat treatment step after forming the impurity layer, reducing the extent to which the impurity layer spreads below the first electrode, thereby significantly improving transfer loss.

しかも、不純物層の注入を傾斜角度を持って行う場合に
は、不純物層が第1の電極に対して離れた位置に形成さ
れるので、不純物層の拡散横広がりがあっても、第1の
電極下方にまで広がることを十分に防止できる。
Moreover, when the impurity layer is implanted at an inclined angle, the impurity layer is formed at a distance from the first electrode, so even if the impurity layer spreads laterally, the first electrode It can be sufficiently prevented from spreading below the electrode.

(実施例) 以下、本発明の第1の実施例について図面を参照しなが
ら説明する。
(Example) Hereinafter, a first example of the present invention will be described with reference to the drawings.

第1図及び第2図は本発明の電荷転送装置の製造過程と
構成を示す模式図である。第2図の構成図において、1
はP型基板、2はn型埋め込み層、3はP型不純物層、
4は第1酸化膜層、5は第1電極、6は第2酸化膜層、
7は第2電極である。
FIGS. 1 and 2 are schematic diagrams showing the manufacturing process and structure of the charge transfer device of the present invention. In the configuration diagram of Figure 2, 1
is a P-type substrate, 2 is an n-type buried layer, 3 is a P-type impurity layer,
4 is a first oxide film layer, 5 is a first electrode, 6 is a second oxide film layer,
7 is a second electrode.

また、同図(a)において、G1は第1電極5の奇数列
と第2電極7の奇数列とを接続した第1入力端子、G2
は第1電極5の偶数列と第2電極7の偶数列とを接続し
た第2入力端子である。同図(b)において、φ1は上
記第1入力端子G1に印加入力するパルス波形、φ2は
第2入力端子G2に印加入力するパルス波形であって、
各パルスはハイレベルの時に正電圧を各々入力端子Gl
In addition, in the same figure (a), G1 is the first input terminal connecting the odd numbered rows of the first electrodes 5 and the odd numbered rows of the second electrodes 7;
is a second input terminal connecting the even numbered columns of the first electrodes 5 and the even numbered columns of the second electrodes 7. In the same figure (b), φ1 is a pulse waveform applied to the first input terminal G1, φ2 is a pulse waveform applied to the second input terminal G2,
When each pulse is at a high level, a positive voltage is applied to each input terminal Gl.
.

G2に印加する。Apply to G2.

第2図(a)の下図は、同図(b)の時間tのときの電
位分布を示す図であって、QSは信号電荷である。
The lower diagram of FIG. 2(a) is a diagram showing the potential distribution at time t in FIG. 2(b), where QS is a signal charge.

以上のように構成された本発明の電荷転送装置について
、以下その製造方法と動作を説明する。
The manufacturing method and operation of the charge transfer device of the present invention configured as described above will be described below.

第1図は第2図の電荷転送装置の製造過程を示す図であ
って、先ず、同図(a)のときP型基板1とn型埋め込
み層2とで構成する半導体基板の該n型埋め込み層2の
上に第1の絶縁膜として第1酸化膜層4を形成した後、
所定領域に第1電極5゜5・・・を形成する。次に同図
(b)のとき第1電極5の側壁及び上面の全体を覆うよ
うに第2の絶縁膜としての第2酸化膜層6を形成する。
FIG. 1 is a diagram showing the manufacturing process of the charge transfer device shown in FIG. 2. First, in the case of FIG. After forming the first oxide film layer 4 as a first insulating film on the buried layer 2,
First electrodes 5.5 are formed in a predetermined area. Next, in FIG. 5B, a second oxide film layer 6 is formed as a second insulating film so as to cover the entire sidewall and top surface of the first electrode 5.

この時の熱処理は1000℃で20分以上の時間を必要
とする。続いて同図(c)のとき上記第2酸化膜層6を
マスクとしてP型不純物層3を注入して選択的に形成し
、同図Cd)のとき第2酸化膜層6゜6間に第2電極7
.7・を形成する。
The heat treatment at this time requires 20 minutes or more at 1000°C. Subsequently, in the case of (c) in the same figure, a P-type impurity layer 3 is selectively implanted using the second oxide film layer 6 as a mask, and in the case of Cd) in the same figure, a P-type impurity layer 3 is formed between the second oxide film layers 6. Second electrode 7
.. Form 7.

以上のように本実施例では、第2酸化膜層6を1000
℃以上の熱処理により形成した後、該第2酸化膜層6を
マスクにP型不純物層3を注入するので、従来のように
P型不純物に上記高温度の熱処理がかからない。このこ
とにより、P型不純物層3の拡散、横広がりが抑制され
るので、第1電極5の下方へのP型不純物層3の広がり
を低減することができ、転送損失を大幅に改善すること
ができる。
As described above, in this embodiment, the second oxide film layer 6 is
After being formed by heat treatment at temperatures above .degree. C., the P-type impurity layer 3 is implanted using the second oxide film layer 6 as a mask, so that the P-type impurity is not subjected to the high-temperature heat treatment as in the prior art. This suppresses the diffusion and lateral spread of the P-type impurity layer 3, which makes it possible to reduce the spread of the P-type impurity layer 3 below the first electrode 5, thereby significantly improving transfer loss. I can do it.

また、P型不純物層3をイオン注入する際にマスクとな
る第2酸化膜層6は、通常1500〜3000人の厚さ
があるため、その厚さたけ、P型不純物層3の注入領域
が第1電極5の端部より遠く離れることになり、P型不
純物層3の第1電極5の下方への拡散、入り込みを一層
抑制することができる。
Furthermore, since the second oxide film layer 6, which serves as a mask when ion-implanting the P-type impurity layer 3, is usually 1,500 to 3,000 thick, the implanted region of the P-type impurity layer 3 is Since it is far away from the end of the first electrode 5, diffusion and penetration of the P-type impurity layer 3 downward into the first electrode 5 can be further suppressed.

次に、本発明の第2の実施例について図面を参照しなが
ら説明する。
Next, a second embodiment of the present invention will be described with reference to the drawings.

第3図及び第4図は本発明の電荷転送装置の製造過程及
び構成を示す模式図である。前記第1の実施例の第2図
に示す構成と違う点は、第4図に示す構成において、不
純物の注入を傾斜角度を持たせて行っている点である。
FIGS. 3 and 4 are schematic diagrams showing the manufacturing process and structure of the charge transfer device of the present invention. The difference from the structure shown in FIG. 2 of the first embodiment is that in the structure shown in FIG. 4, impurity implantation is performed at an inclined angle.

次に、第4図の電荷転送装置について、以下その製造方
法と動作を第3図の工程図に基いて説明する。先ず、第
3図(a)のとき第1酸化膜層4を形成した後、第1電
極5を形成する。次に同図(b)のとき第1電極5を覆
う第2酸化膜層6を形成する。この時の熱処理は100
0℃で20分以上の時間を必要とする。次に同図(C)
のとき第2酸化膜層6をマスクにP型不純物層3を電荷
の転送方向に対して10〜45°の傾斜角度を持たせて
注入する。この理由は、第1電極5の厚さが0.5μm
である関係上、注入角を10〜45°の傾斜角度に設定
すれば、そのP型不純物層3が後工程の熱処理により拡
散、横広がりしても、その広がりを0.1〜0.5μm
の間に抑制できて、第1電極5の下部への影響を無視て
きるからである。続いて同図(d)のとき第2電極7を
形成する。
Next, the manufacturing method and operation of the charge transfer device shown in FIG. 4 will be explained based on the process diagram shown in FIG. 3. First, in FIG. 3(a), the first oxide film layer 4 is formed, and then the first electrode 5 is formed. Next, as shown in FIG. 5B, a second oxide film layer 6 covering the first electrode 5 is formed. The heat treatment at this time was 100
It requires at least 20 minutes at 0°C. Next, the same figure (C)
At this time, using the second oxide film layer 6 as a mask, the P-type impurity layer 3 is implanted at an inclination angle of 10 to 45 degrees with respect to the charge transfer direction. The reason for this is that the thickness of the first electrode 5 is 0.5 μm.
Therefore, if the implantation angle is set to an inclination angle of 10 to 45 degrees, even if the P-type impurity layer 3 diffuses and spreads laterally during heat treatment in the post-process, the spread will be 0.1 to 0.5 μm.
This is because the influence on the lower part of the first electrode 5 can be ignored. Subsequently, the second electrode 7 is formed as shown in FIG. 3(d).

以上のように本実施例では、第2酸化膜層6をマスクに
P型不純物層3を傾斜角度を持たせて注入するので、P
型不純物層3の拡散横広がりによる転送損失が発生する
側のポテンシャルバリアをなくすことができる。
As described above, in this embodiment, the P-type impurity layer 3 is implanted at an inclined angle using the second oxide film layer 6 as a mask.
The potential barrier on the side where transfer loss occurs due to lateral diffusion of the type impurity layer 3 can be eliminated.

尚、以上の説明では、N型の埋め込み層にP型の不純物
層を形成する場合を示したが、P型の埋め込み層にN型
の不純物層を追加形成する場合も同様に適用できるのは
言うまでもない。
In addition, although the above explanation shows the case where a P-type impurity layer is formed in an N-type buried layer, the following can be similarly applied to the case where an N-type impurity layer is additionally formed in a P-type buried layer. Needless to say.

(発明の効果) 以上説明したように、本発明の電荷転送装置の製造方法
によれば、不純物層の電極下方への拡散横広がりを抑制
して転送損失を低減することができるので、転送損失が
極めて少ない高性能の電荷転送装置を作成することが可
能となり、実用上著効を発揮することができる。
(Effects of the Invention) As explained above, according to the method for manufacturing a charge transfer device of the present invention, it is possible to suppress the lateral diffusion of the impurity layer below the electrodes and reduce the transfer loss. It becomes possible to create a high-performance charge transfer device with extremely little amount of charge transfer, and it is possible to exhibit remarkable practical effects.

しかも、不純物層の注入を電荷の転送方向に対して傾斜
角度を持たせて行う場合には、不純物層を電極に対して
離れた位置に形成して電極下方にまで広がることを十分
に防止できるので、−層高性能の電荷転送装置を作成す
ることを可能にできる。
Moreover, if the impurity layer is implanted at an angle with respect to the charge transfer direction, the impurity layer can be formed at a distance from the electrode and can be sufficiently prevented from spreading below the electrode. Therefore, it is possible to create a high-performance charge transfer device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は第1実施例における電荷転送装置の製造過程を
示す図、第2図は同電荷転送装置の断面構成と電位分布
とパルス波形を示す図、第3図は第2実施例における電
荷転送装置の製造過程を示す図、第4図は同電荷転送装
置の断面構成と電位分布とパルス波形を示す図、第5図
は従来の電荷転送装置の製造過程を示す図、第6図は従
来の電荷転送装置の断面構成と電位分布とパルス波形を
示す図である。 1・・・P型基板、2・・・n型埋め込み層、3・・・
P型不純物層、4・・・第1酸化膜層、5・・・第1電
極、6・・第2酸化膜層、7・・第2電極、G1・・・
第1入力端子、G2・・・第2入力端子、φ1・・・G
1人力波形、φ2・・・G2人力波形、QS・・・信号
電荷、GL・・・残留電荷。 1・・P型基板 2、・n型埋め込み層 3 P型不純物層 4・第1酸化膜層 5・・第1電極 6・・・第2酸化膜層 7・・第2電極 G1・・・第1入力端子 G2・第2入力端子 φ1・・G1人力波形 φ2・・G2人力波形 QS・・信号電荷 GL・残留電荷 第1図 第2図 第3図 第4図 第5図
Fig. 1 is a diagram showing the manufacturing process of the charge transfer device in the first embodiment, Fig. 2 is a diagram showing the cross-sectional configuration, potential distribution, and pulse waveform of the charge transfer device, and Fig. 3 is a diagram showing the charge transfer device in the second embodiment. FIG. 4 is a diagram showing the cross-sectional structure, potential distribution, and pulse waveform of the charge transfer device. FIG. 5 is a diagram showing the manufacturing process of a conventional charge transfer device. FIG. 2 is a diagram showing a cross-sectional configuration, potential distribution, and pulse waveform of a conventional charge transfer device. 1...P-type substrate, 2...n-type buried layer, 3...
P-type impurity layer, 4... first oxide film layer, 5... first electrode, 6... second oxide film layer, 7... second electrode, G1...
First input terminal, G2...Second input terminal, φ1...G
1 manual waveform, φ2...G2 manual waveform, QS...signal charge, GL...residual charge. 1...P type substrate 2,...N type buried layer 3, P type impurity layer 4, first oxide film layer 5, first electrode 6...second oxide film layer 7, second electrode G1... 1st input terminal G2・2nd input terminal φ1・・G1 manual waveform φ2・・G2 manual waveform QS・・Signal charge GL・Residual charge Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 5

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板上に第1の絶縁膜を形成した後、該第
1の絶縁膜の所定領域に第1の電極を形成し、その後、
前記第1の電極の側壁を少なくとも覆う第2の絶縁膜を
形成した後、前記第1の電極及び該第1の電極の側壁に
位置する前記第2の絶縁膜をマスクとして選択的に不純
物層を形成することを特徴とする電荷転送装置の製造方
法。
(1) After forming a first insulating film on a semiconductor substrate, a first electrode is formed in a predetermined region of the first insulating film, and then,
After forming a second insulating film that covers at least a side wall of the first electrode, selectively add an impurity layer using the first electrode and the second insulating film located on the side wall of the first electrode as a mask. 1. A method of manufacturing a charge transfer device, comprising: forming a charge transfer device.
(2)不純物層の形成を、電荷の転送方向に対して所定
の傾斜角度を有するイオン注入によって行うことを特徴
とする請求項(1)記載の電荷転送装置の製造方法。
(2) The method for manufacturing a charge transfer device according to claim (1), wherein the impurity layer is formed by ion implantation having a predetermined inclination angle with respect to the charge transfer direction.
(3)半導体基板上に第1の絶縁膜を形成した後、該第
1の絶縁膜の所定領域に第1の電極を形成し、その後、
前記第1の電極の側壁を少なくとも覆う第2の絶縁膜を
形成した後、前記第1の電極及び該第1の電極の側壁に
位置する前記第2の絶縁膜をマスクとして前記第2の絶
縁膜側面から基板表面上で0.1μm〜0.5μmの距
離を離れて不純物層を選択的に形成するように不純物を
注入することを特徴とする電荷転送装置の製造方法。
(3) After forming a first insulating film on the semiconductor substrate, forming a first electrode in a predetermined region of the first insulating film, and then
After forming a second insulating film that covers at least a side wall of the first electrode, the second insulating film is formed using the first electrode and the second insulating film located on the side wall of the first electrode as a mask. 1. A method for manufacturing a charge transfer device, comprising implanting impurities so as to selectively form an impurity layer at a distance of 0.1 μm to 0.5 μm from a side surface of a film on a substrate surface.
JP28074190A 1990-10-18 1990-10-18 Manufacture of charge transfer device Pending JPH04155842A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28074190A JPH04155842A (en) 1990-10-18 1990-10-18 Manufacture of charge transfer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28074190A JPH04155842A (en) 1990-10-18 1990-10-18 Manufacture of charge transfer device

Publications (1)

Publication Number Publication Date
JPH04155842A true JPH04155842A (en) 1992-05-28

Family

ID=17629310

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28074190A Pending JPH04155842A (en) 1990-10-18 1990-10-18 Manufacture of charge transfer device

Country Status (1)

Country Link
JP (1) JPH04155842A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0689994A (en) * 1992-09-08 1994-03-29 Matsushita Electron Corp Manufacture of solid-state image pickup
US5443116A (en) * 1992-08-31 1995-08-22 Mitsubishi Jukogyo Kabushiki Kaisha Stacked heat exchanger
JPH08222725A (en) * 1995-02-17 1996-08-30 Nec Corp Charge-coupled element and manufacture thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50115982A (en) * 1974-02-08 1975-09-10
JPS6214469A (en) * 1985-07-11 1987-01-23 Toshiba Corp Manufacture of semiconductor device
JPS63308959A (en) * 1987-06-10 1988-12-16 Mitsubishi Electric Corp Manufacture of charge transfer device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50115982A (en) * 1974-02-08 1975-09-10
JPS6214469A (en) * 1985-07-11 1987-01-23 Toshiba Corp Manufacture of semiconductor device
JPS63308959A (en) * 1987-06-10 1988-12-16 Mitsubishi Electric Corp Manufacture of charge transfer device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5443116A (en) * 1992-08-31 1995-08-22 Mitsubishi Jukogyo Kabushiki Kaisha Stacked heat exchanger
JPH0689994A (en) * 1992-09-08 1994-03-29 Matsushita Electron Corp Manufacture of solid-state image pickup
JPH08222725A (en) * 1995-02-17 1996-08-30 Nec Corp Charge-coupled element and manufacture thereof

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