JPS6213824B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit using a static induction transistor (hereinafter referred to as SIT), and particularly to an integrated circuit in which a split gate structure is introduced into the static induction transistor.

I ² L using an inverted junction static induction transistor
A type logic circuit (hereinafter referred to as SITL) has already been prototyped in Si using a very rudimentary process, and a minimum delay time of 3.5 nsec and a power delay product of 2fj have been obtained. The current delay time of SITL is determined mostly by the cumulative effect of minority carriers injected into the channel from the gate. SITL using a split gate structure SIT has been proposed as a structure to eliminate the speed limitation due to the accumulation effect of minority carriers (Patent No. 1302727 (Japanese Patent Publication No. 1302727)
No.) "Static induction transistor and semiconductor integrated circuit", Patent No. 1236163 (Special Publication No. 12017) "Semiconductor integrated circuit", Patent No. 1247054 (Special Publication No. 1987-12017)
21176) "Static induction transistor semiconductor integrated circuit", Patent No. 1231827 (Special Publication No. 59-8068) "Semiconductor integrated circuit").

In the split gate structure SIT, the gate that almost surrounds the channel is divided into multiple gates, some of which are used as drive gates that open and close the channel depending on the input signal, and the remaining gates are connected to the source to drive minority carriers. A fixed potential gate is used to suck out the liquid.
Because the dimensions of the drive gate are smaller than the channel dimensions, its capacitance is smaller.Since the fixed potential gate sucks out the minority carriers of the channel, the operating speed becomes very fast. At the same time, it also serves as an isolation region, so the integration density is improved, etc.
This is a characteristic of SITL.

It is an object of the present invention to provide a split-gate static induction transistor integrated circuit exhibiting improved characteristics.

The present invention will be explained in detail below using the drawings.

FIG. 1 shows a specific example of the split gate SITL of the present invention, which is a one-input, four-output unit. 1A is a plan view, FIG. 1B is a sectional view taken along lines A and A', and FIG. 1C is an equivalent circuit of one unit. The n ⁺ region 11 is a substrate region or a p
It is provided on the substrate by epitaxial growth, diffusion, ion implantation, etc. N ^- region 12 is a high resistance region and is usually provided on n ⁺ region 11 by epitaxial growth. Of course, diffusion, ion implantation, etc. may also be used. n ⁺ area 13, P ⁺ area 14, 15,
16 are each formed by diffusion, ion implantation, or a combination of both. The n ⁺ region 11 is the source region of an inverted SIT, the p ⁺ region 14 is the source region of an insulated gate field effect transistor (hereinafter referred to as MOS FET) that becomes an injector transistor, and the p ⁺ region 15 is the drain of the aforementioned MOS FET. At the same time, it is a drive gate for an inverted SIT. P ⁺ region 16 is a fixed potential gate. Each of the n ⁺ regions 13-1, 13-2, 13-3, and 13-4 serves as a drain of an inverted SIT. Fixed potential gate P ⁺ region 16 is connected to n ⁺ region 17 through electrode 17', and n ⁺ region 17 is maintained at almost the same potential as source region 11 via ^n- region. 1
3-1' and 13-3' are drain electrodes, respectively. Of course, electrodes are also provided on the n ⁺ regions 13-2 and 13-3. 14' is the injector
It serves as the source electrode and gate electrode of the MOS FET. Although no electrode is shown on the drive gate p ⁺ region 15, the electrode is provided at a location away from the AA' line. 18 is SiO ₂ ,
It is an insulating layer made of Si ₃ N ₄ , Al ₂ O ₃ or the like, or a composite insulating layer made by combining a plurality of these. In Figure 1c,
Vss (+) is the power supply voltage, Vin is the input voltage, and Vout is the output voltage. The impurity density of each region is about 11:10 ¹⁸ to 10 ²¹ cm ^-3 for the n ⁺ region and 1 for the n ^- region, respectively.
2: about 10 ¹² to 10 ¹⁶ cm ^-3 , n ⁺ area 13, 17:
About 10 ¹⁷ to 10 ²¹ cm ^-3 , p ⁺ regions 14, 15, 16:
It is about 10 ¹⁶ to 10 ²¹ cm ^-3 . Drive gate p ⁺ region 1
5 and the fixed potential gate p ⁺ region 16 is determined in relation to the impurity density of the channel n ⁻ region 12. SIT channel dimensions and impurity density are
The diffusion potential of the p ⁺ n ^-junction alone causes the channel to completely pinch off, creating a high potential barrier in the channel. For example, if the impurity density in the n ^-region is, for example, 7×10 ¹³ cm ^-3 , 2×10 ¹⁴ cm ^-3 ,
If it is about 2×10 ¹⁵ cm ⁻³ , the spacing between p ⁺ regions 15 and 16 is about 5 μm, 3 μm, and 1 μm or less, respectively. Of course, this value also changes depending on the source-drain spacing. The source-drain interval is, for example, about 0.5 to 5 μm. The shorter the source-drain interval, the shorter the carrier travel time. Furthermore, the shorter the source-drain distance, the shorter the channel width and the lower the impurity density. The thickness of the insulating layer under the gate electrode 14 is made thin enough to form an inversion layer even when the gate is kept at the same potential as the source. In the equivalent circuit of Fig. 1c, a MOS FET is drawn as an injector, but as can be seen from the structures of Fig. 1a and b, the injector is a MOS FET.
It is effectively a parallel connection of a FET and a bipolar transistor (hereinafter referred to as a BJT). Therefore, a large current can flow even in a small area, which causes high-speed operation. In the mixed operation of an injector, MOS FET and BJT, current flows as holes injected into the n ^- region at the same time as the inversion layer. If the spacing between p ⁺ regions 14 and 15 is narrow, the BJT will almost be punched through, so as the voltage across both ends increases, the current will increase. In other words, the previous stage is in a conductive state and the drive gate is at a low level (for example, 0.1 to 0.3V).
If the power supply voltage Vss is maintained at about 0.6 to 1.3 V (for example, we are considering Si and GaAs), the voltage across the injector transistor is large, and the supply current of the injector is large. . In other words, a large current flows through the drain of the driver SIT in the conductive state at the previous stage. On the other hand, the previous stage driver SIT is cut off, and the drive gate voltage is at a high level (for example,
(approximately 0.5 to 1.2 V), the voltage of the injector transistor is reduced, the supplied current is reduced, and unnecessary minority carrier injection into the driver SIT channel is controlled. Of course, it is also possible to prevent the BJT section of the injector transistor from punching through so that an almost constant current flows above a certain voltage. When the drive gate becomes high level, the SIT changes from a cut-off state to a conduction state. As the potential of the drive gate increases and the potential barrier in the channel is lowered, the holes injected from the gate further lower the potential barrier and promote injection of electrons from the source region 11 into the channel. The more holes are injected from the gate, the more electrons are injected from the source, and the drain current becomes larger. In other words, a large drain current can flow with a small channel area. As the channel area becomes smaller, the size of the drive gate also becomes smaller, which inevitably reduces the capacitance of the drive gate and increases the operating speed. Holes injected into the channel are sucked out to the fixed potential gate p ⁺ region 16, and almost no accumulation effect appears. In order to efficiently suck out the holes in the channel, it is desirable that the impurity density of the p ⁺ region 16 be as high as possible. For Si at room temperature, the impurity density in the p ⁺ region is 1×10 ¹⁷ cm ^-3 and 1×
10 ²⁰ cm ^-3 , the Fermi level differs by about 0.1V. Also, 0.1V at 10 ¹⁶ cm ^-3 and 10 ¹⁸ cm ^-3
There are varying degrees. In other words, the potential of holes in the channel is lowered accordingly, making them easier to flow out. Holes in the channel are very quickly sucked out to the fixed potential gate, reducing the accumulation effect. On the other hand, if the impurity density of the fixed potential gate p ⁺ region 16 is high, holes in the channel are sucked out more efficiently and the accumulation effect is reduced, but holes injected from the drive gate are sucked out quickly. Therefore, the hole density in the channel in the conductive state is effectively reduced, and the drain current is accordingly reduced. That is,
SIT current gain decreases. In order to reduce the drop in current gain while maintaining the effect of sucking out holes in the channel, the impurity density in the drive gate region can be increased and the impurity density in the fixed potential gate region can be lowered, for example 10 ¹⁸ to 10 As mentioned above, it is about 10 ¹⁶ to 10 ¹⁸ cm ^-3 compared to about ²¹ cm ^-3 . Alternatively, when holes from the drive gate flow into the fixed voltage gate and a current starts to flow, the resistance from the fixed voltage gate to the source region 11 is increased so that the potential of the fixed voltage gate becomes positive and high according to the current. It may be set to a predetermined value. That is, when a certain amount of current flows through the fixed potential gate, the potential becomes positive and high, and almost no holes flow into the fixed potential gate anymore.

If the purpose is to reduce the minority carrier accumulation effect as much as possible, the higher the impurity density in the fixed potential gate region, the better. The impurity density of the region is selected to be low. The impurity density of the drive gate region is chosen high to reduce gate resistance. For example, it is about 10 ¹⁸ to 10 ²¹ cm ^-3 . The width of the n ⁺ region 17 that directly connects the fixed potential gate to the source region is wider than the width of the channel, so that the n ^- region below it does not pinch off at the diffusion potential. The drain region 13 may be directly attached to the p ⁺ regions on both sides. Of course, interposing an insulator such as SiO ₂ between the drain region and the gate region reduces the gate-drain capacitance and improves the operating speed.

The structure of the present invention is not limited to that shown in FIG.
Even types with completely reversed conductivity types operate in almost the same way, just by reversing the polarity of the voltage.
A portion where a drain is not provided between the drive gate and the fixed potential gate (region 12' in Figure 1a)
This is because the minority carriers injected from the drive gate flow unnecessarily and reduce the current gain.
It is desirable to use an insulator region. This way,
Each drain becomes completely independent, eliminating malfunctions when using wired logic. p ⁺ area is ^n-
A structure is shown in which most of the n ⁺ region 11 is reached through the layer, but even if it is slightly distant or n ⁺
It may be embedded in the area 11. The planar shape also
It is not limited to this almost square shape. Of course, the shape may be circular or rectangular, and the number of drains (fan-out number) is not limited to four. For example, if a large drive capability is required, such as in the final stage of a circuit system or in a decoder section of a memory, a drain may be provided all around the drive gate to form a single drain. In order to further increase the driving capability, the length around the driving gate may be increased. In addition, it is possible to reduce the accumulation effect and control the current gain by increasing or decreasing the impurity density of the individual constant potential gate region.
It can be applied not only to cases using MOS FETs but also to all split gate structure SITLs. For example, the injector may be a BJT or FET, or the injector may be a Substrate fed type that supplies current from the substrate.
Of course, it can also be applied to shapes. A desired logic circuit can be constructed by combining a plurality of inverter circuit units as shown in FIG. 1 to obtain wired logic.

The structure of the present invention can be manufactured by conventionally known epitaxial growth techniques, diffusion techniques, ion implantation techniques, microfabrication techniques, CVD techniques, oxidation techniques, vapor deposition techniques, electrode wiring techniques, and the like.

The split gate SITL of the present invention is applied to the injector.
By introducing a MOS FET structure and operating in a mixed mode of MOS FET and BJT, a large current can flow in a small area, achieving higher density and higher speed. In addition, the impurity density in the fixed potential gate region is made different from the impurity density in the drive gate region, and when the impurity density is set high, the minority carrier accumulation effect in the channel is extremely reduced and the speed is increased, and when the impurity density is set low, the current gain is increased. Its industrial value is extremely high as it further promotes higher density and higher speeds, such as almost eliminating the accumulation effect while maintaining the same temperature.

[Brief explanation of the drawing]

FIG. 1 shows an example of the structure of a split gate SITL according to the present invention, in which a is a plan view, b is a sectional view taken along line AA', and c is an equivalent circuit of one circuit unit.

Claims (1)

[Scope of Claims] 1. The driver includes a split-gate static induction transistor, the injector includes a transistor that operates in a mixed mode of an insulated gate field effect transistor and a bipolar transistor, and the drive gate of the split-gate static induction transistor and the insulating transistor are provided. A semiconductor integrated circuit including a portion where a drain of a gate field effect transistor and a collector of the bipolar transistor are configured to be a common area. 2. In a split-gate static induction transistor integrated circuit configured such that the drain or collector of the injector transistor and the drive gate of the split-gate static induction transistor are in a common area, the impurity density of the fixed potential gate region is A semiconductor integrated circuit characterized by including a portion configured to have a different impurity density. 3. A high impurity density region of a conductivity type opposite to that of the fixed potential gate region provided along the fixed potential gate region and the fixed potential gate region are directly connected by an electrode. The semiconductor integrated circuit according to item 1 or 2.