JPH0147015B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a static induction transistor integrated circuit that operates at high density, high speed, and low power.

An example of a normally-off design of a static induction transistor (hereinafter referred to as SIT) configured with a short channel and low impurity density and applied to an integrated circuit has already been disclosed in Patent No. 1181984 (Special Publication No. 11102) Semiconductor Integrated Circuit It has been proposed and described in , and has been shown to be capable of high-density, low-power operation. I ² L integrated circuits that use normally-off SITs as driver transistors have the characteristics of being able to achieve extremely high levels of integration because they do not require isolation areas, do not require ground wiring, and can perform wired logic. There is. In addition, since the channel region consists of a high resistance region, the junction capacitance between the gate and source and between the gate and drain is extremely small, making it possible to achieve low power consumption operation in devices with relatively large gate dimensions. There is. For example, Figure 1a shows a conventional I ² L type SIT integrated circuit (hereinafter referred to as
An example of the cross-sectional structure of a SITL (referred to as I ² L-type SITL) is shown below. n ⁺ substrate 11, n ^- epi region 12, n ⁺ region 13-1, 13
-2 is a drain region, p ⁺ region 14 is a gate region of an inverted SIT, and p ⁺ region 15 is an emitter region of a lateral bipolar transistor. p ⁺ area 1
4 also serves as the collector region of the lateral bipolar transistor. 11', 13-1', 13-2', 14', and 15' are a source electrode, a drain electrode, a gate electrode, and an emitter electrode, respectively. 17 is an insulating material layer such as SIO ₂ , Si, N ₄ , Al ₂ O ₃ or AlN.

FIG. 1 shows an example of one input and two outputs.

Gate region 14 and source region 11 of inverted SIT
Since they are separated from each other and the high resistance n- region 12 is interposed between them, the gate-source capacitance becomes extremely small. For example, n-epi layer thickness 5 μm,
Propagation delay time is 30 nsec for sample with impurity concentration of 1 to 3 × 10 ¹³ cm ^-3 and p ⁺ gate region diffusion depth of 1.3 to 1.5 μm.
+ Power consumption of 0.07μW or power consumption of 1μW results in a propagation delay time of 10nsec. moreover,
If the injector voltage is increased with the aim of high-speed operation, the diffusion capacitance between the gate and source increases rapidly, which prevents high-speed operation. The accumulation effect of holes in the n ^-region also becomes extremely significant. Although the junction capacitance is large, in order to prevent the diffusion capacitance from increasing so much even when the voltage exceeds a certain level, the method shown in FIG. 1b may be used. That is,
This means that the p ⁺ gate region 14 and the n ⁺ source region 11 are almost or completely adjacent to each other. However, even with this structure, if the crystal is Si, for example, if the voltage applied to the gate exceeds 0.65V to 0.7V, the diffusion capacitance term will suddenly increase, putting a limit on the operating speed. It is.
Furthermore, the gate current is large, which reduces the current gain of the inverted SIT.

Figure 2 is an example of an I ² L type SITL that has improved the above-mentioned drawbacks. Figure 2a is a plan view showing the diffusion region;
FIG. 2b is a sectional view taken along the line A-A', FIG. 2c is a plan view of another structure, and FIG. 2d is a circuit configuration of the basic gate section. FIG. 2 shows an example of one input and two outputs. Compared to the structure in Figure 1, the second
In the structure shown, p ⁺ regions 14 and 15 and n ⁺ region 11
An insulating layer 18 is provided between them. In the case of Si, the film 18 may be a film of Al ₂ O 3 or AlN, which is usually a film of SiO ₂ , Si _{3 N 4} or a composite film thereof. Insulating layer 18 and n ⁺ region 11 are in direct contact with each other in this example, but of course they may be apart. What is shown in Figure 2 is
This is a basic gate section, and its circuit configuration is as shown in FIG. 2d. The driver transistor _T2 is an inverted SIT, and the load is a bipolar transistor (hereinafter referred to as BJT) _T1 . p ⁺ (15)−
n ^- (12)−p ⁺ (14) is the emitter of the lateral BJT,
It has become a base and a collector. n ⁺ area 11,
The p ⁺ region 14, n ⁺ regions 13-1 and 13-2 are the source region, gate region, and drain region of the inverted SIT, respectively. 11', 13-1' and 13-
2', 14', and 15' are a source electrode, a drain electrode, a gate electrode, and an emitter electrode, respectively. 1
7 is an insulating layer made of SiO ₂ , Si, N, Al ₂ O ₃ , AlN, GaO _X N _Y , or the like. The impurity density N _D and thickness (source-drain distance l) of the n ^- region 12 and the distance between the gates are determined as follows.

N _D W ² <3×10 ⁷ cm ⁻¹ and l/W >0.5. The first condition is that the channel is sufficiently pinched off only by the diffusion potential between the gate and the channel, and a potential barrier is created in the channel. The second condition is that even if a voltage similar to the diffusion potential is applied between the source and drain, a potential barrier remains in the channel under the condition that the gate and source are kept at almost the same potential. This is a condition that prevents that much current from flowing. If N _D becomes large,
l/w must be gradually increased. However, if l/w becomes too large, the resistance during conduction will increase, so it is desirable to set l/w to the value that is as low as possible to achieve sufficient interruption. Usually l/
w is set to about 2 to 5 or less. Naturally, as N _D becomes larger or l becomes shorter, the gate-to-gate interval W must be made smaller. In Figure 2 a and b, the inverted SIT
In this example, the drain regions of are arranged on the left and right,
Of course, it is also possible to arrange them one above the other as shown in Figure 2c. Insulating layer 1 between gate and source
8, the p ⁺ gate region and n ⁺
No current flows directly between the source regions. Holes injected from the gate are effectively injected only into the channel region. Therefore, the gate current is drastically reduced, and at the same time, the diffusion capacitance between the gate and source is also drastically reduced, allowing extremely fast operation. Lateral BJT emitter area 1
Since the insulating layer is also provided under the emitter region 15, almost no current flows directly from the emitter region 15 to the source region 11. For that purpose 1
Since the current flowing from 5' flows into the collector region 14 very efficiently, power consumption is also reduced. To further emphasize this trend,
The outer periphery of the p ⁺ gate region 14 and the p ⁺ emitter region 15
An insulator region such as SiO ₂ may be provided adjacent to the outer periphery of the region other than the region that operates as the base region. The n ^- region base 12 narrowed by the p ⁺ regions 15 and 14 is shown to have the same impurity density as the other n ^- regions 12, but the impurity density has been increased by ion implantation etc. Good too. Also,
The length of the base region may be set so that a neutral region remains, it may be in a punch-through state, or it may be close to a punch-through state in certain operating conditions.

Figure 2 shows the case where the load is a BJT, but
The load may be a resistance. However, as mentioned above, it is difficult to obtain normally-off characteristics unless l/W>0.5, which is disadvantageous in shortening the channel, and has the drawback of increasing resistance when conducting.

An object of the present invention is to provide an electrostatic induction integrated circuit which eliminates the above-mentioned conventional drawbacks and which operates at high density, high speed, and low energy and is suitable for shortening channels.

The present invention will be described in detail below with reference to the drawings. FIG. 7 shows the circuit configuration of a SITL with one input and two outputs, in which the load is a resistor. Figures 3 to 6
The figure shows an example in which the channel region is also composed of p ^- regions. By forming the channel region as a p ^- region, l/w can be made to a much smaller value than in the example shown in FIG. In other words, it becomes a shorter channel driver transistor. If the channel is formed in the p ^- region, the potential barrier of the channel will essentially be higher than if it is formed in the n ^- region. Therefore, even if the source-drain distance l is made shorter, it is easier to create a cut-off state. Although it depends on the impurity density in the p ^- region, a cut-off state can be achieved even if l/w is shortened to about 0.1. In a structure in which the channel is set in the p ^- region, l/w is reduced as the impurity density N _A in this region increases. The impurity density N _A and dimensions of the channel region are
When in the cut-off state, settings are made so that little or no neutral region remains between the source and the drain. Since l/w is small, the voltage drop during conduction is small and a large amount of current flows,
Extremely low impedance and low power consumption. In addition, the accumulation effect of excess carriers is small and the speed is high. In FIG. 3, the load resistance is determined by the dimensions of the ^p- region between p ⁺ region 15 and p ⁺ region 14. When aiming for higher speed operation and lowering the resistance, the spacing may be shortened, but as shown in FIG. 4, it is sufficient to provide the p region 16 to a predetermined depth with a predetermined impurity density by ion implantation or the like. It is. As shown ⁱⁿ FIG.
6', the resistance becomes smaller.

Although FIGS. 3 to 5 show the case where the p ⁺ region is provided by diffusion from the surface, the p ⁺ region may also be provided by ion implantation. In that case, it is possible to create a structure in which the p ⁺ region bulges away from the surface, as shown in Figure 6. This structure is better
It can be easily cut off and has low resistance and voltage drop when conducting.

The impurity density and various dimensions of each region in the embodiments so far will be described. n ⁺ area 11: 1×10 ¹⁸ ~
×10 ²¹ cm ^-3 degree, n ^- area 12: 1 × 10 ¹² ~ 3 ×
About 10 ¹⁵ cm ^-3 , p ^-region 12': 1 x 10 ¹³ to 1 x 10 ¹⁶
cm ^-3 degree, p ⁺ area 14 and 15: 1 x 10 ¹⁷ ~ 1 x
10 ²¹ cm ^-3 degree, n ⁺ area 13: 1×10 ¹⁸ to 1×10 ²¹
cm ^-3 (p region 16: 1×10 ¹⁵ to 1×
10 ¹⁸ cm ^-3 degree). n ⁺ area 11 and 13, p ⁺ area 1
The impurity density of 4 and 15 is preferably as high as possible without impairing crystallinity. The source-drain distance l is
Approximately 0.2 to 3μm, gate-to-gate interval W is 0.3 to 3μm
It is about m. The thickness of the insulating layer 18 is about 100 Å to about 2000 Å. In Figure 7, V _EE , Vin,
Vout indicates the power supply voltage, input voltage, and output voltage as in FIG. 2d.

Next, a specific example of characteristic improvement will be described. 8th
The figure shows an example of the planar mask dimensions and cross-sectional structure of a conventional I ² L-type SITL. Figure 8a shows a p ⁺ boron diffusion mask. n ⁺ Resistivity of substrate 11 0.01Ω−
cm, n ^- region impurity density: 4.5×10 ¹³ cm ^-3 , p ⁺ diffusion depth: 2.0-2.1 μm, source-drain spacing: 2 μm
It is m. Let Wd be the gate-to-gate interval at the mask level. The load resistor is made of p-region 16 by ion implantation.

First, FIG. 9 shows the relationship between the current and gate voltage of the inverted SIT. This is an example when the drain voltage Vd is kept at 0.5V. If a is Wd=5μm, b is
This is the case when Wd=6 μm. Id is the drain current, Ig
is the gate current. Ig is 6μm even if Wd is 5μm
However, although there is almost no difference, Id is naturally larger when Wd = 6 μm.

Figure 10 shows the gate voltage dependence of the current in an inverted SIT when a SiO ₂ layer of about 300 Å is interposed between the p ⁺ regions 14 and 15 and the n ⁺ region 11 with almost the same structure as in Fig. 8. As shown in the figure. a is when Wd=5μm,
b is the case when Wd=6 μm. Drain current Id
is almost the same as the example in Figure 9, but the gate current Ig
It can be seen that the value has become smaller by more than one order of magnitude. In other words, unnecessary gate current is reduced and current gain is increased. The reduction in gate current Ig means that the diffusion capacitance between the gate and source is reduced. The situation is shown in FIG.
a and b correspond to cases where Wd is 5 μm and 6 μm, respectively. The solid line is the result shown in FIG. 8, and the dotted line is the result of the inverted SIT of the present invention. Naturally, the gate-drain capacitance hardly changes, but the gate-source capacitance is reduced by more than one order of magnitude when the insulating layer 18 is interposed. Naturally, high-speed operation can be performed.

In a circuit configuration in which inverted SITs are connected in series as shown in Fig. 12. Drain voltage Vd and current I
The relationship is shown in FIG. A is the result of the structure shown in FIG. 8, and b is the result of the structure in which the insulating layer 18 is introduced. FIG. 13a shows that when Vd exceeds 0.75V, the current I suddenly increases. This is due to the sudden increase in the current flowing to the gate of the next stage. Insulating layer 1
In the example where 8 is introduced, Vd becomes 0.9V and a slight increase in current is observed.

FIG. 14 shows the power delay characteristics obtained by constructing a nine-stage ring oscillator using samples with different load resistance values. a is the conventional example, and b is the result of the present invention. The power consumption was around 100μW and about 2nsec. It has been shown that the delay time has been improved to 0.5nsec with the same power consumption. Figure 14b, Rc=
In the case of 510Ω, the ring oscillator's oscillation waveform still has sufficient separation between low and high levels. That is, the period is 9 ns, the rise time is about 2 ns, and the fall time is about 3 ns. It can still be done faster. Keep the load resistance as it is and use the inverted type
The size of SIT should be made a little smaller. Figure 14 shows an example where Wd=6μm, but Wd
= 5 μm, the operating speed will be about 1.5 to 2 times slower. The result in Figure 14 is p ⁺ gate region 1
4 has been obtained in a fairly wide range of cases. Since it is made by diffusion, the width of the p ⁺ gate region 14 on the surface is
It is approximately 7μm. If this region is formed by ion implantation and made thinner, the speed will be faster. Furthermore, if the channel is made into a p ^- region and the source/drain distance is shortened, the speed will be even faster.

FIG. 15 shows the gate voltage dependence of the gate-source capacitance. The solid line is the conventional example, and the dotted line is the example of the present invention. When Vg exceeds 0.7V, Cgs increases rapidly. The junction capacitance of Cgs is about 2PF, but Vg
When it becomes =0.8V, Cgs becomes 25PF. In the device of the present invention including the insulating layer 18, Cgs is extremely small even when Vg=0.8V.

It goes without saying that the examples of the present invention are not limited to those described here. Here, the source area 11
Although all explanations have been made using a substrate, it goes without saying that an n ⁺ buried region provided in a p-substrate may also be used.
Surrounding the unnecessary outer periphery of the p ⁺ gate region or emitter region that is not adjacent to the channel region or base region with an insulator such as SiO ₂ increases the current gain.
Effective for speeding up by lowering Cgs.

A structural example that further emphasizes such an example is shown in FIG. Figure 16a is a plan view, Figure 16b is a
This is a cross-sectional structure along line BB'. The channel is not surrounded by a p ⁺ gate region as in the past, but has a structure in which a part of the channel is surrounded by an insulating layer 17' made of SiO ₂ or the like. Therefore, the gate current and gate capacitance are further reduced, making it suitable for higher speeds. The distance between the p ⁺ gate and the insulator region 17' is naturally designed to be narrower than in the case where both sides are gate regions. Rather than making the entire insulator region adjacent to the channel an insulator, the area adjacent to the p ⁺ channel region is made of a thin insulating film and then placed on top of it.
If you create a structure with p ⁺ polysilicon, both sides p ⁺
This means that almost the same structure as that made in the gate region can be used. This tendency becomes even more pronounced if the p ⁺ polysilicon is directly connected to the source region through an electrode and kept at the same potential.

Although the load resistor has been described as a resistor provided inside the semiconductor, it is of course possible to use a polysilicon resistor provided on the surface insulating layer. To further increase speed, the gate region should be made as small as possible, unnecessary gate current should not flow (this will reduce the diffusion capacitance of the gate), and the distance between the source and drain should be shortened to create a small channel. To allow a large current to flow in a given area, and to set an appropriate load resistance value so that the gate and drain are not forward biased too deeply.
The forward voltage between gate and drain is at least
It is necessary to keep the voltage below about 0.6V. here,
Although the case of 1 input and 1 output is shown, the inverted type of the present invention
Since the current gain of SITL can easily be several hundred or more,
It is extremely easy to increase the number of output terminals. It is also easy to take fan outs of 10 or more.

Here, the insulating layer 18 was prepared by forming a thin SiO ₂ film on an n ⁺ substrate in advance, patterning it in a predetermined manner, opening a window, and then performing n ^- growth to prepare the _sample . Of course, an N ₄ membrane is also suitable. Further, the insulating layer 18 may be formed by implanting oxygen or nitrogen into a predetermined location by ion implantation.

[Brief explanation of drawings]

Figure 1 a and b are examples of the cross-sectional structure of a conventional I ² L type SITL, Figure 2 I is an I ² L type SITL, a is a plan view, and b is a
Cross-sectional view along line AA′, c is a plan view of another structure, d
The circuit configuration of the basic gate, FIGS. 3 to 6 are examples of the SITL cross-sectional structure of the present invention, FIG. 7 is the circuit configuration of the basic gate part, FIG. 8 is the conventional I ² L type SITL, and a is a plan view. b is a cross-sectional view, Fig. 9 is the dependence of current on gate voltage, a is when Wd = 5 μm, b is when Wd = 6 μm, and Fig. 10 is the dependence of current on gate voltage of the inverted SIT of the present invention. a is Wd = 5μm, b is Wd
= 6 μm, Figure 11 shows the drain current dependence of the gate-source capacitance Cgs and the gate-drain capacitance Cgd, where a is Wd = 5 μm, b is Wd
= 6 μm, Fig. 12 shows the circuit configuration, Fig. 13 shows the current-voltage characteristics (Wd = 6 μm), a is the conventional example, and b
is an example of the present invention, Figure 14 is the power delay characteristic (9-stage ring oscillator), a is the conventional example (Wd = 6 μm), b is the example of the present invention (Wd = 6 μm), Figure 15 is the Vg dependence of Cgs (Wd=6 μm), the solid line is the conventional example, the dotted line is the present invention, and FIG. 16 is a structural example of the SITL of the present invention, where a is a plan view and b is a cross-sectional structural example along line BB'.

Claims (1)

[Claims] 1 A first semiconductor region of a first conductivity type with high impurity density, and at least one opening having a diameter or a side length of W formed in a part of the upper part of the first semiconductor region. a first insulator region, a second insulator region formed in a part of the upper part of the first semiconductor region and separated from the first insulator region, and the first semiconductor region a second semiconductor region having a second conductivity type impurity density of 1×10 ¹³ cm ⁻³ to 1×10 ¹⁶ cm ⁻³ and a thickness l formed on top of the semiconductor region adjacent to the first semiconductor region; a third semiconductor region of a second conductivity type with high impurity density formed above the first insulator region; and a third semiconductor region of a second conductivity type with high impurity density formed above the second insulator region. and a fifth semiconductor region of a first conductivity type with high impurity density located above the opening of the first insulator region and formed on the surface of the second semiconductor region. The ratio of the l to the W, that is, l/W, is about 0.1, and an input signal is applied to the third semiconductor region, an output signal is taken out from the fifth semiconductor region, and the input signal is applied to the third semiconductor region. A semiconductor integrated circuit that includes a small number of parts that apply power supply voltage to the circuit.