JPS6232624B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a novel structure for a static induction transistor integrated circuit with very high speed operation.

An integrated circuit in which a bipolar transistor (hereinafter referred to as BJT) is arranged as an injector (load) transistor and a static induction transistor (hereinafter referred to as SIT) as a driver transistor was proposed by one of the inventors of the present application, and was issued in Patent No. 1181984 (Patent No. 1181984). Kosho 58-
No. 11102) "Semiconductor integrated circuit"), excellent characteristics of low energy, high speed, and high density have been realized. One of the inventors of the present invention has proposed an integrated circuit using an upright SIT that can operate at higher speeds while maintaining the advantages of high-density, low-energy operation (Japanese Patent Application Laid-Open No. 55-11112).
- No. 46548 "Electrostatic induction integrated circuit device".

The upright type SIT, in which the source region is provided on the surface and the buried region is the drain region, has a large conversion conductance gm, a large current gain, good frequency characteristics, and can operate at extremely high speed.

Since the current gain of the upright SIT is large, the current in the injector transistor is required to vary greatly, and the injector transistor not only supplies a nearly constant current, but also performs switching. That is, the frequency characteristics of the injector transistor also affect the operating speed. Alternatively, unnecessary current flows from the gate of the driver SIT, increasing the minority carrier accumulation effect and reducing the operating speed.

An object of the present invention is to provide a structure of a semiconductor integrated circuit that eliminates the above-mentioned conventional drawbacks and operates at high speed using an upright SIT as a driver transistor.

The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a structural example and an equivalent circuit of one unit of a semiconductor integrated circuit according to the present invention. Figure 1 shows the lateral injector (load) transistor.
This is an example of a pnpBJT with 1 input and 2 outputs in which the driver transistor is an upright type SIT. FIG. 1a is a plan view with the electrode wiring and insulating layer on the surface removed. FIG. 1b is an example of a cross-sectional structure taken along line AA' in FIG. 1a. FIG. 1c is an example of a cross-sectional structure taken along line BB' in FIG. 1a. FIG. 1d is an equivalent circuit. A P ^- substrate 11 is provided with an n ⁺ buried drain region 12, an n ^- region 13, n ⁺ regions 14, 15, 16, and P ⁺ regions 17, 18. Area 1
9 is a separation area for separating each unit. n ⁺ region 14 is the source region of the upright SIT, n ⁺ region 15 is the base extraction region of the lateral BJT, n ⁺
Region 16 is a drain extraction region of the upright type SIT. The P ⁺ region 17 is the emitter region of the lateral BJT, and the P ⁺ region 18 is the gate region of the upright SIT. The region of the P ⁺ region 18 that faces the P ⁺ region 17 serves as a collector region of the lateral BJT.
As shown in the equivalent circuit of Figure 1d, the driver
A Schottky diode _D3 is connected between the gate and source of SITT ₂ . At the same time, this example is 1
Since this is an example of two inputs and two outputs, Schottky diodes D ₁ and D ₂ are provided at the output terminals to isolate each output.

T ₁ is a lateral PnPBJT. In FIG. 1b, the gate region 18 and the base extraction region 15 are connected by the electrode 15'.
There is an ohmic contact between 15' and the P ⁺ region 18, but a shot contact is made between it and the n ⁺ region 15, forming a diode _D3 . Electrode 1
There is also a short contact between 6' and n ⁺ region 16,
A diode D ₁ is formed. In FIG. 1c, the source region 14 and the base extraction region 15 are connected by electrodes and are in ohmic contact.

There is a shot contact between the electrode 16'' and the n ⁺ region 16. A diode _D2 is formed. 17' is the emitter electrode and 18' is the gate electrode. _VEE is the power supply, Vin is the input voltage, and Vout is the The output voltage is shown.The source region is grounded.20 is
It is an insulating layer of SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , AlN, etc., or a composite insulating layer or multilayer insulating layer of these.
Isolation region 19 is also made of a similar insulator.

The current gain of an upright SIT can easily exceed 100. In the low current range, it can reach several thousand.
Therefore, if the diode _D3 were not present, the previous stage would be in a cutoff state and most of the current in the injector _T1 would flow into the channel from the gate of the driver SIT. Assuming that the current gain of the driver SIT is, for example, 100, in this example with two outputs, the current flowing into the gate only needs to be 1/50 of the current taken out from the drain. That is, 99% of the current supplied from the injector (if the current of the injector transistor is approximately constant) is ultimately unnecessary. A means to bypass this current is to introduce diode _D3 . In other words, when Vin is at a high level and Si is used, for example 0.7V, the short metal and its area are selected so that most of the current flowing from the injector will flow to diode _D3 . . To increase the shot barrier, Ni, Pd, Pt, etc. may be used. If it is Al, it is a little low, but in that case, you can adjust it by reducing the area. In such a configuration, the current in the injector BJTT ₁ can remain almost constant, and its switching characteristics have little effect on operation. The injector current flows to the drain of the previous stage when the previous stage is in a conductive state. When the previous stage is cut off, the driver
It flows into the gate of SIT and causes its potential to rise rapidly. After reaching the predetermined gate potential, most of the injector current will flow through the shotgun diode _D3 . A Schottky diode _D3 is formed between the electrode 15' and the n ⁺ region 15. The value of the flowing current may be controlled by the barrier height and area. Since FIG. 1 shows an example of two outputs, shot diodes D ₁ and D ₂ are provided to separate the output terminals. In order to increase the noise margin of operation, it is desirable that the barrier heights of D ₁ and D ₂ be as small as possible within a range where current does not flow in the opposite direction due to thermal excitation. For example, if Si is Ti
If you use , you can get a forward voltage drop of about 0.25 to 0.3V. A small forward voltage drop is also achieved with Mg. Therefore, the forward voltage drop of D ₁ and D ₂ is designed to be as small as possible. _D1 ,
D ₂ is formed between the electrodes 16', 16'' and the n ⁺ region 16. If the resistance between the n ⁺ region 12 and the electrodes 16', 16" is not a problem, there is no n ⁺ region 16. It's okay. In order to further reduce the resistance,
It is only necessary to make n ⁺ region 16 deeper, and n ⁺ region 1
2, it becomes very small.
The forward voltage drop of D ₃ may be determined in relation to the desired high level. With this configuration, the frequency characteristics of the injector transistor have almost no effect on the operation, and the gate potential of the driver SIT rises in an extremely short period of time. from being injected into the channel. In other words, even at the time of interruption, the accumulation effect of minority carriers is reduced, and the speed becomes extremely high.

If the gate-drain distance of the driver SIT is too deep and becomes forward biased, the operating speed will decrease rapidly. For example, in the case of Si, if the gate-drain voltage is forward biased to more than about 0.4V, the speed decreases rapidly. In order to suppress this effect, a Schottky diode _D4 may be provided between the gate and drain of the SIT, as shown in the equivalent circuit of FIG. In this structure, the forward bias depth between the gate and drain of driver SITT ₂ is limited to less than the forward drop voltage of D ₄ . The forward voltage drops of the diodes D ₁ , D ₂ , D ₃ , and D ₄ are assumed to be Vf ₁ , Vf ₂ , Vf ₃ , and Vf ₄ . On the other hand, let the high level of the input and output be _VH , and the low level be _VL .

The following relationship exists between these quantities: V _H ≈V _L +Vf ₄ −Vf ₁ V _H ≈Vf ₃ . For example, in the case of Si, V _H ≒0.7V, V _L ≒0.5V,
Vf ₁ ≒0.2V, Vf ₄ ≒0.4V, and Vf ₃ ≒0.7V. In this example, the voltage drop when SITT ₂ is conductive is 0.3V, and the voltage drop between gate and drain is 0.1V.
It will be forward biased. Since a Schottky diode is inserted into the output terminal, the logic voltage amplitude, that is, the difference between high and low logic levels, is reduced accordingly. As much as the logic width, the gate
It is preferable to only forward bias between the drains to improve speed. In this numerical example, the logic width is 0.2V.

To create a forward bias between the gate and drain equal to the logic amplitude, the shot diode at the output terminal can be removed. For this purpose, it is sufficient to limit the number of output terminals of one unit to one. An equivalent circuit of this example is shown in FIG. The forward bias value between the gate and drain of SIT is determined only by the forward voltage drop of the Schottky diode _D4 . For example, Vf ₄ can be set to a value of about 0.25V. In this example, the relationship V _H =V _L +Vf ₄ exists. The logic width is Vf ₄ . The Schottky diode _D4 can be constructed by connecting the gate region 18 and the n ⁺ region 16 with an electrode, and forming a Schottky junction between the electrode and the n ⁺ region 16. The area and type of metal may be selected to achieve desired values.

The SIT used in the driver is designed to be normally off. That is, when the gate is at zero voltage, no current flows even if a predetermined voltage (high level voltage) is applied to the drain. Effective gate spacing W, gate source distance
Let the length in the drain direction be l. Also, if the impurity density of the channel is N _D , then N _D W ² <2.0×10 ¹⁵ cm ^-3
(W is in μm), dimensions and impurity density are selected so as to satisfy the condition of l/w20.7.

So far, we have mainly discussed the case where Si is used. When GaAs is used, the recombination time of the injected minority carriers is short, and the speed at which the driver SIT is shut off is extremely fast, making it suitable for high-speed operation. The high electron mobility allows more current to flow than in Si with the same dimensions, which also helps speed up the process. When GaAs is used, each region is often constructed on a semi-insulating substrate instead of the P ^- substrate 11. The isolation region 19 and the insulating layer 20 may be made of the above-mentioned insulator, or may be made of an insulator such as GaOxNy. Alternatively, the isolation region 19 may be made into an insulator by irradiating GaAs with protons. As the shot metal, Pt, Au, Be, Ag, Al, W, Ti, or other metals may be used.

It goes without saying that the semiconductor integrated circuit of the present invention is not limited to the structure shown in FIG. It goes without saying that the conductivity type may be reversed. However, in GaAs, InP, etc., the mobility of holes is small, so when a P channel SIT is used as a driver, not much speed can be expected. The separation region 19 may be relatively deep. The short electrodes may be provided in appropriate locations in the overall layout where they can be easily provided. In any case, it is sufficient to have a structure in which an upright type SIT is used as a driver transistor, and a shot diode for effectively bypassing the injector current is inserted between the gate and source of the driver SIT. . The injector may be a FET or a MOSFET.

By using the semiconductor integrated circuit of the present invention, all desired logic gates can be realized using wire logic.

The semiconductor integrated circuit of the present invention can be manufactured using conventionally known crystal technology, crystal growth technology, oxidation, diffusion, ion implantation technology, etching technology, photolithography technology,
It can be easily manufactured using microfabrication technology, CVD technology, (wiring technology), etc.

A semiconductor integrated circuit in which the upright type SIT of the present invention is used as a driver transistor and a shot diode is inserted between the gate and source of this SIT suppresses unnecessary injection of minority carriers from the gate, resulting in an upright type SIT. Taking advantage of SIT's high GM, high current gain, and good frequency characteristics, it can operate at extremely high speeds, and has a high degree of integration, making it of high industrial value.

[Brief explanation of the drawing]

FIG. 1 shows the SIT integrated circuit unit of the present invention, in which a is a plan view, b is a sectional view taken along line AA', c is a sectional view taken along line BB', and d is an equivalent circuit. It is an equivalent circuit of another embodiment of the SIT integrated circuit of the present invention.

Claims (1)

[Scope of Claims] 1. A first semiconductor region of a first conductivity type with high impurity density formed at least in a common portion on a semiconductor substrate, and a first conductivity type semiconductor region formed on an upper part of the first semiconductor region. a second semiconductor region with low impurity density;
third and fourth semiconductor regions of the first conductivity type with high impurity density formed in a part of the upper part of the semiconductor region; a fifth semiconductor region of a second conductivity type with a high impurity density located at an intermediate portion between the fourth semiconductor region and the fourth semiconductor region and surrounded by the fourth semiconductor region; A second semiconductor region formed in a part of the upper portion at a position facing the fifth semiconductor region with respect to the third semiconductor region.
a sixth semiconductor region of conductivity type with high impurity density; a first ohmic contact electrode formed on the top of the sixth semiconductor region; and a second ohmic contact formed on the top of the fifth semiconductor region. an electrode, a third ohmic contact electrode formed on the top of the fourth semiconductor region, a first Schottky contact electrode formed on the top of the third semiconductor region, and a third ohmic contact electrode formed on the top of the third semiconductor region; a first wiring layer electrically connecting second and third shot key contact electrodes formed on the top, the first shot key contact electrode, and the second ohmic contact electrode; and the first shot key electrode. and a second wiring layer that electrically connects the first ohmic contact electrode and the second ohmic contact electrode.
A semiconductor integrated circuit characterized in that a power supply voltage is applied between the wiring layer and the wiring layer, an input signal is applied to the second ohmic electrode, and an output signal is taken out from the second shot key electrode. 2 the third shot key contact electrode and the second shot key contact electrode;
2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is electrically connected to an ohmic contact electrode. 3. A first semiconductor region of a first conductivity type with a high impurity density formed in at least a common portion on a semiconductor substrate, and a second semiconductor region of a first conductivity type with a low impurity density formed on an upper part of the first semiconductor region. a semiconductor region of
third and fourth semiconductor regions of the first conductivity type with high impurity density formed in a part of the upper part of the semiconductor region; a fifth semiconductor region of a second conductivity type with a high impurity density located at an intermediate portion between the fourth semiconductor region and the fourth semiconductor region and surrounded by the fourth semiconductor region; A second semiconductor region formed in a part of the upper portion at a position facing the fifth semiconductor region with respect to the third semiconductor region.
a sixth semiconductor region of conductivity type with high impurity density; a first ohmic contact electrode formed on the top of the sixth semiconductor region; and a second ohmic contact formed on the top of the fifth semiconductor region. an electrode, a third ohmic contact electrode formed on the top of the fourth semiconductor region, a fourth ohmic contact electrode formed on the top of the second semiconductor region, and a third ohmic contact electrode formed on the top of the second semiconductor region; a first shot key contact electrode formed on top of the second semiconductor region; a second shot key contact electrode formed on top of the second semiconductor region;
a first wiring layer that electrically connects the first shot key contact electrode and the second ohmic contact electrode; and a first wiring layer that electrically connects the first shot key contact electrode and the third ohmic contact electrode. a second wiring layer and a third wiring layer electrically connecting the second shot key contact electrode and the second ohmic contact electrode; A semiconductor integrated circuit characterized in that a power supply voltage is applied between the second wiring layer, an input signal is applied to the second ohmic electrode, and an output signal is taken out from the fourth ohmic contact electrode.