JPS6329836B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tunnel injection transistor having a shotgun junction as an injection electrode and an integrated circuit using the same.

Until now, Schottky junctions have been used in transistors for the gate and drain control electrodes of field-effect transistors (FETs). It has never been used for emitters or sources that supply carriers. This is because if used as an emitter or source, the bias will be reversed in normal operation and carrier injection cannot be performed.

The inventors of the present application previously proposed a new transistor that operates using a shotgun junction in the carrier supply region (Japanese Patent Application Laid-open No. 76574/1983: shotki injection electrode type semiconductor device). Here, we will explain its basic structure and operating principle. FIG. 1 is a band diagram near a metal n-type semiconductor shottock junction. 11 is an n-type semiconductor, 12 is an end of a conduction band, 13 is an end of a charging band, 14 is a Fermi level, and 15 is a metal. _B is the barrier height, ε _C is the conduction band edge energy, and ε _F is the Fermi level. The depletion layer width W, where the impurity density of the region 11 is N _D , is is given by The commonly used shotgun joint
_B is set high enough to prevent electrons from the metal side from crossing the barrier and being injected into the semiconductor side. Furthermore, the magnitude of _B is mostly determined by the type of metal and semiconductor, and cannot be controlled by a control electrode. FIG. 2 shows an example of the cross-sectional structure of a shottock junction transistor having a shottock junction as an emitter. The n ⁺ region 21 is a collector region (or may also be called a drain region),
The n region 22 is a channel, the p ⁺ region 23 is a gate region, 24 is a metal electrode forming a shot junction, and 21' and 23' are a collector electrode and a gate electrode, respectively. If 26 is a semiconductor or Si, then
Insulators such as SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , AlN, etc. or composite insulators of these, and GaAs
These are Si ₃ N ₄ , Al ₂ O ₃ , AlN, GaOxNg, etc., or composite insulators thereof. Along the line X-X' in Figure 2,
Figure 3 shows the potential distribution from the emitter to the collector. A predetermined positive voltage Va is applied to the collector. FIG. 3a shows the case when the gate voltage Vg=0, and FIG. 3b shows the case when the gate voltage Vg>0. Vg
If =0, for example, even if a positive voltage is applied to the collector, no current will flow because the Schottky junction is reverse biased. In this state, when a predetermined positive voltage is applied to the gate, holes are injected from the p ⁺ gate region. The injected holes flow into the highest part of the potential distribution shown in FIG. 3, that is, just before the shotgun emitter. Since the holes do not immediately flow out to the metal electrode, they remain just in front of the shotgun emitter. If the hole density near the emitter is P, the depletion layer width is
approximately It gradually becomes narrower. Since the collector voltage Va is applied, the actual value of W will be slightly different, and of course the hole density P will also be spatially distributed, so W can be expressed by a more complicated expression than Equation (2). However, there is basically no error even if you use equation (2) as an approximation. In any case, if there is a place with a high potential, holes will flow into it. The potential distribution in a state where some holes have been injected is as shown in FIG. 3b. In other words, the potential barrier width is becoming narrower. Although it depends on the size of _B , if this potential barrier width becomes narrower than several hundred angstroms, electrons will tunnel from the metal to the semiconductor and flow into the collector. In other words, current begins to flow. In this transistor, the width rather than the height of the potential barrier is controlled by the gate,
Electrons in the shotgun emitter region are injected into the channel by tunneling. This transistor can be called a Schottky Emitter due to its structure.
Transistor (SET) or Schottky Source
It can also be called Transistor (SST), and from the principle of operation it can be called Injected Carrier Induced Tunnel.
It may also be called an injection transistor (TIT).
Here, we will call it TIT.

To cut off the TIT when it is conducting,
Just return Vg to zero. Some of the holes that entered the channel disappear by recombination at the Schottky junction interface, and the rest are absorbed into the P ⁺ gate region.
In order to quickly absorb holes into the P ⁺ gate region, the P ⁺ gate interval should not be too wide. For example, in a zero gate bias state, the diffusion potential of the P ⁺ gate region and the n-channel region should be such that the depletion layer extending from the P ⁺ gate region to the n-side is approximately connected at the center of the channel or more completely connected. If the P ⁺ gate spacing is 2a, it will be about N(2a) ² 1×10 ⁸ cm ^-1 . If the depletion layer is completely connected, holes will return to the P ⁺ gate region quickly, allowing high-speed operation. Of course, when the operating speed does not need to be so fast, the gate spacing may be wider. TIT is
Since the cut-off is achieved by a shotgun junction, the cut-off characteristics do not deteriorate even if the gate interval is widened. In TIT, some of the electrons injected into the channel during conduction are P ⁺
This flows into the gate region, increases the gate current, and becomes a factor that deteriorates the current gain.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a short-circuit junction transistor that eliminates the above-mentioned drawbacks, and to provide an integrated circuit using a short-circuit junction transistor.

The present invention will be described below with reference to the drawings.

Due to its operation and structure, TITs are applicable to all integrated circuits using conventional bipolar transistors. In other words, TTL (Transistor
Transistor Logic), ECL (Emitter Coupled
Logic), NTL (Non-Threshold Logic), STL
(Schottky Transistor Logic), ISL (Integrated
Schottky Logic) et al. That is, T.I.T.
−TTL, TIT−ECL, TIT−STL, TIT−ISL
As it was said. In such an integrated circuit configuration, the driver transistor is composed of a TIT.

First, we will explain TIT-STL, which is most suitable for applying TIT.

FIG. 4 shows an example of its cross-sectional structure. 36-
34-35-32 is TIT. An n ⁺ collector region 32 is provided buried on a p-substrate 31 . N region 34 is a channel region, P ⁺ region 3
5 is a gate region, 36 is a short emitter region, and 35' is a gate electrode. 37 is a shot electrode for clamping between the gate and collector of TIT. Reference numerals 38-1 and 38-2 are short electrodes for making the output terminals independent when performing wiring logic, and serve as output terminals. 39 is a separation region, usually made of _SiO2 . 40 is an insulator.
P' region 41 is a channel stopper region.
FIG. 5 shows the circuit configuration of the TIT-STL shown in FIG. 4.
Since there is no fixed symbol for TIT, the symbol for static induction transistor (SIT) is used for convenience. Vin is the input voltage, Vout is the output voltage, V _DD
(10) is the power supply voltage. V is the forward voltage drop of the shotgun diode for gate-collector clamping, and V' is the forward voltage drop of the output terminal shotgun diode. RL is the load resistance. Fourth
Although the load resistor part is not shown in the figure, it is usually formed of a polysilicon resistor on an insulator. Of course, if a certain degree of deterioration in characteristics can be tolerated,
Diffusion resistance may also be used. Inverter operation is bipolar
It is exactly the same as STL. If Vin is at a high level (V+Vd: Vd is the voltage drop when TIT conducts), TIT is conductive and Vout is at a low level (Vf′+
Vd). If Vin is low level, Vout is high level. In other words, the logic amplitude is (Vf − Vf′)
is given by Considering the noise margin, (Vf−
Vf′) is normally required to be about 0.2V or higher. In special cases, it may be smaller. The type and area of the shot metal are selected to ensure this. In TIT-STL, when conductive, the gate and collector are forward biased by Vf, so in the structure shown in FIG. 4, direct contact is made between the gate and collector so that the diffusion capacitance between them does not increase. If Vf is about 0.6V or more, the capacitance between the two regions will be smaller if P ⁺ and N ⁺ are in direct contact, and Vf will be
If it is as small as 0.6V, the capacitance will be smaller if a high-low resistance region is interposed between the P ⁺ and n ⁺ regions.

If you shorten the distance between the emitter and collector and shorten the gate interval, for example,
If the gate spacing is set to about 1 μm or less, and the gate spacing is set to about 1 to 2 μm or less, the operating speed of the TIT-STL becomes extremely fast. When the operating speed is sufficiently fast,
The area between the n ⁺ collector region and the substrate affects the operating speed. The smaller the collector-to-substrate capacitance is, the more desirable it is. If the impurity density of the P substrate 31 is lowered in an attempt to reduce the capacitance, the width of the depletion layer extending from the n ⁺ collector region to the substrate side changes extremely slowly, making it impossible to perform fast operation. Increasing the impurity density of the P substrate increases the capacitance and reduces the operating speed. A structure in which this defect has been eliminated is shown in FIG.
The substrate is a P ⁺ substrate, and a high resistance region 42 of the P ^- or i layer is provided between the P ⁺ substrate and the n ⁺ collector region. The thickness and impurity density of the region 42 may be selected such that the diffusion potential with the n ⁺ region is substantially or completely depleted.

It is desirable that Vf' of the output end shot diode be as small as possible. It is sufficient that the current does not flow in the opposite direction. At the same time, the lower the barrier height of the TIT emitter, the easier it is to flow current with a small amount of hole injection from the gate, so it is desirable that the barrier height be lower.
Therefore, it is preferable that at least 36 and 38 be made of the same metal. For 37, Vf may be increased by making the area of the shot hole small, or it may be made of a metal with a high barrier.

The examples shown in FIGS. 4 and 6 are structures mainly for Si. On the other hand, in GaAs, a semi-insulating region can be easily obtained.

FIG. 7 shows an example of the cross-sectional structure when the TIT-STL is made of GaAs. On the semi-insulating substrate 71,
Each of the n ⁺ layers and n layers is grown to a predetermined thickness. The insulating region 79 for gate isolation is formed by proton irradiation. The P ⁺ gate region 74 is formed by ion implantation of Be, Cd, or the like. The n ⁺ region 72 is a collector region, and the n region 73 is a channel region.
75 is a shot emitter, 74' is a gate electrode,
Reference numeral 77 represents a shot connection electrode for gate collector clamping, and 78-1 and 78-2 represent output terminal shot connection electrodes. 80 is Al ₂ O ₃ , AlN,
This is an insulating layer made of GaOxNy, etc. In this example, since the n ⁺ region and the n region are formed by epitaxial growth, the accuracy of the thickness is extremely high.
It can be formed with an accuracy of about 0.1 μm. For example n ⁺
The thickness of the region is approximately 0.5 to 1 μm, and the thickness of the n region is approximately 0.3 to 1 μm. Of course, it may be thicker or thinner than this. Further, an n region may be left between the P ⁺ gate and the n ⁺ collector. In Figure 6, load resistance RL
Although not shown in the figure, it may be made of a diffused resistor, or polysilicon may be formed on an insulator using a low-temperature plasma CVD process to serve as a load.
The width of n region 73 is approximately 0.3 to 2 μm. The impurity densities of the n ⁺ collector region, n region, and P ⁺ gate region are approximately 5×10 ¹⁷ to 5×10 ¹⁸ cm ^-3 and 1
×10 ¹⁴ to 1 × 10 ¹⁷ cm ^-3 , 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm
It is about ^-3 . In the case of GaAs, the electron mobility is high, so the current can be increased even in the same area, allowing high-speed operation.

In the examples described so far, the case has been described in which the collector region, channel region, and gate region are all made of the same material. In this case, some of the electrons injected from the emitter into the channel become P ⁺
This flows into the gate region, contributing to a decrease in current gain.

A structure that overcomes this drawback is shown in FIG. Individual
The cross-sectional structure of TIT is shown in FIG. n ⁺
Collector region 51, n-channel region 52, P ⁺
They are a gate region 53, a shot emitter 54, a collector electrode 51', and a gate electrode 53'. 56 is an insulating layer. The basic structure is the previous TIT
is the same as However, in this structure, the forbidden band width of the P ⁺ gate region is made wider than the forbidden band width of the channel region. In other words, a heterojunction is formed between the gate channels. Assuming that the forbidden band width of the P ⁺ gate region is ε _g2 and the forbidden band width of the channel region is ε _g1 , when the gate and channel are formed by a heterojunction, the channel width is smaller than when they are formed by a homojunction. The height of the conduction band edge of the gate as seen from the conduction band edge of is always higher by (ε _g2 −ε _g1 ). Although it depends on the density of states in both regions, (ε _g2 −ε _g1 ) is
If it is about 0.1 eV or more, the electrons in the channel become P ⁺
There is almost no flow into the gate. In other words, all electrons injected into the channel from the emitter flow into the collector, except for those that are annihilated by recombination. A heterojunction is formed between the gate and channel. If the number of interface states is small, the recombination current at the interface will increase, and the current gain will actually decrease. For example, Si-SIPOS (Semi-SIPOS) is a heterojunction with few interface states.
Insulating Polycrystaline Silicon), GaAs−
Ga _1-x Al _x AS, GaAs−GaAs−Ga _1-x Al _x As _1-y P _y
etc.

FIG. 9 shows a cross-sectional structure of a planar TIT having a heterojunction between the gate and the channel. A TIT is constructed on the P substrate 51, and the n ⁺ collector region is a buried region.
57 is an insulating layer. P' region 58 is a channel stopper region. Other areas are the same as in FIG.

A structure in which a high resistance region 59 is interposed between the n ⁺ collector region and the substrate is shown in FIG. 1st
The structure shown in FIG. 0 also shows an example in which the channel region is not uniform and is divided into two impurity density regions. The impurity density of the n1 region 53-2 is
Usually, the impurity density is lower than that of n2 region 53-1. Hole injection from the gate is mainly 53-
It is designed to be carried out only in 2 cases. at the same time,
The impurity density in the region near the collector is set high so that the space charge resistance does not increase due to the high density of electrons injected from the emitter.

FIG. 11 shows a planar heterojunction TIT using a material such as GaAs that can easily form a semi-insulating region by itself. semi-insulating substrate 91,
n ⁺ collector region 92, n channel region 93,
P ⁺ gate region 94, shortcut emitter 95,
n ⁺ collector extraction region 97, region 99 made semi-insulating by proton irradiation, insulator 9
It is 8. 97' is a collector electrode.

When the gate and collector are deeply biased in the forward direction, the diffusion capacitance that appears between the gate and collector becomes smaller if current does not flow in the forward direction between the gate and collector. That is,
This allows for high-speed operation. If the P ⁺ gate is made of a material with a wide forbidden band width, even if the gate-collector is forward biased,
No electron injection from the n ⁺ collector region to the P ⁺ gate region occurs. However, hole injection from the P ⁺ gate region to the n ⁺ collector region occurs. This hole injection from the gate to the collector can be almost suppressed if the n ⁺ collector region is also made of a material with a wider forbidden band width than the channel.

Heterojunction shown in FIGS. 8 to 11
TITs can of course be used in integrated circuits.
Since the current gain is large and the diffusion capacitance between the gate and emitter and between the gate and collector is small, it is naturally possible to operate at high speed.

It goes without saying that the heterojunction short emitter transistor of the present invention is not limited to the structure described here. Although only a surface gate structure is shown here, it goes without saying that a buried gate structure or a notched gate structure may also be used. In addition, integrated circuits using Schottky emitter transistors are easy to manufacture, have a large current gain, allow a large current to flow in a small area, have a large conversion conductance, and can operate at high speed. is extremely high.

[Brief explanation of the drawing]

Figure 1 is a band diagram near the metal/n-type semiconductor Schottky junction, Figure 2 is the cross-sectional structure of a Schottky injection electrode transistor, and Figure 3 is the source/drain of the transistor in Figure 2 along the X-X' direction. In the potential distribution between a and Vg=0, a is
b is Vg>0, Figure 4 shows STL using TIT
Figure 5 is a cross-sectional structural diagram of Figure 4, the circuit configuration of Figure 6 is
Figures and Figure 7 show the cross-sectional structure of STL using TIT.
8 to 11 show cross-sectional structures of transistors of the present invention.

Claims (1)

[Scope of Claims] 1. A metal electrode in short contact with an n-type semiconductor region is used as an emitter, and an n-type high impurity density region is provided at a position adjacent to the n-type semiconductor region and facing the metal electrode to form a collector region. In a structure in which a p-type high impurity density region is provided near the metal electrode so as to substantially surround the n-type semiconductor region to serve as a gate region, the forbidden band width of the gate region is set to the n-type semiconductor region. The shot barrier width is controlled by applying a forward bias voltage between the gate region and the n-type semiconductor region, and carriers are injected from the shot contact into the n-type semiconductor region by tunnel injection. A semiconductor device characterized by performing the following. 2 A metal electrode that is in direct contact with the n-type semiconductor region is used as an emitter, and a high n-type impurity density is provided at a position adjacent to the n-type semiconductor region and facing the metal electrode, and the bandgap width of the n-type semiconductor region is higher than that of the forbidden band width of the n-type semiconductor region. In a structure in which a region having a wide forbidden band width is provided as a collector region, and a p-type high impurity density region is provided near the metal electrode so as to substantially surround the n-type semiconductor region, as a gate region, The shot barrier width is controlled by making the forbidden band width of the gate region wider than the forbidden band width of the n-type semiconductor region and applying a forward bias voltage between the gate region and the n-type semiconductor region. A semiconductor device characterized in that carriers are injected into the n-type semiconductor region by tunnel injection from contact. 3. A metal electrode in occasional contact with the n-type semiconductor region is used as an emitter, an n-type high impurity density region is provided at a position adjacent to the n-type semiconductor region and facing the metal electrode to serve as a collector region, and the metal electrode A gate region is provided near the n-type semiconductor region with a p-type high impurity density and a wider forbidden band width than the n-type semiconductor region, and the gate region and the n-type A shot injection electrode type transistor is used as a driver transistor, which controls the shot barrier width by applying a forward bias voltage between the semiconductor regions and injects carriers from the shot contact into the n-type semiconductor region by tunnel injection. A semiconductor device characterized by: 4. A metal electrode in occasional contact with the n-type semiconductor region is used as an emitter, and has a high n-type impurity density at a position adjacent to the n-type semiconductor region and facing the metal electrode, and is wider than the n-type semiconductor region. A region having a forbidden band width is provided as a collector region, and a forbidden band width is provided in the vicinity of the metal electrode and has a p-type high impurity density and has a wider forbidden band width than the n-type semiconductor region so as to substantially surround the n-type semiconductor region. The shot barrier width is controlled by applying a forward bias voltage between the gate region and the n-type semiconductor region, and carriers are injected from the shot contact into the n-type semiconductor region by tunnel injection. A semiconductor device characterized in that a shot injection electrode type transistor that performs this is used as a driver transistor.