WO1983002369A1

WO1983002369A1 - Semiconductor tetrode

Info

Publication number: WO1983002369A1
Application number: PCT/HU1982/000067
Authority: WO
Inventors: Központi Fizikai Kutato Intézet Mta
Original assignee: Mohacsy, Tibor; SZUHAR, Mihály; ZIMMER, György
Priority date: 1981-12-23
Filing date: 1982-12-23
Publication date: 1983-07-07
Also published as: IT1153688B; EP0096686A1; JPS58502175A; HU183760B; IT8224911A1; EP0096686A4; IT8224911A0

Abstract

Process and embodiment for production of a semiconductor tetrode. The essence of the process in accordance with the invention lies in that double diffusion or implantation is made into a semiconductor substrate to ensure p-n-p or n-p-n bipolar transistor structure along the surface which contains emitter, base and collector. After the creation of this semiconductor structure an isolation layer and an extra electrode are made over the base. After the above steps contact windows are opened over the emitter, base and collector and leads are provided to them and to the extra electrode. The embodiment in connection with the invention contains emitter, base and collector layer in a semiconductor substrate and an isolation layer on it. It contains further an extra electrode over the base on the isolation layer and the emitter base, collector and the extra electrode are connected to leads. The semiconductor tetrode in connection with the invention is essentially a bipolar transistor supplied with an extra controlling electrode which enables continuous regulation of the main electronic parameters of bipolar transistors and makes possible the correction of parameter divergence inevitably resulting from the technology. The tetrode in connection with the invention is particularly useful in creating special amplifiers, in simplifying circuits and in creating devices with input resistance similar to MOS transistors and with output resistance and saturation voltage similar to bipolar transistors.

Description

SEMICONDUCTOR TETRODE

The invention relates to a method of a producing a semiconductor tetrode.

It is well known that the bipolar transistor is one of the fundamental components of sophisticated electronics. It has found a wide range of application in digital and analog techniques either as a discrete element or as a component of integrated circuits.

Because bipolar transistors are more advantageous than are electronic tubes in respect both of production and of achievable electronic parameters, they have, apart from some very special applications, replaced electronic tubes. Moreover, sophisticated means of serial production has led to significant decrease in the cost of manufacture of bipolar transistors.

The bipolar transistor is a semiconductor device containing three electrodes, viz. emitter, base, collector. The operation of such bipolar transistors can be characterized by the relatively small base current (input signal at the most general applications) determining a relatively high emitter current in jected into the base region which, after some loss (base current), is collected by the electric field of the collector and ensures a collector current (output signal at the most general applications) which is proportional to the base current. This above mode of operation is the reason that the bipolar transistor is widely used as an active element of different circuits such as amplifiers, buffers, gates, etc. It is pointed out, however, that due to the complex technology, bipolar transistors have the disadvantages that the accurate adjustment of their electronic parameters is difficult and the tolerance which should be allowed is high. The single governing capability of bipolar transistors makes its employment difficult or sometimes impossible in certain fields of application. Additionally, the significantly lower input resistance relative to that of electronic tubes or MOS devices represents a higher load for the drivers.

When the tolerance of one or more parameters is a decisive requirement then the use of a highly accurate measurement technique and classification by quality control of devices are needed which of course increase the costs and lower production yield thereby decreasing economic efficiency. Obviously if these requirements are increased, these adverse effects are similarly increased.

When more then one controlling capability is needed then the use of a circuit containing more discrete devices or integrated elements is unavoidable which of course increases the cost.

Moreover in numerous applications even if significant economic disadvantages are allowed one cannot increase the technical level already achieved by the use of bipolar transistors.

The aim of the invention specified here is to eliminate simultaneously all the aforementioned deficiencies of the said bipolar transistors and to develop a semiconductor device which is able to remove the high divergence introduced by technology and is able to provide adjustment of the electronic parameters in a wide range without changing the technology.

Accordingly, the task solvable by the invention is to create a process and embodiment which fulfils the aforementioned purposes and ensures an extra governing possibility for controlling the collector current.

The invention is based on the recognition that be applying a bipolar transistor supplied with a controlling electrode, i.e. a semiconductor tetrode, instead of using traditional bipolar transistors the task cited can be solved.

The process described by the invention is developed on the basis of a known process during which couble diffusion or implantation is made in a semiconductor material thus creating a p-n-p or n-p-n transistor structure which contains emitter, base and collector regions then on the isolation layer created automatically over the semiconductor surface during this process contact windows are opened and leads are made for the emitter, base and collector regions.

The development provided by the said invention lies in that a special isolation layer is created over the base after the diffusion or implantation and an extra electrode supplied with a lead is placed on this isolation layer. It seems to be expedient if this said extra electrode, its lead and the leads earlier mentioned are made at the same time from identical material.

It also seems to be expedient if at first only the extra electrode is formed and the leads are made after this from unidentical material.

Moreover it is expedient if the diffusion or implantation is made in an epitaxial layer created earlier on the semiconductor material, i.e. on a semiconductor substrate.

further on it is expedient if the diffused or implanted layers are replaced entirely in the epitaxial layer.

Further on it is expedient, too, if the diffused or implanted base is replaced partly in the epitaxial layer.

The embodiment described by the invention is developed on the basis of a known embodiment which contains emitter, base and collector regions in a semiconductor material and isolation layer with contact windows and leads over it.

The development, i.e. the invention, lies in that there is an extra electrode on the isolation layer over the base and the emitter, base and collector layers replaced in the semiconductor material as well as the extra electrode connected to leads.

In the sense of the invention it seems to be expedient if the base lead is connected directly to the base layer. It also seems to be expedient if the base layer is connected to the base lead through a base stretching layer.

Moreover it is expedient if the embodiment contains an epitaxial layer.

Further on it is expedient if the base layer and the base lead are connected through the semiconductor substrate.

The invention will be described in detail by means of a known embodiment and some prefered embodiments belonging to the invention, with the aid of the accompanying drawings, wherein: figure 1 is the layout of a known embodiment, figure 2 is the cross section of a known embodiment, figure 3 is the layout of an embodiment according to the invention (first example), figure 4 is the cross section of an ambodiment according to the invention (first example), figure 5 is the layout of another embodiment according to the invention (second example), figure 6 is the cross section of another embodiment according to the invention (second example), figure 7 is the layout of a further embodiment according to the invention (third example), figure 8 is the cross section of a further embodiment according to the invention (third example), figure 9 characteristics of an embodiment according to the invention.

The identical reference numbers in the figures denote the same parts. The known embodiment is to be seen in figures 1 and 2. Pigure 1 shows the layout and figure 2 the cross section of a possible embodiment of bipolar transistor produced with the help of planar technology. This possible embodiment contains, in the semiconductor substrate 11, base layer 12, emitter layer 13, collector layer 20 and on the surface of the semiconductor substrate 11 isolation layer 2L and further on base 15, emitter 17, collector 19 leads connected to the different said layers through base 14, emitter 16, collector 18 contact windows.

As is known during the planar technology used for producing bipolar transistors at first a layer of oposite conductivity is created in the semiconductor substrate II with the help of selective diffusion. The selectivity is ensured by a masking material on the surface of the semiconductor substrate 11 in which the diffusion constant of the dopant is some orders of magnitude lower than in the semiconductor substrate 11 itself. As an example of this, in the case of silicon as semiconductor substrate 11 the silicon dioxide created unavoidably during the thechnological process was proved to be excellent masking material. After this selective emitter diffusion follows to produce n-p-n or p-n-p structures in both horizontal and vertical directions then contact windows are opened in the silicon dioxide isolation layer 21 at appropriate places over the diffused 12,13 and collector 20 layers.

Further on the surface is covered with a metallic layer and later this layer is removed from the places where it is not required by selective etching and metallic contacts ensured between the semiconductor layers 12, 13,20 and the 15,17,19 leads at the 14,16,18 contact places by means of alloying.

The operation of a bipolar transistors created in this way assuming that the most general common emitter con figuration is considered can be summed up as follows. Through the forward biased emitter-base junction (the interface between the base 12 and the emitter 13 layers) minority charge carriers are injected into the base layer 12, the amount of which is proportional to the bias voltage, i.e. the base voltage. A small part of these injected carriers is recombined or compensated in the base layer 12 and ensures the base current and the remaining more significant part of the carriers are swept out of base layer 12 to the collector layer 20 by the electric field of the reverse biased colleetor-base junction (the interface between the collector 20 and the base 12 layers).

The electronic parameters of the device are primarily determined by the doping level and the geometric form of the 12,13,20 layers. The common emitter current gain, i.e. the rate of the collector and the base current which is perhaps the most characteristic parameter of bipolar transistors far example, is mainly a function of the base charge integral (i.e. the base impurity level) and the current gain as a function of the collector current is determined primarily by the geometry of the 12,13,20 layers. A bipolar transistor if it is built up with the following parameters: diffusion depth 1-3 μm, base width 0.5 μm, emitter sheet resistance 5-10 Ohm/♢, base sheet resistance 150-300 Ohm/♢, collector resistivity 0.1-1 Ohmcm ensures for example current gain in the range 50-100.

The layout (figure 3) and the cross section (figure 4) of the semiconductor tetrode, i.e. the gate controlled bipolar transistor according to the invention, is to be seen in figures 3 and 4 . Though with different geometry the tetrode similarly to the bipolar transistor contains emitter 13, base 12 and collector 20 layers, moreover these 12, 13, 20 layers are connected to the 15,17,19 leads through the 14,16,18 contact windows opened in the isolation layer 21. (However it should be mentioned that the said tetrode in accordance with the invention can be created not only on the basis of the traditional bipolar transistor but on the basis of any other semiconductor structure which contains at least two appropriately replaced p-n or n-p junctions on the surface.) The said tetrode however contains an extra controlling 22 electrode and a lead 23 for it, moreover the isolation layer 21 over the base layer 12 is used not only to make possible selective technological steps and to protect the surface but also to ensure a capacitive way for the extra controlling electrode 22 to influence the base layer 12 through the electric field and give another controlling capability. Therefore the isolation layer 21 applied here or at least that part of it which lies beneath the extra controlling electrode 22 should satisfy much more severe re quirement than those for bipolar transistors. The thickness of isolation layer 21 for example which is an essentially insignificant parameter with bipolar transistors plays an important role here in determining the value of the electric field and thus in determin ing the slope of the control curve. Uoreover the concentration of the oxide charge and interface states influences the range of control by shifting the effective potential on the controlling electrode 22 and mainly determines the reliability of the device. The control range can be influenced by changing the impurity concentration in the base layer or by varying the material of the controlling electrode 22 through the metal-semiconductor work function difference, too.

The technology used for the creation of the basic structure, i.e. for creation of the emitter 13, base 12 and collector 20 layers as well as for forming contacts and leads, is similar to that used for produc tion of bipolar transistors through the optimal parameters for some of the technological steps can be different from the parameters used for biplar transistors. However, the controlling electrode 22 and the isolation layer 21 beneath it should be made by one of the methods well-known from the technology of MOS devices, for example when silicon substrate is used the isolation layer 21 can be created by dry oxidation followed by thermal treatment and the controlling electrode can be made from aluminium simultaneously with forming the 15,17,19,23 leads.

Operation of the semiconductor tetrode produced in this way can be described as follows. The emitter-base junction is forward biased whereas the collector-base junction is reverse biased as is done in the case of the active regime of bipolar transistors and an injection current flows from the emitter to the collector which can be governed by the base current. However, while the direction of the current flowing is mainly vertical in the case of traditional bipolar Transistors, for the said tetrode the current should flow mainly along the plane of the surface since only this component of the collector current can be controlled by the electric field of the controlling electrode 22, and the vertical comnonent of the collector current does not depend.on the potential of controlling electrode 22 and can be influenced only through the base current, The operation of the controlling electrode 22 is based on the fact that the amount of charge carriers at the semiconductor surface of an MOS capacitance (in our case the controlling electrode 22, the isolation layer 21 and the base layer 12 construct such a structure) which equals the amount of ionized dopants in the ideal case without any bias between the controlling electrode 22 and the semiconductor surface can be altered by the potential given on the controlling electrode 22 and the measure of accumulation, depletion or inversion depends on the impurity concentration near the surface. It means that the base width and the base charge integral near the surface of the base layer 12 can be changed by altering the potential given to the controlling electrode 22 and thus the virtual doping profile of the bipolar transistor and in accordance with it the main electronic parameters (current gain, cutoff frequency, etc) can be altered. Therefore the basic bipolar structure created during the technological process can be altered thereby providing another effective controlling capability and thus a tetrode is made.

The electronic parameters of the basic structure similarly to the bipolar transistors are determined by the impurity concentration and geometry of the 12, 13,20 layers. However in contrast to the bipolar transistors in the case of a tetrode the embodiment and the geometra should be made so that the ratio of the outline and the territory of the emitter region be as high as possible in order to ensure current flow mainly along the semiconductor surface, Further on, regarding choice of the doping profile, it should be taken into account that the slope of the control curve and its range of control besides the material of isolation layer 21 and controlling electrode 22 and the width of isolation layer 21 depend on the dop ing profile at the semiconductor, too.

Figures 5 and 6 respectively show the layout (figure 5) and the cross section (figure 6) of a further embodiment in accordance with the invention. This type of embodiment besides the semiconductor substrate 11, the base layer 12, the emitter layer 13, the collector layer 20, the 14,16,18 contacts, the 15,17, 19,23 leads, the controlling electrode 22 and the isolation layer 21 contains epitaxial layer 24 and base stretching layer 25, too. The epitaxial layer 24 which in this case represent the collector layer 20 and contains in itself the whole base layer 12 ensures an isolation possibility when using the said tetrode in integrated circuits and the addition of a buried layer under the base with a conductivity identical to that of the base (this is not shown in the figures) enables the current component to be decreased which is otherwise uncontrollable by the controlling electrode 22.

The technology for producing this embodiment differs from the previous in that at first an epitaxial layer 24 is created on the surface of the substrate II which in this case need not necessarily semiconductor material and the base and emitter diffusion or implantation is made only after this through one and the same resist window. Then the base stretching layer 25 is formed by diffusion or implantation (note that this layer can be formed before the base and emitter diffusion, too), and the isolation layer 21 is created, the 14,16,18 contact windows are opened and last the controlling electrode 22 and the 15,17, 19,23 leads are made.

Since base and emitter diffusion take place through one and the same resist window, automatic aligning is performed and the production of tetrodes with this base and good ratio of outline to territory can be achieved. Howevex in this case the base contact 14 cannot be replaced as earlier since the base width is too thin thereby necessitating the base stretching layer 25 which, through contact 14 ensures contact between base layer 12 and base lead 15.

Figures 7 and 8 respectively show the layout (figure 7) and the cross section (figure 8 ) of another embodiment.

This embodiment contains besides the semiconductor substrate 11, the base layer 12, the emitter layer, the collector layer 20, the 14,16,18 contacts, the 15,17,19,23 leads, the contcolling 22 electrode, the isolation 21 layer and the epitaxial 24 layer an extra isolation layer 26 in order to ensure isola tion between the controlling 22 electrode, its lead 23 and the emitter, base, collector 15,17,19 leads.

The technology for producing this embodiment differs from the previous technologies in that collector layer 20 is represented by an epitaxial layer 24 which only partly includes the base layer 12, i.e. the base layer 12 is diffused through the epitaxial layer 24 into the semiconductor substrate 11 which has the same type of conduction as does base 12 and thus the base contact 14 can be made on the semi- conductor substrate 11 and the base lead 15 can be connected here. An alternative technology is that the material used for the controlling electrode 22 and its lead 23 differs from the material applied for emitter, base and collector 15,17,19 leads (in the case of silicon it can be for example polysilicon), and thus double layer metallization is ensured and better density of devices can be achieved for inter- rated circuit applications but this double layer metallization requires the use of an extra isolation layer 26.

A further characteristic of the embodiment that the collector current component uncontrollable by the controlling electrode 22 is practically elminated since no n-p-n or p-n-p structure is created beneath the base layer 12. However the above characteristic causes a disadvantage, in that in spite of using epitaxial layer 24 the full isolation of separate tetrodes for integraed circuit applications is impossible since their base layers 12 are connected through the semiconductor substrat 11.

Figure 9 shows a characteristic of the embodiment in connection with the invention. Namely the ratio of collector I_C and base I_B currents, i.e. the common emitter current gain I_C/I_B as the function of the potential on the controlling electrode V_V is shown with the base current as parameter more exactly at I_B1, I_B2 and I_B3 where I_B1, is lower than I_B2 a nd I_B3 higher than I_{B2 .} In this case the bipolar transistor is represented by an n-p-n structure therefore a positive potential given to the controlling electrode V_V causes partly depletion, partly inversion in the surface layer of the base and accordingly a lowered base charge integral and base width which results in a higher current gain I_C/I_B. In contrast to positive potential, the application of negative controlling potential V_V gives an opposite, effect since in this case due to the accumulation of charges at the surface of the base layer the base charge integral and the base width grow and thus the current gain I_C/I_B decreases through obvioulsly this process gives a lower slope of control curve than the previous one. Further, it can be noticed that by increasing the base current I_B the current gain I_C/I_B is lowered, but this is a well-known, phenomenon of the physics of bipolar trasistors and is caused mainly by the lowering of emitter efficiency over some current level. This phenomenon is made even more significant at depletion and less important at accumulation caused by the controlling potential in the base surface layer.

The advantages of the process and embodiment in connection with the invention may be summarized, as follows:

- with the help of it a semiconductor tetrode can be created, - electronic parameters of bipolar transistors can be altered electrically with the help of the invention and thus it is possible to eliminate or at least lower the divergence of parameters caused by the technology, - production of special amplifiers (extra high current gain, small switching time, etc) can be ensured,

- joins the high input resistance of 1-103 devices and the low output resistance and small saturation voltage of bipolar transistors, - the said invention can be produced by a combination of technological steps well-known from serial production of semiconductor devices,

- the said invention can be produced by modifying the bipolar or MOS process and thus serial production can be realized easily and economically.

Claims

What is claimed:

1. Process for producing a semiconductor tetrode, during which double diffusion is made in a semiconduc tor substrate in order to create a n-p-n or p-n-p bipolar transistor structure along the surface, which contains emitter, base and collector, then contact windows are opened in the isolation layer formed during the diffusion or in a separate tech nological step over the emitter, base and collector and leads are made to these layers characterized in that over the base layer an extra electrode is made isolated from that, and a lead is provided to this extra electrode.

2. Process as claimed in claim 1 characterized in that the oxide layer formed over the base is etched away and a new more suitable oxide layer is made.

3. Process as claimed in claim 1 characterized in that the electrode and lead belonging to it is created at the same time from identical material.

4. Process as claimed in claim 1 characterized in that at first the extra electrode is made and the leads are connected only after this.

5. Process as claimed in claim 1 characterized in that the diffusion or implantation is made into an epitaxial layer created on the surface of the semiconductor substrate.

6. Process as claimed in claim 5 characterized in that the diffused or implanted layers are replaced entirely in the epitaxial layer.

7. Process as claimed in claim 5 characterised in that the diffusion or implantation extends over the epitaxial layer.

3. Embodiment of semiconductor tetrode for realization of claims 1-7 which embodiment has emitter, base, collector and isolation layer and leads to them characterized in that it has an extra electrode over the base on the isolation layer. (figure 3 and 4)

9. Embodiment as claimed in claim 8 characterized in that the base lead is made directly to the base layer. (figures 3 and 4)

10. Embodiment as claimed in claim 8 characterized in that the base lead is connected to the base layer through the stretching layer. (figures 5 and 6)

11. Embodiment as claimed in claim 8 characterized in that it has an epitaxial layer, too.

(figures 5 and 6)

12. Embodiment as claimed in claim 11 characterized in that the base lead is replaced on the semiconductor substrate.

(figures 7 and 8)