JPS598068B2 - semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a static induction transistor that operates at low power and high speed, and a semiconductor integrated circuit using the same.

It has a high input impedance, requires almost no drive power, has low power consumption, and is easy to increase density.
Static induction transistors, with their large transducer conductance, high fan-out, and high speed operation, are well suited for integrated circuits.

A static induction transistor integrated circuit (81T) configured in a circuit format equivalent to IIL including an inverted static induction transistor
It's called L. ) has been proposed by the inventor of the present application, for example, in the patent application filed in 1973.
It was proposed in Japanese Patent Application No. 0-146588 and Japanese Patent Application No. 51-92467, and the equivalent circuit of the basic circuit section is shown in FIG. 1a, and an example of its structure is shown in FIG. 1b. 1st
The figure shows the case of one input and two outputs. P* regions 1 and 2 are the emitter and collector of a lateral bipolar transistor that operates as an injector.

P* region 2 is also the gate of the inverted static induction transistor. 3 is the source of the static induction transistor, n
``substrate or n'' buried region.

The n* regions 5, 5' are the drains of the static induction transistors. In the standard process of 4 masks and 2 diffusions as shown in FIG. 1B, a minimum delay time of 4 nsec is obtained in the low current region with a power delay product of 0,002 PJ and a power consumption of 100 PW. IILs that are configured using such standard processes and have a large number of collectors of driver bipolar transistors (hereinafter referred to as BPTs) hardly perform logical operations, and are realized using more complicated structures and processes. The minimum delay time of a static induction transistor integrated circuit using a standard process is VI, which is also a representative of modified IIL.
L (Vertical Injection Logic)
or SSL (Self-AlignedSuperInj
The power delay product is O, 07PJ for VIL, and O, 06 for SSL.
Since it is a PJ, it is less than 1/30. The current transport rate of lateral bipolar transistors can be relatively high, the gate capacitance can be reduced without increasing the gate resistance, and even in an inverted structure where the drain area is larger than the source, the electrostatic induction transistor focuses the carrier flow. This good performance is due to the high conversion conductance and high conversion conductance. The speed limit of conventional static induction transistor integrated circuits was due to the accumulation effect of excess minority carriers injected into the channel from the gate of the static induction transistor operating as an inverter, and the total static electricity expected from the gate of the static induction transistor. It is the capacitance. Static induction transistors are essentially voltage damping devices.

However, in the SITL, when the driving SIT is turned on, the gate is shifted in the forward direction, so minority carriers are inevitably injected from the gate into the channel. The injected carriers have the effect of reducing the resistance of the SIT in the conducting state, increasing the drain current and increasing the operating speed. However, if a large amount of amaz is injected, the accumulation effect of excess minority carriers becomes significant and the speed decreases.
In addition, in the example of FIG. 1 which operates with forward gate bias,
It is particularly important to reduce the capacitance from the gate. The inventor of the present invention has proposed a split gate structure as a structure that reduces the capacitance of the gate without reducing the conversion conductance so much (see, for example, Japanese Patent Application No. 81796/1983).

FIG. 2 is an example of a split gate structure. FIG. 2a shows a diffusion region on an epitaxial substrate in plan view.

2B and 2C are cross-sectional structures taken along line A-A' in FIG. 2A, and FIG. Figure c shows an upright SIT with the substrate or buried region 1 as the drain.
It is. FIG. 2 is an example of an n-channel SIT. Second
In the figure b, n+ region 1 is the source, n-region 2 is the channel, n+ region 3 is the drain, P+ region 4 is the drive gate, P+ region 5 is the fixed potential gate, 3' is the drain electrode,
4' is a gate electrode for driving, 5' is a gate electrode for fixed potential, and 6 is an insulating layer of SlO2, Si3N4, AI12O3, etc. or a combination thereof. In Figure 2c, n+
It is the same as FIG. 2b except that region 1 is the drain, n+ region 3 is the source, and 3' is the source electrode. The characteristic of the static induction transistor shown in Figure 2 is that the gate region surrounding the channel is divided into two parts, one of which is a driving gate for inputting signals, and the other is a floating gate or a gate designed to give a constant potential. That's a good thing.

In the structure shown in FIG. 2, the capacitance of the driving gate that controls the drain current according to the input signal is at least half the capacitance of the entire gate surrounding the channel, and the capacitance Cgs between the driving gate and the source is The reduction in the capacitance C9d between the drains directly improves the frequency characteristics of the static induction transistor, shortens the time required to change the gate potential to a predetermined potential, and allows high-speed operation. Further, the fixed potential gate may be a floating gate, or a required potential may be applied as necessary. Such a static induction transistor having a fixed potential gate can vary the value of the drain current over a wide range even if the signal input to the driving gate and the drain voltage are the same, depending on the potential applied to the gate. For example, if a reverse gate bias is applied to a fixed potential gate, the drain current will become smaller, and if a forward gate bias is applied, the drain current will become larger. Of course, it can also be used as a floating gate with a depletion layer determined by the diffusion voltage between the gate and the channel extending into the channel. FIG. 3 shows an example of a structure in which Cgs and C9d are further made smaller and 9m is made larger than in FIG. 2.

FIG. 3 shows that each region is almost cylindrical or annular, and the fixed potential gate 15 is annular.
It consists of a cylindrical drive gate 14 located at the center, and an annular drain 13 (FIG. 3b) or source 13 (FIG. 3C) narrowed therebetween.

Since the drive gate can be made extremely small compared to the channel, Cgs and C9d are extremely small. At the same time, the area of the channel controlled by the driving gate voltage is wide and 9 m is large. Since C9s and C9d are small and 9m is large, its frequency characteristics are extremely good, the operating speed is fast, and a large number of fan outs can be obtained. Figures 3B and 3c are cross-sectional structures taken along the line A-A' in Figure 3a, where Figure 3b is an inverted type static induction transistor and Figure 3c is an upright type static induction transistor. It is. In the diagram of FIG. 3b, 11 is a source, 12 is a channel, 13 is a drain, 14 is a driving gate, 15 is a fixed potential gate, 13' is a drain electrode, 14' is a driving gate electrode, and 16 is an insulating layer. It is.
In the diagram of FIG. 3c, 13 is the source, 11 is the drain, and 13'
is the drain electrode, and the rest is the same as in FIG. 3Bb. The impurity density of each region is 11 to 1017, respectively.
~10210! IL-3 level, 12 is 1012 to 1
016CffL-3 degree, 13 is 1017 to 1021
About -3, 14 is about 1017 to 1021 '3,
15 is about 1017 to 1021CT1L-3.
The source and drain spacing, channel dimensions, and impurity density are determined by the application. For example, when the fixed potential gate 15 is made into a floating gate and the zero gate bias is applied,
In the case of a cut-off state, that is, a normally-off type, the channel width and impurity density are selected so that the depletion layer crosses and closes the channel with only the diffusion potential between the gate and the channel. It is used in integrated circuits, operates at low drain voltages, for example, on the order of 0.2 to 0.6 V, and is extremely fast. For example, when performing sub-nanosecond operation, 5P
It is sufficient to make it less than m. When using a fixed-potential gate with a reverse bias, it is not necessary to close the channel with the diffusion potential alone, even if the normally-off type operation is used. FIGS. 4a to 4d are plan views showing structural examples of a split gate type static induction transistor, in particular, a static induction transistor having a fixed potential gate provided around the periphery.

FIG. 4 shows an example in which four drains are provided. In the figure, 22 is a high resistance region, 23 is a drain, 24
25 is a driving gate, and 25 is a fixed potential gate. FIG. 5 is a sectional view taken along line A-A' in FIG. 4d.

An example of an n-channel is shown. 21 is a source consisting of a buried region or a substrate.

The impurity density of each region is 21 to 1017, respectively.
About 020cm-3, 22 is 1012 to 1020c!
About n-3, 22 is about 1012 to 10156-3,
23 is about 1017 to 1021CIn-3, 24,2
5 is 1016 to 1021? It is about -3. The fixed potential gate may be a floating electrode or may be operated by applying a predetermined potential. FIG. 6 shows an example of a structure in which the fixed potential gate is set to the same potential as the source. Adjacent to the P+ region 25, an n+ region 26 is provided in a part thereof, and the structure is such that 25 and 26 are connected by an electrode 25' made of metal or the like. 6th
In the figure, 27 is an insulating layer made of SlO2, Si3N4, A22O3, or a composite layer thereof. 23-4′,
24', 23-1', and 25' are electrode metals that are in ohmic contact with the respective regions and are made of Al, MO, or the like.

Of course, low resistance polysilicon may also be used. area 26
is directly connected to the source 21 via the n-region 22, so
The fixed potential gate 25 of the configuration shown in FIG. 6 is kept at the same potential as the source. Split-gate static induction transistors are usually used in a normally off-type mode, in which the channel opens and becomes conductive only when a predetermined forward voltage is applied to the drive gate, so the channel dimensions and impurity density are , when the drive gate is at the same potential as the source,
Select so that the channel can be pinched off and sufficiently cut off.

Although FIGS. 5 and 6 show examples in which the gate regions 24 and 25 reach the source region, the gate regions do not necessarily have to reach the source region.

When the gate region reaches the source, is the diffusion potential between the gate bottom surface and the source region equal to the diffusion potential between the gate region and the channel region? Because it is large, it has the advantage that unnecessary minority carrier injection from the bottom of the gate can be suppressed when the drive gate is moved in the forward direction. In the structure shown in Fig. 4, the part where the drive gate 24 and the fixed potential gate 25 directly oppose each other has a P+n-P+ transistor structure, and a bunch of current flows through the area, which causes a decrease in the impedance of the drive gate and increases speed. may cause a decrease in The n-region where such a punch-through current may flow can be removed by increasing the impurity density of the n-region by ion implantation, diffusion, etc. to such an extent that no punch-through current flows. FIG. 7 shows an example in which the number of drains serving as output terminals is further increased.

FIG. 7 shows an example in which the number of drains is 10. The channels corresponding to the six drains 23-2 to 23-4, 23-7 to 23-9 in FIG.
The characteristics caused by the split gate are not as pronounced as in the example shown in FIG. Also, although fixed potential gates are normally set to the same potential as the source, they are often set to reverse gate bias.
The six channels and 23-1, 23-5, 23-
6, 23-10, the dimensions of the channels must be changed so that the current levels are the same. Usually, the size of the latter channel is made larger than the former.
An example of a multi-channel structure that eliminates these drawbacks is shown in FIG. 7b. The drive gate 24 is formed in one region, and the area is reduced compared to that in FIG. 7a, and naturally the capacitance is also reduced. Since each channel is surrounded by fixed potential gates on all three sides, with only one side facing the drive gate, the area of each channel can be nearly the same if the same current level is obtained. Of course, if the current at the output terminal of each channel is different, the channel area may be changed accordingly. An object of the present invention is to provide an integrated circuit using a static induction transistor having a fixed potential gate around it and a drive gate inside.

The static induction transistor (hereinafter referred to as SIT) shown in FIG. 4 has a fixed potential gate around it, a drive gate inside, and a plurality of drains serving as output terminals.

) is constructed in a 12L type electrostatic induction transistor integrated circuit as shown in FIG. 4d, and one unit is shown in FIG. Figure 8 shows I2L type S in the case of 1 input and 4 outputs.
One unit of ITL is shown.

Examples of cross-sectional structures along lines A-A', B-B', and C-C' in FIG. 8 are shown in FIGS. 9, 10, and 11.
, b. EE is the power supply voltage, In is the input voltage, Vou
l is the output voltage. In FIGS. 8 to 11, the injector is a PnP bipolar transistor (hereinafter referred to as BPT), and the driver is an n-channel divided gate SIT. As is clear from Figures 9 to 11, the injector BPT
is provided on the surface of the drive gate. That is, P+(
29)-n(28)-P+(24) is injector BP
T's emitsuta, b. has become a collector. As in the case of FIG. 4, the substrate or buried region 21 is the source of the SIT. Region 31 is SiO
This is the second insulator region. In the n' region 31, no punch-through current flows between the drive gate and the fixed potential gate. This is a region in which the impurity density is made as high as n-region 22 in order to reduce the impurity density. Of course, this is not necessarily necessary since it is sufficient that even a punch-through current does not flow. 9th to 1st
The structure shown in FIG. 1q can be easily constructed by selective epitaxial growth, selective diffusion, ion implantation, etc., and the structures shown in FIGS. 9 to 11 b can be easily constructed by selective diffusion, ion implantation, etc. As shown in the structural examples of FIGS. 8 to 11, the SITL in which the injector BPT is provided above the drive gate can have an extremely high degree of integration without requiring a large area for the injector, and moreover, the injector BPT is The current transport rate is almost 1 and the current V
Almost all the current supplied from EE can be used effectively,
Effective for speeding up and reducing energy consumption. Additionally, the surrounding fixed potential gate controls the potential of the channel and at the same time
Since it also serves as an isolation region for each SITL unit, a large number of units can be provided directly adjacent to each other, making the increase in the degree of integration even more remarkable. I2L type SITL can configure NOR, OR gates, etc. with wired logic, and all functions can be configured with wired logic, so the 8th
By providing each SITL unit as shown in Figures 1 to 11 with the necessary output terminals, the desired function can be achieved using only the electrode wiring on the surface, resulting in an extremely highly integrated circuit. The dimensions and impurity density of each region of the divided gate SIT are as described above. The impurity density of the regions 28 and 29 constituting the injector BPT is 101
It is about 6 to 1118 C-3, and about 1017 to 1021 C-3. When the driver SIT is turned on, the drive gate is forward biased.

In the examples shown in FIGS. 8 to 11, it is, for example, approximately +0.4 to 0.7. In particular, as the forward bias becomes deeper and more minority carriers (holes in the case of FIGS. 8 to 11) are injected into the channel, the accumulation effect becomes noticeable, which causes a reduction in speed. However, in the SITL of the present invention, the fixed potential gate is kept at the same potential as the source (52, 12,
20), or when properly reverse biased, the fixed potential gate also serves as a sink electrode for the minority carriers injected into the channel at the same time, causing almost no accumulation effect. , making high-speed operation even more remarkable. Although FIGS. 8 to 11 show examples in which the injector is constructed from BPTs, FIG. 12 shows an example in which the injectors are constructed from field effect transistors (FETs). Figure 12 shows
This corresponds to a sectional view taken along line A-A7 in FIG. The P+ regions 32 are the source and channel of an FET which is an injector, respectively. The injector is the 12th FET.
When configured with J-FETs as shown in the figure, a larger current can flow with the same injector area, and the speedup becomes even more remarkable. In FIG. 12, the drain 23 of the SIT, the drain 33 of the injector FET, and the channel 32 are shown separated, but of course they may be in direct contact.

The drain 23 and channel 22 serve as the gate of the injector FET. As mentioned above, all functions can be assembled using wired logic. It is also a common belief mentioned above that the fixed potential gate serves as channel control, separation region, and minority carrier extraction electrode. 8 to 12, the 4-output dividing gate S in FIG. 4d
The case of IT is shown. Of course, the structure is the fourth
It may have a structure other than that shown in the figure, or may have a large number of output terminals as shown in FIG. 7, or may have one output terminal as shown in FIG. Third
As shown in the figure, in the case where the channel is annular and the driving gate is circular, the capacitance of the driving gate is particularly small, the conversion conductance is large (9 m), and the driving ability of the next stage is large and high speed is achieved. Further, although FIG. 9 shows an example in which the area of the injector BPT is the same as that of the drive gate, it goes without saying that it may be smaller. So far, I have talked about SIT, but the exact same thing can be said about junction FET.
It can also be applied to

If the channel width is made sufficiently narrow, normally-off operation will be performed, and the structure of the present invention can be applied as is. Of course, the SITL of the present invention is not limited to that shown in FIGS. 8 to 12.

Of course, the conductivity type may be reversed. The channels are not limited to circular or rectangular shapes, but may have any elliptical shape, and the multiple channels are simultaneously controlled by fixed potential gates surrounding the multiple channels and drive gates whose potentials are changed by signals inside. It is sufficient that the structure is such that a plurality of outputs, that is, fan-out can be obtained, and a transistor serving as an injector is provided on the drive gate. Although an example has been shown in which both the fixed potential gate and the drive gate are in direct contact with the source region, it goes without saying that they may be separated from each other. Although channels with uniform impurity density are shown here, they may also have a multilayer structure with different impurity densities. Although the n+ and P+ regions on the surface are separated, they may be in direct contact. Furthermore, although a structure in which all gates are flat has been shown, it goes without saying that a structure in which gates are provided along the sides of the cut region may also be used. The gate provided on the side of the notch area is a junction type,
It may be a shotgun type, MOS, or MIS type.
The structure of the present invention can be manufactured by conventionally known crystal growth techniques, microfabrication techniques, selective diffusion techniques, selective etching (dry, chemical), ion folding techniques, and the like.

A fixed potential gate surrounding a plurality of channels and a drive gate were provided inside, and an injector was provided above the drive gate.

In the SIT integrated circuit of the present invention, the capacitance of the driving gate is small, the current transport rate of the injector transistor is large, and the fixed potential gate acts as a minority carrier extraction electrode, so that there is almost no minority carrier accumulation effect. It can operate at extremely high speeds, has a large number of fan-outs, and has an extremely high degree of integration, so its industrial value is high.

[Brief explanation of the drawing]

Figure 1 A, b, Figure 2 a to c, Figure 3 a to c, Figure 4
Figures a to d, Figures 5, 6, and 7 A and b are examples of conventional structures, and Figure 8 a is an example of the present invention, which is a plan view of an I2L type static induction transistor integrated circuit. , FIG. 8b shows I
Equivalent circuit of 2L type static induction transistor integrated circuit, No. 9
Figures A and b are examples of cross-sectional structures taken along line A-A' in Figure 8a, Figures 10A and b are examples of cross-sectional structures taken along line A-B-B' in Figure 8a, and Figure 11A. , b is an example of a cross-sectional structure taken along line C-C' in FIG.

Claims (1)

[Claims] 1. A source and a drain made of high impurity density regions of the same conductivity type, a fixed potential gate surrounding a channel made of a high resistance region of the same conductivity type as the high impurity density region, and a fixed potential gate of the fixed potential gate. 1. A semiconductor integrated circuit comprising at least one unit in which an injector transistor is provided on at least a portion of the drive gate of a split-gate static induction transistor having a drive gate for controlling the channel. 2. The semiconductor integrated circuit according to claim 1, further comprising at least one unit in which the injector transistor is a bipolar transistor and the drive gate is a collector of the bipolar transistor. 3. The semiconductor integrated circuit according to claim 1, characterized in that at least a part of the unit includes a unit in which the injector transistor is a field effect transistor and the drive gate is the drain of the field effect transistor.