JPS6248910B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a static induction transistor that operates at low power and high speed, and a semiconductor integrated circuit using the same.

Hereinafter, in this specification, both individual semiconductor elements and semiconductor integrated circuit devices will be referred to as a semiconductor device.

Static induction with high input impedance, requiring almost no drive power, low power consumption, easy to increase density, large conversion conductance, large number of fan outs, and high speed operation. Transistors are well suited for integrated circuits. IIL including an inverted static induction transistor
A static induction transistor integrated circuit (referred to as SITL) configured in a corresponding circuit form has been disclosed by the inventor of the present application, for example, in Japanese Patent No. 1181984 (Japanese Patent Publication No. 58-11102).
No.) ``Semiconductor integrated circuit'' and Patent No. 1208034 (Special Publication No. 1983-38938) ``Semiconductor integrated circuit'', and the equivalent circuit of the basic circuit part is shown as shown in Figure 1a, an example of its structure. are as shown in Fig. 1b and c. Figure 1 shows the case of one input and two outputs. FIG. 1b is a plan view, and FIG. 1c is a sectional view.

The emitter of a lateral bipolar transistor in which p ⁺ regions 1 and 2 act as injectors,
is a collector. The p ⁺ region 2 is also the gate of the inverted static induction transistor. 3 is the source of the static induction transistor, which is the n ⁺ substrate. n ⁺
Regions 5 and 5' are the drains of the static induction transistors. With the standard process of 4 masks and 2 diffusions as shown in Figure 1b, the minimum delay time is 0.002PJ in the low current region and the power consumption is 100μW.
4nsec is obtained. A multi-output IIL with many collectors of driver bipolar transistors (hereinafter referred to as BJTs) configured using such a standard process hardly performs logical operations.
Multi-output IIL is realized through more complex structures and processes. The minimum delay time of an integrated circuit of static induction transistors by standard process is modified IIL
VIL (Vertical Injection Logic), which is also a representative of
and SSL (Self-Aligned Super Injection Logic)
, and the power delay product is VIL.
Since it is 0.07PJ and 0.06PJ for SSL, it is less than 1/30. The current transport rate of the lateral bipolar transistor can be relatively high, the gate capacitance can be reduced without increasing the gate resistance, and even in an inverted structure where the drain area is larger than the source, the static induction transistor has the following advantages: This good performance is due to the fact that it has a focusing effect and a large conversion conductance. The speed limit of conventional static induction transistor integrated circuits was due to the accumulation effect of excess minority carriers injected into the channel from the gate of the static induction transistor operated by the inverter, and the calculation expected from the gate of the static induction transistor. Total capacitance.

Static induction transistors are essentially voltage-controlled devices. However, in SITL, for driving
When SIT is made conductive, the gate is transferred in the forward direction, so minority carriers are inevitably injected from the gate into the channel. The injected carrier has the effect of reducing the resistance of the conducting SIT, increasing the drain current and increasing the operating speed. However, if too large a quantity is injected, the accumulation effect of excess minority carriers becomes significant and the speed decreases. In addition, the first gate operates with a forward gate bias.
In the illustrated example, it is particularly important to reduce the capacitance from the gate.

The present inventor has proposed a split gate structure as a structure that reduces the capacitance of the gate without reducing the conversion conductance so much (for example, Japanese Patent No. 1302727 (Japanese Patent Publication No. 1302727)).
60-20910) "Static induction transistor and semiconductor integrated circuit", Patent No. 1236163 (Special Publication No. 1982-12017)
No.) "Semiconductor integrated circuit", Patent No. 1247054 (Special Publication No. 59-21176) "Static induction transistor semiconductor integrated circuit", Patent No. 1231827 (Special Publication No. 59-8068)
"Semiconductor integrated circuit").

FIG. 2 is an example of a split gate structure.

FIG. 2a shows a diffusion region on a semiconductor substrate in a plan view. Figures 2b and c are A- in Figure 2a.
The cross-sectional structure taken along line A' is shown in Fig. 2b, an inverted SIT with the substrate or buried region 11 as the source region, and Fig. 2c shows an upright SIT with the substrate or buried region 11 as the drain. It is.
FIG. 2 is an example of n-channel SIT. Figure 2b
In the figure, n ⁺ region 11 is the source, n ^- region 12 is the channel, n ⁺ region 13 is the drain, and p ⁺ region 14
is a driving gate, p ⁺ region 15 is a fixed potential gate,
13' is a drain electrode, 14' is a drive gate electrode, 15' is a fixed potential gate electrode, and 16 is a gate electrode for fixed potential.
It is an insulating layer made of Sio ₂ , Si ₃ N ₄ , Al ₂ O ₃ or a combination of these. 2c is the same as FIG. 2b except that n ⁺ region 11 is the drain, n ⁺ region 13 is the source, and 13' is the source electrode.

The characteristic of the static induction transistor shown in Figure 2 is that the gate region surrounding the channel is divided into two.
One is a drive gate that inputs a signal, and the other is a floating gate or a gate designed to provide a constant potential. In the structure shown in Figure 2, the capacitance of the driving gate that controls the drain current according to the input signal is at least half the capacitance of the entire gate surrounding the channel, and the capacitance Cgs between the driving gate and the source and the drain capacity between
A reduction in Cgd directly improves the frequency characteristics of the electrostatic induction transistor, shortens the time required to change the gate potential to a predetermined potential, and enables high-speed operation. Also, the fixed potential gate is
A floating gate may be used, or a required potential may be applied as necessary. Such a static induction transistor having a fixed potential gate can vary the value of the drain current over a wide range even if the signal input to the driving gate and the drain voltage are the same, depending on the potential applied to the gate. for example,
If a reverse gate bias is applied to a fixed potential gate, the drain current will become smaller, and if a forward gate bias is applied, the drain current will become larger. Of course, it can also be used as a floating gate with a depletion layer determined by the diffusion voltage between the gate and the channel extending into the channel. Furthermore, if the fixed potential gate is directly connected to the source through an electrode or an appropriate bias is applied, the minority carriers injected into the channel can be sucked out, thereby eliminating the accumulation effect of excessive minority carriers.

Split-gate SITs are suitable for extremely high-speed operation because they have a small drive gate capacitance, no minority carrier accumulation effect, and a large conversion conductance. However, it has the disadvantage that punching-through current tends to flow between the driving gate and the fixed potential gate, which face each other without intervening the source or drain, resulting in unnecessary gate current and easily reducing the current gain of SIT. .

An object of the present invention is to provide a static induction transistor that eliminates the above-mentioned drawbacks, maintains a high current gain, and operates at high speed, and a high-density semiconductor integrated circuit that operates at high speed.

The present invention will be explained in detail below using the drawings.

FIG. 3 is a plan view of a structural example of the split gate type SIT of the present invention, in which a splitting insulator is introduced into the portion where the drive gate and the fixed potential gate directly oppose each other. n
In the case of channel SIT, 24 and 25 are a drive gate p ⁺ region and a fixed potential gate p ⁺ region, respectively, and 23-1, 23-2, 23-3, and 23-4 are n ⁺ drain regions, respectively. 26 is an isolation insulator region. This is an example of a fan-out, that is, a case where the number of output terminals is 4. Although only a top view is shown in FIG. 3, the substrate or buried n ⁺ region acts as a source.

Another structural example of the present invention in which the channel is rectangular is shown in FIG. Figure 4a is a plan view, Figure 4b is a plan view.
FIG. 4c is a cross-sectional view taken along line AA', and FIG. 4c is a cross-sectional view taken along line BB'. The n ⁺ region 21 is a substrate or a buried region, the source region, and the n ^- region 22 is a channel. Other areas are the same as in FIG. An insulating layer 26 is provided in a portion where the drive gate and the fixed potential gate face each other without intervening the drain region. When the SIT is normally off, i.e. when the drive gate potential is at the same potential as the source, the channel is pinched off and a high potential barrier is created in the channel, causing a blocking state, especially when the drive gate and fixed Since punching-through current tends to flow between potential gates, isolation using an insulator is extremely effective in reducing unnecessary gate current. When the drive gate is kept at the same potential as the source, the SIT is in a cutoff state, and a forward voltage (in this example, a positive voltage, for example, about +0.4 to +0.8V) is applied to the drive gate. Then, when the potential barrier lowers or disappears and the channel opens, the holes injected from the gate make the channel a positive potential, promoting the injection of electrons from the source and turning it into a conductive state. As shown in FIG. 4d, if the n ⁺ region 27 is provided and directly connected to the fixed potential gate by an electrode, the fixed potential gate will have almost the same potential as the source region 21, so the holes injected into the channel will be Suction out,
Prevents hole accumulation. That is, very high speed switching is performed.

FIG. 5 shows an example in which the present invention is applied to an I ² L type SITIC. FIG. 5 shows an example of a structure in which the substrate is used as one main electrode of an injector transistor. This is an example in which two basic circuits of I ² L type SITIC with fanout 4 are combined in succession. Of course, it is not limited to two. Figure 5a is a plan view, Figure 5b is a plan view.
FIG. 5c is a cross-sectional view taken along line DD', and FIG. 5c is a cross-sectional view taken along line EE'. Similar to Figures 3 and 4, n ⁺ regions 21 and 2
3, n ^- region 22, p ⁺ region 24, 25, respectively
These are the SIT source, drain, channel, drive gate, and fixed potential gate. Fixed potential gate 25
In this case, it also serves as a separation between adjacent I ² L type SIT logics. In Figure 5, area 30 is
n ⁺ region, directly connected to the fixed potential gate,
It plays the role of keeping the potential of the fixed potential gate almost at the same potential as the source and sucking out minority carriers. The p ⁺ region 32, p region 33, and p ⁺ region 24 serve as the source, channel, and drain of a p channel FET that operates as an injector transistor. The p ⁺ region 24 serves as the drive gate of the SIT as well as the drain of the injector FET. The n ⁺ region 21 is the source region of the SIT and also the gate region of the injector FET. The equivalent circuit of the basic circuit portion is shown in FIG. 5d. Vss (+) is the power supply voltage, which is selected to be approximately +0.4 to 0.9V in an example using Si. Vss(+) is
It is applied to the p ⁺ region 32 via an electrode. Vin,
Vout indicates logic level input and output, respectively. The n ⁺ region 21, which is the source of SIT, is
Grounded via electrode.

The insulator region 26 serves to suppress punch-through current between the drive gate 24 and the fixed potential gate, which face each other. The region 26 is made of SiO ₂ ,
Examples include Si ₃ N ₄ , Al ₂ O ₃ or a combination thereof, or a resin-based insulator made of polyimide or the like. In any case, any insulating material may be used as long as it matches well with the base material crystal and can be microfabricated. In the device of the present invention in which the substrate is used as one main electrode of the injector transistor shown in FIG. 5, the fixed potential gate suppresses minority carrier accumulation and at the same time serves as an isolation region between each unit.
The degree of integration becomes extremely high.

FIG. 5 shows only one example of the I ² L type SIT logic, and the structure of the present invention in which the mutually opposing drive gates and fixed potential gates are separated by an insulator is based on the invention of the present inventor (for example, the patent No. 1302727
No. (Special Publication No. 60-20910) "Static Induction Transistor and Semiconductor Integrated Circuit", Patent No. 1236163 (Special Publication No.
59-12017) "Semiconductor integrated circuit", Patent No. 1247054
Needless to say, the present invention can be applied to any structure such as ``Static Induction Transistor Semiconductor Integrated Circuit'' (Japanese Patent Publication No. 59-21176). Since the I ² L type SIT logic allows wired logic, it is possible to construct all desired logic gates by creating a large number of basic circuits and using wired logic. Of course, the conductivity types shown in FIGS. 3, 4, and 5 may be reversed. An example is shown in which the p ⁺ regions 24 and 25 have the same depth as the n ^- region, but of course they may be deeper. Although an example has been shown in which the injector transistor is provided entirely below the P ⁺ region 24, it is of course possible that this is not the case.

The isolation insulator region of the present invention may be manufactured by etching and cutting a predetermined location and then oxidizing it or depositing an insulator by sputtering, vapor deposition, or CVD. Of course, a plurality of these can also be used. Alternatively, predetermined portions may be changed to porous silicon by anodization and then oxidized.

The split-gate semiconductor device (individual semiconductor elements and integrated circuits are collectively referred to as a semiconductor device) of the present invention has a small driving gate capacitance, no unnecessary current flows through the gate, and a large conversion conductance. In addition, there is almost no minority carrier accumulation effect, allowing high-speed operation, and since the fixed potential gate simultaneously serves as an isolation region, a high degree of integration can be achieved, and its industrial value is extremely high.

[Brief explanation of the drawing]

FIGS. 1a to 1c show an example of a structure of an I ² L type SIT logic, FIGS. 2a to 2c show an example of a structure of a split gate SIT, and FIG. 3 shows a split gate of an embodiment of the present invention
One structural example of the SIT, FIGS. 4a to d are other structural examples of the split gate SIT according to an embodiment of the present invention, and FIGS. 5 a to d are still other structural examples of the split gate SIT according to an embodiment of the present invention. FIG. 2 is a structural example and an equivalent circuit diagram.

Claims (1)

[Scope of Claims] 1. In a vertical static induction transistor including a source region, a gate region, and a drain region, the gate region is divided into a plurality of parts, and at least a portion of the gate region is divided between the divided gate region parts. 1. A split gate type semiconductor device, wherein an insulator region is disposed in the region to prevent punching-through current from flowing between the regions. 2. The split gate vertical static induction transistor according to claim 1, wherein the depth of the insulator region is greater than the depth of the opposing portions of the divided gate region portions. Split gate semiconductor device. 3. In the split-gate vertical static induction transistor according to claim 1 or 2, the insulator region is an oxide of a semiconductor material forming at least one of the source, gate, and drain regions. A split gate semiconductor device comprising: 4. In the split-gate vertical static induction transistor according to any one of claims 1 to 3, the semiconductor device has a substrate or a buried region, and the insulator region is a surface A semiconductor device, characterized in that the semiconductor device extends from the substrate to the substrate or the buried region.