JPH0451066B2 - - Google Patents
Info
- Publication number
- JPH0451066B2 JPH0451066B2 JP58039934A JP3993483A JPH0451066B2 JP H0451066 B2 JPH0451066 B2 JP H0451066B2 JP 58039934 A JP58039934 A JP 58039934A JP 3993483 A JP3993483 A JP 3993483A JP H0451066 B2 JPH0451066 B2 JP H0451066B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- conductivity type
- semiconductor layer
- impurity density
- high impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 31
- 239000012535 impurity Substances 0.000 claims description 20
- 230000006698 induction Effects 0.000 claims description 14
- 230000003068 static effect Effects 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 10
- 230000007423 decrease Effects 0.000 claims 1
- 238000000034 method Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 238000004080 punching Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- -1 Si 3 N 4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/098—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being PN junction gate field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】
本発明は、静電誘導トランジスタ及びベースが
完全に空乏層で覆われ殆んどパンチスルーしかか
つているバイポーラトランジスタを有する低電
力、高速度で動作する半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit operating at low power and high speed having a static induction transistor and a bipolar transistor whose base is completely covered with a depletion layer and has almost no punch-through.
高入力インピーダンスであつて次段との直結が
行え、駆動電力を殆ど必要とせず、消費電力が少
なく、しかも高密度化が容易で、不飽和型電流・
電圧特性を示して変換コンダクタンスが大きく、
フアン・アウト数が多くとれ、高速度で動作する
静電誘導トランジスタは、集積回路に極めて適し
ている。倒立型静電誘導トランジスタを含むIIL
相当の回路形式に構成された静電誘導トランジス
タ集積回路は、本願発明者より、例えば特許第
1181984号（特公昭58−11102号）及び特許第
1208034号（特公昭58−38938号）において提案さ
れている。マスク４枚、拡散２回の標準プロセス
で、低電流領域では0.002pJの電力遅延積及び消
費電力100μWで最小遅延時間4nsecが得られてい
る。こうした標準プロセスによる構成ではIILは
殆ど論理動作をまともには行わず、より複雑な構
造、プロセスにより実現されている。標準プロセ
スによる静電誘導トランジスタの集積回路の最小
遅延時間は、これらの代表でもあるVIL
（Vertical Injection Logic）やSSL（Self−
Aligned Super Injection Logic）を越える値を
与えており、電力遅延積ではVILで0.07pJ、SSL
で0.06dpJであることから、1/30以下になつてい
る。ラテラル・バイポーラトランジスタの電流輸
送率が比較的大きくできること、ゲート抵抗を増
加させずにゲート容量を小さくできること、ソー
スよりドレインの面積の大きい倒立型構造におい
ても、静電誘導トランジスタ（以後SITと称す）
はキヤリア流を集束する効果を備えていて変換コ
ンダクタンスが大きいことなどが、こうした良好
な性能の原因である。SITはI2L型の回路形式に
組まれるだけでなく、他の殆どすべての従来型の
回路形式に組むことができる。 It has a high input impedance and can be directly connected to the next stage, requires almost no drive power, has low power consumption, and can be easily increased in density.
It shows voltage characteristics and has large conversion conductance.
Static induction transistors with high fan-out numbers and high speed operation are well suited for integrated circuits. IIL including an inverted static induction transistor
A static induction transistor integrated circuit configured in a corresponding circuit format has been disclosed by the inventor of the present application, for example, in patent no.
No. 1181984 (Special Publication No. 58-11102) and Patent No.
It was proposed in No. 1208034 (Special Publication No. 58-38938). In the standard process of 4 masks and 2 diffusions, a power delay product of 0.002 pJ and a minimum delay time of 4 nsec with power consumption of 100 μW are obtained in the low current region. With a configuration based on these standard processes, IIL hardly performs logical operations, and is realized using more complex structures and processes. The minimum delay time of a static induction transistor integrated circuit using a standard process is VIL, which is also a representative of these.
(Vertical Injection Logic) and SSL (Self-
The power delay product is 0.07pJ for VIL and 0.07pJ for SSL.
Since it is 0.06dpJ, it is less than 1/30. The current transport rate of the lateral bipolar transistor can be relatively high, the gate capacitance can be reduced without increasing the gate resistance, and even in an inverted structure where the drain area is larger than the source, the static induction transistor (hereinafter referred to as SIT) can be used.
This good performance is due to the fact that it has the effect of focusing the carrier flow and has a large conversion conductance. SIT can be implemented not only in the I 2 L circuit format, but also in almost any other conventional circuit format.
また、ベースが完全に空乏化し殆どパンチスル
ーしかかつたバイポーラトランジスタ（以後パン
チングスルーBPTと称す）は、殆どSITと同様
の動作を行うことは、特許第1060320号（特公昭
55−50420号）「半導体集積回路」に詳述されてい
る。 Furthermore, it is known that a bipolar transistor whose base is completely depleted and almost punch-through (hereinafter referred to as punch-through BPT) operates almost the same as SIT.
55-50420) "Semiconductor integrated circuits".
本発明の目的は、ゲート同士の間隔や不純物密
度分布を調節してノルマリオフ型動作及びノルマ
リオン型動作をするようにSIT及びパンチングス
ルーBPTを組み合せるかあるいは印加電圧の極
性によつて異なる動作するようになしたSITもし
くはパンチングスルーBPTを、同一基板上に構
成し、なおかつ前記ノルマリオフ型トランジスタ
のドレイン領域と、前記ノルマリオン型トランジ
スタのソース領域を前記基板内部に作られた埋め
込み領域を用いることにより共通となし、高集積
化を計つた半導体集積回路を提供することであ
る。 It is an object of the present invention to combine SIT and punching-through BPT to perform normally-off type operation and normally-on type operation by adjusting the spacing between gates and impurity density distribution, or to operate differently depending on the polarity of the applied voltage. By configuring the SIT or punching-through BPT as described above on the same substrate, and using a buried region made inside the substrate for the drain region of the normally-off transistor and the source region of the normally-on transistor. The objective is to provide semiconductor integrated circuits that are common and highly integrated.
以下図面を用いて本発明を詳細に説明する。 The present invention will be explained in detail below using the drawings.
第１図は、ノルマリオフ型ｎチヤンネルSITと
ノルマリオン型ｎチヤンネルSITを組み合せた論
理回路構成例である。ａ、ｂ、ｃはそれぞれ、イ
ンバータ回路、２入力のNOR回路、２入力の
NAND回路である。第１図でゲート・ソースが
直結されたSITがノルマリオン型SITであり、入
力Ａ、Ｂの入るSITはノルマリオフ型動作になつ
ている。VDは電源でこの場合は正電圧になつて
いる。第１図ａ、ｂでは、入力信号が低レベルに
ある間は、出力端子は殆ど電源電圧になつている
が、入力信号が高レベルにかわると出力端子電圧
は所定の値まで低下する。第１図ｃでは、Ａ、Ｂ
いずれも高レベルになつたときだけ出力端子電圧
は低レベルにかわる。 FIG. 1 is an example of a logic circuit configuration that combines a normally-off type n-channel SIT and a normally-on type n-channel SIT. a, b, and c are an inverter circuit, a 2-input NOR circuit, and a 2-input NOR circuit, respectively.
It is a NAND circuit. The SIT in which the gate and source are directly connected in FIG. 1 is a normally-on type SIT, and the SIT to which inputs A and B enter is in normally-off type operation. V D is the power supply, which in this case is a positive voltage. In FIGS. 1a and 1b, while the input signal is at a low level, the output terminal is almost at the power supply voltage, but when the input signal changes to a high level, the output terminal voltage drops to a predetermined value. In Figure 1c, A, B
In either case, the output terminal voltage changes to a low level only when it becomes a high level.
例えば、第１図ａのインバータを実現する構造
例を第２図ａ、ｂに示す。 For example, structural examples for realizing the inverter shown in FIG. 1a are shown in FIGS. 2a and 2b.
第２図でｐ基板７の埋め込み層として設けられ
たn+領域１は、ノルマリオフ型SIT（以後Ｆ−
SITと称す）のドレインであり同時にノルマリオ
ン型SIT（Ｎ−SITと称す）のソースになつてい
る。n-領域２はチヤンネル、n+領域３，５はそ
れぞれＦ−SITのソース、Ｎ−SITのドレイン、
p+領域４，６はＦ−SIT、Ｎ−SITのゲート領域
である。１′，３′，４′，５′はそれぞれの領域の
電極である。８は、SiO2、Si3N4、Al2O3等の絶
縁層、もしくはこれらを複数個組み合せた複合絶
縁層である。第２図ａは、Ｆ−SITのゲート間隔
は狭く、Ｎ−SITのゲート間隔が広い場合の例で
ある。Ｆ−SITのゲート間隔は狭いからチヤンネ
ルは拡散電位だけでゲートから延びる空乏層によ
つて覆われており、チヤンネル中に高い電圧障壁
が生じていて遮断状態にある。Ｎ−SITのゲート
間隔は広く、拡散電位だけではチヤンネルは空乏
層では覆われず、導通状態にある。第２図ｂは、
Ｆ−SIT、Ｎ−SITが同一の構造をしている例で
ある。ゲートのp+領域が例えば拡散などの方法
によつて作られると、第３図のように、表面のゲ
ート間隔がもつとも狭くなるような構造になる。
こういう構造のSITは、ソース・ドレインをどち
らの電極にとるかによつて、Ｎ−SITにもＦ−
SITにもなり得るのである。n+領域３をソースに
したSITはＦ−SITになり、n+領域５をドレイン
にしたSITはＮ−SITとなる。従つて、第１図ａ
と同様にＦ−SIT、Ｎ−SITの直列接続によるイ
ンバータ回路となる。 In FIG. 2, the n + region 1 provided as a buried layer of the p-substrate 7 is a normal-off type SIT (hereinafter F-
It is the drain of the normal-ion type SIT (referred to as N-SIT) and the source of the normal-ion type SIT (referred to as N-SIT). n - region 2 is a channel, n + regions 3 and 5 are respectively the source of F-SIT and the drain of N-SIT,
The p + regions 4 and 6 are gate regions of F-SIT and N-SIT. 1', 3', 4', and 5' are electrodes of the respective regions. 8 is an insulating layer made of SiO 2 , Si 3 N 4 , Al 2 O 3 or the like, or a composite insulating layer made by combining a plurality of these. FIG. 2a shows an example in which the F-SIT gate interval is narrow and the N-SIT gate interval is wide. Since the gate spacing of F-SIT is narrow, the channel is covered by a depletion layer extending from the gate with only diffusion potential, creating a high voltage barrier in the channel and blocking it. The gate spacing of N-SIT is wide, and the channel is not covered with a depletion layer by the diffusion potential alone, and is in a conductive state. Figure 2b is
This is an example in which F-SIT and N-SIT have the same structure. When the p + region of the gate is formed by a method such as diffusion, a structure is created in which the gate spacing on the surface becomes narrower as time goes on, as shown in FIG. 3.
A SIT with this structure can be N-SIT or F-SIT depending on which electrode is used for the source and drain.
It can also become a SIT. SIT with n + region 3 as the source becomes F-SIT, and SIT with n + region 5 as drain becomes N-SIT. Therefore, Figure 1a
Similarly, an inverter circuit is formed by connecting F-SIT and N-SIT in series.
第３図は、第２図と同様の動作をパンチングス
ルーBPTを用いて行つた場合の断面構造例であ
る。第３図は、チヤンネル領域がp-領域に変わ
つたことを除けば第２図ａと全く同様である。
n+領域１３，１５はそれぞれＦ−パンチングス
ルーBPTのエミツタ、Ｎ−パンチングスルー
BPTのコレクタである。n+領域１１はＦ−パン
チングスルーBPTのコレクタであり、Ｎ−パン
チングスルーBPTのエミツタである。p+領域１
４，１６はそれぞれのベースである。Ｆ−パンチ
ングスルーBPTはチヤンネルが狭く未だ電圧障
壁が残つていて遮断状態であるが、Ｎ−パンチン
グスルーBPTはチヤンネルが広く完全にパンチ
ングスルーして導通状態になつている。 FIG. 3 is an example of a cross-sectional structure when the same operation as in FIG. 2 is performed using punching-through BPT. FIG. 3 is exactly the same as FIG. 2a except that the channel region has been changed to a p - region.
n + regions 13 and 15 are emitters of F-punching through BPT and N-punching through, respectively.
It is a collector of BPT. The n + region 11 is the collector of the F-punching-through BPT and the emitter of the N-punching-through BPT. p + area 1
4 and 16 are their respective bases. The F-punching through BPT has a narrow channel and a voltage barrier still remains and is in a cut-off state, but the N-punching through BPT has a wide channel and is completely punched through and is in a conductive state.
本発明の構造は、もちろんこれらに限るわけで
はない。導電型を全く反転したものでもよいし、
ゲートやベースを切り込み領域の側面に設けても
よい。また、ゲートも接合型に限らず、MOS、
MIS、シヨツトキーでもよい。ここで述べた回路
構構成をいれば、すべての論理回路は構成でき
る。 Of course, the structure of the present invention is not limited to these. The conductivity type may be completely reversed, or
A gate or base may be provided on the side of the cut region. In addition, gates are not limited to junction types; MOS,
MIS or short keys may be used. All logic circuits can be constructed using the circuit configuration described here.
本発明のゲート間隔や不純物密度分布を調節し
て、ノルマリオフとノルマリオン型動作にした
り、印加電圧の極性によつて異なる動作をする
SITやパンチングスルーBPTを同一基板上に構
成し、なおかつノルマリオフ型トランジスタのド
レイン領域とノルマリオン型トランジスタのソー
ス領域を共通の埋め込み層によつて形成した半導
体集積回路は製作が容易でしかも、SITやパンチ
ングスルーBPTの良好な周波数特性を反映して、
低電力で高速度の動作が行え、その上高集積化が
できるので、その工業的価値は極めて高い。 By adjusting the gate spacing and impurity density distribution of the present invention, normal-off and normal-on operation can be achieved, or different operations can be performed depending on the polarity of the applied voltage.
A semiconductor integrated circuit in which SIT and punching-through BPT are configured on the same substrate and the drain region of a normally-off transistor and the source region of a normally-on transistor are formed using a common buried layer is easy to manufacture. Reflecting the good frequency characteristics of punching-through BPT,
Its industrial value is extremely high because it can operate at high speed with low power and can be highly integrated.
第１図ａ乃至ｃはSITをいた論理回路構造例、
第２図ａは本発明の断面構造例のゲート間隔を変
えた例、第２図ｂは本発明の断面構造例の印加電
圧の極性で特性が変る例、第３図は本発明の断面
構造例のパンチングスルーBPTのチヤンネル間
隔を変えた例である。
Figures 1a to 1c are examples of logic circuit structures with SIT,
Figure 2a is an example of a cross-sectional structure of the present invention in which the gate spacing is changed, Figure 2b is an example of a cross-sectional structure of the present invention whose characteristics change depending on the polarity of the applied voltage, and Figure 3 is a cross-sectional structure of the present invention. This is an example of changing the channel spacing of the punching-through BPT.
Claims (1)
第１導電型とは異なる第２導電型で低不純物密度
の半導体層を有し、前記半導体基板と前記半導体
層との間に埋め込まれた第２導電型で高不純物密
度の埋め込み領域をドレイン領域となし、前記半
導体層の表面側に形成された第２導電型で高不純
物密度の第１ソース領域と、前記第１ソース領域
を取り囲むように設けられた第１導電型で高不純
物密度の第１ゲート領域と、前記半導体層の一部
からなるチヤンネル領域とから構成されたノルマ
リオフ型静電誘導トランジスタを有し、また、前
記埋め込み領域をソース領域となし、前記半導体
層の表面側に形成された第２導電型で高不純物密
度の第２ドレイン領域と、前記第２ドレイン領域
を取り囲むように設けられ、かつ前記第１ゲート
領域よりもゲート間隔の広い、第１導電型で高不
純物密度の第２ゲート領域と、前記半導体層の一
部からなるチヤンネル領域とから構成されたノル
マリオン型静電誘導トランジスタを有する構造に
おいて、前記ノルマリオフ型静電誘導トランジス
タをドライバトランジスタに、前記ノルマリオン
型静電誘導トランジスタを負荷にしたことを特徴
とする半導体集積回路。 ２ 第１導電型の半導体基板の一主表面に、前記
第１導電型とは異なる第２導電型で低不純物密度
の半導体層を有し、前記半導体基板と前記半導体
層との間に埋め込まれた第２導電型で高不純物密
度の埋め込み領域をドレイン領域となし、前記半
導体層の表面側に形成された第２導電型で高不純
物密度の第１ソース領域と、前記第１ソース領域
を取り囲むように設けられ、かつ深くなるに従つ
て幅が減少する、１導電型で高不純物密度の第１
ゲート領域と、前記半導体層の一部からなるチヤ
ンネル領域とから構成されたノルマリオフ型静電
誘導トランジスタを有し、また、前記埋め込み領
域をソース領域となし、前記半導体層の表面側に
形成された第２導電型で高不純物密度の第２ドレ
イン領域と、前記第２ドレイン領域を取り囲むよ
うに設けられ、かつ前記第１ゲート領域とほぼ同
じゲート間隔で深くなるに従つて幅が減少する、
第１導電型で高不純物密度の第２ゲート領域と、
前記半導体層の一部からなるチヤンネルル領域と
から構成されたノルマリオン型静電誘導トランジ
スタを有する構造において、前記ノルマリオフ型
静電誘導トランジスタをドライバトランジスタ
に、前記ノルマリオン型静電誘導トランジスタを
負荷にしたことを特徴とする半導体集積回路。 ３ 第１導電型の半導体基板の一主表面に、第１
導電型で低不純物密度の半導体層を有し、前記半
導体基板と前記半導体層との間に埋め込まれた前
記第１導電型とは異なる第２導電型で高不純物密
度の埋め込み領域をコレクタ領域となし、前記半
導体層の表面側に形成された第２導電型で高不純
物密度の第１エミツタ領域と、前記第１エミツタ
領域を取り囲むように設けられた第１導電型で高
不純物密度の第１ベース領域と、前記半導体層の
一部からなるチヤンネル領域とから構成されたノ
ルマリオフ型パンチングスルーバイポーラトラン
ジスタを有し、また、前記埋め込み領域をエミツ
タ領域となし、前記半導体層の表面側に形成され
た第２導電型で高不純物密度の第２コレクタ領域
と、前記第２コレクタ領域を取り囲むように設け
られ、かつ前記第１ベース領域よりもベース間隔
の広い、第１導電型で高不純物密度の第２ベース
領域と、前記半導体層の一部からなるチヤンネル
領域とから構成されたノルマリオン型パンチング
スルーバイポーラトランジスタを有する構造にお
いて、前記ノルマリオフ型パンチングスルーバイ
ポーラトランジスタをドライバトランジスタに、
前記ノルマリオン型パンチングスルーバイポーラ
トランジスタを負荷にしたことを特徴とする半導
体集積回路。[Scope of Claims] 1. A semiconductor layer of a second conductivity type different from the first conductivity type and having a low impurity density is provided on one main surface of a semiconductor substrate of a first conductivity type, and the semiconductor substrate and the semiconductor layer A buried region of a second conductivity type and a high impurity density buried between the drain region and a first source region of a second conductivity type and a high impurity density formed on the surface side of the semiconductor layer; A normally-off static induction transistor includes a first gate region of a first conductivity type and high impurity density provided to surround a first source region, and a channel region made of a part of the semiconductor layer. , the buried region is used as a source region, a second drain region of a second conductivity type and high impurity density is formed on the surface side of the semiconductor layer, and a second drain region is provided so as to surround the second drain region, and A normal-ion static induction transistor comprising a second gate region of a first conductivity type and high impurity density, which has a wider gate interval than the first gate region, and a channel region made of a part of the semiconductor layer. 1. A semiconductor integrated circuit having a structure in which the normally-off type static induction transistor is used as a driver transistor, and the normally-on type static induction transistor is used as a load. 2. A semiconductor layer having a low impurity density and having a second conductivity type different from the first conductivity type is provided on one main surface of the semiconductor substrate of the first conductivity type, and is embedded between the semiconductor substrate and the semiconductor layer. A buried region of a second conductivity type and high impurity density is used as a drain region, and a first source region of a second conductivity type and high impurity density formed on the surface side of the semiconductor layer and the first source region are surrounded. The first conductivity type, high impurity density first layer is provided as shown in FIG.
It has a normally-off type static induction transistor composed of a gate region and a channel region made of a part of the semiconductor layer, and the transistor is formed on the surface side of the semiconductor layer, with the buried region serving as a source region. a second drain region of a second conductivity type and high impurity density; the second drain region is provided so as to surround the second drain region, and the width decreases as the depth increases, and the gate interval is approximately the same as that of the first gate region;
a second gate region of a first conductivity type and high impurity density;
In the structure having a normally-on type static induction transistor configured with a channel region made of a part of the semiconductor layer, the normally-off type static induction transistor is used as a driver transistor, and the normally-on type static induction transistor is used as a load. A semiconductor integrated circuit characterized by: 3. On one main surface of the semiconductor substrate of the first conductivity type, a first
a semiconductor layer having a conductivity type and a low impurity density, and a buried region having a second conductivity type different from the first conductivity type and having a high impurity density buried between the semiconductor substrate and the semiconductor layer as a collector region; A first emitter region of a second conductivity type and high impurity density formed on the surface side of the semiconductor layer, and a first emitter region of a first conductivity type and high impurity density provided so as to surround the first emitter region. It has a normal-off type punching-through bipolar transistor composed of a base region and a channel region made of a part of the semiconductor layer, and the buried region is an emitter region, and the transistor is formed on the surface side of the semiconductor layer. a second collector region of a second conductivity type and high impurity density; and a second collector region of a first conductivity type and high impurity density that is provided so as to surround the second collector region and has a base interval wider than the first base region. In the structure having a normally-on type punching-through bipolar transistor composed of two base regions and a channel region consisting of a part of the semiconductor layer, the normally-off type punching-through bipolar transistor is used as a driver transistor,
A semiconductor integrated circuit characterized in that the normally-on type punching-through bipolar transistor is used as a load.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3993483A JPS58169954A (en) | 1983-03-10 | 1983-03-10 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3993483A JPS58169954A (en) | 1983-03-10 | 1983-03-10 | Semiconductor integrated circuit |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9085577A Division JPS5918871B2 (en) | 1977-07-28 | 1977-07-28 | semiconductor integrated circuit |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4020792A Division JPH0618254B2 (en) | 1992-01-06 | 1992-01-10 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58169954A JPS58169954A (en) | 1983-10-06 |
| JPH0451066B2 true JPH0451066B2 (en) | 1992-08-18 |
Family
ID=12566768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3993483A Granted JPS58169954A (en) | 1983-03-10 | 1983-03-10 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58169954A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5425176A (en) * | 1977-07-28 | 1979-02-24 | Handotai Kenkyu Shinkokai | Semiconductor ic |
-
1983
- 1983-03-10 JP JP3993483A patent/JPS58169954A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5425176A (en) * | 1977-07-28 | 1979-02-24 | Handotai Kenkyu Shinkokai | Semiconductor ic |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58169954A (en) | 1983-10-06 |
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