JP3462224B2 - Complementary transistor circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The complementary transistor circuit of the present invention is capable of high-speed operation, low power consumption, low manufacturing cost, and suitable for high-density integrated circuits.
It can be used in configuring hardware in all information processing fields. Further, it is possible to replace all electronic circuits using complementary (complementary) transistor circuits with the complementary transistor circuit of the present invention. Therefore, information and energy control fields,
The complementary transistor circuit of the present invention can be used in the electronic industry, communication industry, and computer industry.

[0002]

2. Description of the Related Art In the case of the MOS type transistor developed so far, the power source for applying a voltage from the source to the gate and the power source for applying from the source to the drain are applied with reference to the source. Therefore, since there is a potential difference between the source and the drain, the electric field from the gate to the source and the drain is not uniform, and the electric field directly below the gate is nonuniform. That is, in the case of the N-channel, when a high "HIGH" level voltage is applied to the gate,
The electric field is directed from the gate to the source, and many lines of electric force are concentrated near the source, but the number of lines of electric force decreases immediately below the gate, which is separated from the source in the drain direction. In particular, since a high voltage is applied to the drain, there are almost no lines of electric force coming out of the gate. That is, there is no inversion layer near the drain, and a depletion layer is formed, which blocks the flow of the drain current and prevents high-speed operation. On the other hand, in the case of the N channel, when a low voltage is applied to the gate, there is no electric field from the gate to the source, so that the inversion layer does not appear immediately below the gate and the drain current does not flow. However, since a high voltage is applied to the drain, an electric field in the reverse direction from the drain to the gate is strong immediately below the gate near the drain, and dielectric breakdown easily occurs near that gate. Can not be used. This condition also hinders high-speed operation. These phenomena are caused by applying a voltage to the gate and the drain with the source as a reference point.

The current drivability of a MOS-FET is represented by a drain current flowing between a source and a drain. An increase in drain current in a transistor structure of the same geometric size improves the operation and speed of the logic circuit.
In order to improve the current driving capability, the gate size and the gate oxide film are reduced and the impurity concentration at the drain end is optimized. However, optimizing the impurity concentration at the drain edge accelerates device deterioration due to the hot carrier effect. The hot carrier effect is that electrons, which are carriers supplied from the source, collide and ionize with lattice atoms due to the high electric field near the drain, and the electrons and holes generated at that time are injected into the gate oxide film. , MO
This is a phenomenon in which the drain current characteristic is deteriorated due to the fluctuation of the threshold voltage of the S-FET and the like and it becomes impossible to operate as a high-speed logic circuit. Due to the hot carrier effect, defects such as shortening the device life appear. If the impurity concentration near the drain is increased, the device operates at high speed, but the electric field between the drain and the substrate increases, and the device reliability decreases due to the hot carrier effect. That is, there is a trade-off relationship between transistor performance and reliability.

Since it is difficult to increase the drain current of a MOS-FET, in order to increase the load current and perform a high speed operation, a bipolar transistor and a MOS-FE are required.
An integrated circuit including transistors having a so-called Bi-CMOS structure is manufactured by combining the T structures, but the manufacturing process is complicated and the number of transistors is large, so that it is difficult to improve the degree of integration.

In a conventional transistor circuit, AN
Since the D circuit and the OR circuit could not be constructed in one stage, a NAND circuit and a NOR circuit were constructed, and an AND circuit and an OR circuit were constructed by combining them with a NOT circuit which is an inverting circuit. This condition has become a barrier to increase the number of transistors and improve the degree of integration.

Further, in a transistor using gallium / arsenic, the mobility of holes is 1/10 to 1/20 or less of the mobility of electrons, and the use of holes as carriers results in low speed operation. It is difficult to construct a complementary (complementary) circuit.

[0007]

[Problems to be Solved by the Invention] Conventional MOS-FET
In the above, when the drain voltage increases and exceeds the drain saturation voltage, the local region at the drain end becomes a depletion layer, the portion becomes high resistance, and the drain current does not increase. In order to avoid this adverse effect and prevent the electric field between the drain and the gate and the electric field between the source and the gate from being generated, it is necessary to use two independent power supplies.
That is, in order for the field effect transistor to operate ideally, a power supply for applying a voltage to the gate to form an inversion layer just below the gate and a power supply for forming a channel by applying a voltage between the source and the drain. Need to be independent.

The channel portion of the transistor of the present invention has a structure in which an inversion layer is formed by using a power source independent of a source and a drain by two gates on both sides. This is called a double-sided gate independent power supply circuit.

An electric field is formed by applying a voltage between two facing gates by one power source, and an inversion layer is generated immediately below the gate. Further, by applying a voltage between the source and the drain by another power source, carriers generated in the inversion layer are moved to form a channel. In the conventional MOS-FET, these two power supplies are commonly used to form a single transistor circuit. Therefore, since the power supply is commonly applied between the source and the drain and between the source and the gate, the ideal MOS-FET operation cannot be performed in the vicinity of the drain, and a high resistance region is generated. , The current flow is restricted.
Therefore, the operation speed of the transistor circuit is limited, and the operation speed is low. That is, the action of the gate voltage is only required to form an inversion layer immediately below the gate and generate carriers in that region by the electrostatic induction effect. The drain voltage need only accelerate the generated carriers to move between the drain and the source. By performing these two operations with independent power supplies, it becomes possible to operate as an ideal field effect transistor.

Since the electric field between the drain and the gate causes the generation of hot carriers, the power supply for supplying the drain and the power supply for supplying the gate voltage are separately provided so that the electric field is not generated between the drain and the gate. Make sure that no electric field is generated between the gates.

Further, since the gate voltage of the conventional MOS-FET has a potential difference between the source and the drain and the source and the gate are close to each other and the drain and the gate are close to each other, the electrostatic capacitance generated in these regions becomes large. . These capacitances have been obstacles to high-speed operation of transistor circuits. Since high-speed operation can be realized by reducing these capacitances, it is necessary to try to reduce the capacitance.

The complementary (complementary) logic circuit has a low power consumption and a large logic amplitude, and is therefore a logic circuit close to an ideal one. However, the conventional complementary (complementary) transistor needs to use electrons and holes as carriers. The mobility of holes in the semiconductor is smaller than that of electrons, and the speedup of logical operation is limited by the mobility of holes. In particular, in MES-FETs using gallium arsenide, the mobility of holes is less than 1/10 to 1/20 of that of electrons, so that a complementary (complementary) circuit is configured to operate at high speed. It was difficult to do. The present invention proposes a transistor circuit capable of performing complementary (complementary) operation using only electrons as carriers.

In the conventional complementary (complementary) circuit, it is necessary to use P-channel and N-channel transistors, and a PN junction existing parasitically inside the integrated circuit occurs, and between these PN junctions and PNPN.
Depending on the circuit condition, a conductive state may occur between the junctions, and a parasitically large current such as a thyristor current may flow, causing a latch-up phenomenon that causes malfunction or destruction. Therefore, it is necessary to design the pattern of the integrated circuit in order to avoid this, and this causes a decrease in the integration density.

[0014]

In the double-sided gate independent power supply circuit of the present invention, two independent power supplies are used. Two gate electrodes are provided on both sides of the channel formation portion between the source and the drain. When one terminal of the first power supply is connected to one gate and the other terminal of the first power supply is connected to the other gate, an inversion layer is formed immediately below either of the two gates. . That is, when there is a P-type diffusion layer semiconductor immediately below the gate, electrons appear as carriers immediately below the gate to which a positive voltage is applied. Further, when the semiconductor of the N-type diffusion layer is directly below the gate, holes appear as carriers just below the gate to which a negative voltage is applied. Next, when a second power source is applied between the drain and the source, the carriers generated in the inversion layer move by the electric field to form a channel. That is, when the carrier is an electron, the electron is supplied from the source of the negative potential and moves toward the drain of the positive voltage to form an N-type channel. On the other hand, when the carrier is a hole, the hole is supplied from the positive potential source and moves toward the negative potential drain to form a P-type channel.

By applying the first and second power supplies independently, the drain current is not limited in the depletion layer region, so that high speed operation is achieved. When two independent power sources are optically or magnetically coupled, they are electrically isolated, so the electrical impedance between the two power sources is very high, so the two power sources There is very little current flowing between them. Therefore, a capacitance is generated between the drain and the gate between the electrodes, but since the power source applied to them is independent, the current flowing through the capacitance becomes extremely small due to the high impedance. Therefore, the capacitance is substantially the same as when there is no capacitance, and the transistor circuit operates at high speed. Similarly, a capacitance between the electrodes is generated between the source and the gate,
Since the power supply applied to them is independent, the current flowing through the capacitance is extremely small due to the high impedance. Therefore, the capacitance is substantially the same as when there is no capacitance, and the transistor circuit operates at high speed.

One of the gates facing each other on both sides of the channel serves as a bias gate and the other serves as a control gate. The potential difference between the bias gate and the control gate controls the current flowing in the channel forming portion of the field effect transistor. That is, by forming a channel directly below one of the two gates, the conventional P-channel MOS-FET and N-channel MOS-FE are formed.
It becomes possible to perform the same operation as T. Therefore,
The circuit configuration and the semiconductor manufacturing process are simplified, and the possibility of parasitically flowing current due to the PN junction hardly occurs.

In a complementary (complementary) MOS logic circuit, a PNPN parasitically present in an integrated circuit
There is a latch-up phenomenon in which the thyristor becomes conductive and a large amount of current flows to cause malfunction or damage. Since the complementary (complementary) circuit of the present invention can be configured with only N channels, the possibility that the latch-up phenomenon will occur is extremely reduced.

[0018]

The operation of the transistor of the present invention will be described by taking the N-channel MOS-FET shown in FIG. 1 as an example. Note that P
In the case of the channel MOS-FET, since the carriers are holes, the mobility is lower than the mobility of the electrons, which are N-channel carriers, and the operating speed is reduced. However, the present invention also includes the case of a P-channel MOS-FET.

As shown in FIG. 1, when the two terminals of the first power source are connected to the two gates provided on both sides of the P-type semiconductor, the positive voltage of the first power source is generated due to the electrostatic induction phenomenon. Electrons, which are carriers, are attracted immediately below the gate to which the terminal is connected, and an inversion layer is formed in that region. That is, when there is a P-type diffusion layer semiconductor directly below the gate, electrons appear as carriers immediately below the positive potential gate, and when there is an N-type diffusion layer semiconductor directly below the gate, a negative potential appears. Holes appear as carriers just below the potential gate. Next, a second power supply is applied between the drain and the source. In the case of N-channel MOS-FET, if the positive terminal of the second power supply is connected to the drain and the negative terminal is connected to the source, the carriers in the inversion layer move due to the electric field created by the second power supply. Thus, a channel is formed just below the gate. That is, when the carrier is an electron, the electron is supplied from the source having a negative potential and moves toward the drain having a positive voltage to form an N-type channel. on the other hand,
When the carrier is a hole, the hole is supplied from the positive potential source and moves toward the negative potential drain to form a P-type channel. At this time, it is a condition for the current to smoothly flow that the channels are evenly arranged immediately below the gate. In order for the channel to be uniformly formed from the source to the drain, the inversion layer must be formed evenly from the source directly under the gate to the drain. In the case of the MOS type transistor developed so far,
The power source for applying a voltage from the source to the gate and the power source for applying a voltage from the source to the drain were both based on the source. Therefore, the electric field from the gate to the source and the drain is not uniform, and the electric field directly under the gate is nonuniform. That is, in the case of the N channel, when a high voltage is applied to the gate, the electric field goes from the gate to the source, but many electric lines of force concentrate near the source and separate from the source in the drain direction. , The number of electric lines of force is reduced. In particular, since a high voltage is applied to the drain, the lines of electric force emitted from the gate are almost eliminated. That is, the inversion layer disappears near the drain and becomes a depletion layer, the flow of the drain current is blocked, and the high speed operation is stopped. Further, in the case of N-channel, when a low voltage is applied to the gate, the electric field from the gate to the source disappears, so that the inversion layer does not appear immediately below the gate and the drain current does not flow. When the source is separated from the drain in the direction of the drain, a high voltage is applied to the drain, so the electric field in the opposite direction from the drain to the gate becomes strong, and dielectric breakdown easily occurs in the vicinity, so use a too thin gate oxide film. It cannot be used, which creates a barrier to fast operation. This phenomenon is caused by applying a voltage to the gate and drain with the source as a reference point. Therefore, in order to ideally operate the field-effect transistor, it is necessary to separate the first power supply applied to the gate to form the inversion layer directly below the gate and the second power supply applied between the source and the drain. There is. The first power source is applied to form a uniform inversion layer directly under the gate, and the second power source is applied to move carriers generated in the inversion layer from the source to the drain direction to form a channel. Since the electric field from the drain to the source and the electric field from the gate to the channel are independent, the non-uniformity of the electric field for forming the inversion layer on the side close to the source and the side close to the drain is eliminated, and the electric field directly under the gate is eliminated. Thus, the inversion layer is formed. Therefore, when it is used as a channel, there are almost no areas that reduce drain current flow.

[0020]

EXAMPLE An N-channel field effect transistor will be described as an example of the present invention. The same description can be applied to a P-channel field effect transistor. In the following description, two power supplies are used. The positive terminal of one of the power supplies is + VDD1 and the negative terminal is GND1. Further, the positive terminal of the other power source will be described as + VDD2, and the negative terminal will be distinguished from GND2.

[Silicon Transistor Circuit] FIG. 1 shows the structure and transistor circuit of a field effect transistor using silicon. On both sides of the P-type semiconductor 1 there is a source 2 of heavily doped N-type semiconductor and a drain 3 of heavily doped N-type semiconductor. further,
A control gate 4 and a bias are provided on both sides of the P-type semiconductor 1.
Gate 5 is installed. These two gates are insulated by the gate oxide film 6 from the P-type semiconductor that is the channel constituent portion. The positive terminal of the first power supply 7 is connected to the control gate 4, and the negative terminal of the first power supply 7 is connected to the bias gate 5. Further, the source 2 is connected to the negative terminal of the second power supply 8, and the drain 3 is connected to the positive terminal of the second power supply 8. Electrons that are carriers appear just below the control gate 4, and an inversion layer is formed. The emerged carriers are moved in the drain direction by the electric field generated by the second power source 8 applied to the source 2 and the drain 3 to form a channel. That is, the first power supply 7 for forming the inversion layer and the emerging carriers are moved, and the second power supply 8 forming the channel is electrically independent and magnetically or optically coupled, thereby electrically The impedance becomes large, and it becomes possible to operate an ideal electric field transistor.

[Gallium / Arsenic Transistor Circuit] As one embodiment of the present invention, an N-channel field effect transistor will be described. FIG. 2 shows the structure and transistor circuit of a field effect transistor (MES-FET) using gallium arsenide (GaAs). On both sides of the P-type semiconductor 1 there is a source 2 of heavily doped N-type semiconductor and a drain 3 of heavily doped N-type semiconductor. Further, the control gate 4 is formed on both sides of the P-type semiconductor 1.
And a bias gate 5 is installed. These two gates make Schottky contact with the P-type semiconductor, which is the channel component, and are therefore also called Schottky gates. All of these are covered with an insulator 10. The positive terminal of the first power supply 7 is connected to the control gate 4, and the negative terminal of the first power supply 7 is connected to the bias gate 5. Further, the source 2 is connected to the negative terminal of the second power supply 8, and the drain 3 is connected to the positive terminal of the second power supply 8. Electrons that are carriers appear just below the control gate 4, and an inversion layer is formed. The emerging carrier is Source 2
A channel is formed by moving in the direction of the drain by the electric field created by the second power supply 8 applied to the drain 3. That is, the first power supply 7 for forming the inversion layer and the emerging carriers are moved, and the second power supply 8 forming the channel is electrically independent and magnetically or optically coupled to each other. The impedance becomes large, and it becomes possible to operate an ideal electric field transistor. Since the mobility of holes in a gallium arsenide Schottky gate field effect transistor is sufficiently smaller than that of electrons, a transistor circuit of the present invention that can form a complementary logic circuit without using holes as carriers is provided. Be beneficial.

[Buffer Circuit] In the buffer circuit of FIG.
Control gate (first gate) to which input voltage VIN is supplied
The opposing provided biasing the gate (second gate) is connected to one power supply terminal + VDD2 of the two power supplies, the input voltage VIN of the Q2 transistor 9 is supplied
That the control gate (third gate) to the counter to provided bi-<br/> Asugeto (fourth gate) is connected to two of said one power supply terminal GND2 of the power supply. When the input voltage VIN of "HIGH" state to the input of this circuit is input, the input voltage VIN is applied close to the + VDD2 to the control gate of the control gate and Q2 of Q1 transistor 9. Therefore, since the bias gate voltage of Q1 is + VDD2, there is a voltage between the control gate and the bias gate of Q1.
No control field or bias gate
The inversion layer is not formed and the channel is not formed even in the substrate immediately below the shift . Therefore, Q1 becomes non-conductive, and the resistance between the output terminal and GND1 becomes high, but the bias gate voltage of Q2 is GND2, so Q2 has a control gate.
Since an electric field from the gate to the bias gate is generated,
An inversion layer is formed immediately below the control gate to form a channel. Therefore, Q2 becomes conductive, and the output end and + VDD1
And a low resistance state. Therefore, the output terminal has a voltage close to VDD1 and the output is in the "HIGH" state. Conversely, if the "LOW" state is input to the input of this circuit,
The control gate of Q1 and Q2 of the transistor 9 has GND2
A potential close to is applied. Therefore, the bias gate voltage of Q1 is a + VDD2, bias gate in Q1
Electric field from the gate to the control gate
A channel is formed by forming an inversion layer in the substrate directly below the substrate . Therefore, Q1 becomes conductive and the resistance between the output terminal and GND2 becomes low, but the bias gate voltage of Q2 is GND2. Therefore, an inversion layer is formed in Q2.
Since no channel is formed, Q2 becomes non-conductive, and a high resistance state exists between the output end and + VDD1.
Therefore, the output terminal has a voltage close to GND1 and the output is in the "LOW" state.

[Inverter circuit] In the inverter circuit of FIG.
Power bias gate (second gate) is connected to one power supply terminal GND2 of the two power, bias gate (fourth gate) of the Q2 transistor 9 of the one of the two power Connected to the terminal + VDD2.
When the input voltage VIN in the "HIGH" state is input to the input of this circuit, a voltage close to + VDD2 is applied to the control gates of Q1 and Q2 of the transistor 9. Therefore, Q
Since the first bias gate voltage is GND2, Q1 of
An inversion layer is formed immediately below the control gate, and a channel is formed in Q1. Therefore, Q1 becomes conductive, and a low resistance state exists between the output end and GND1. Therefore, Q2
Since the bias gate voltage is + VDD2, Q2 of
No electric field is generated between the control gate and bias gate,
No channel is formed in 2. Therefore, Q2 becomes non-conductive, and a high resistance state exists between the output terminal and + VDD1. Therefore, the output terminal has a voltage close to GND1, and the output is in the "LOW" state. Conversely, when the "LOW" state is input to the input of this circuit, Q1 of the transistor 9
A voltage close to GND2 is applied to the control gates of Q2 and Q2. Therefore, since the bias gate voltage of Q1 is GND2, no electric field is generated between the bias gate voltage and the control gate.
There is no channel formed in. Therefore, Q1 becomes non-conductive and a high resistance state is established between the output terminal and GND2, but since the bias gate voltage of Q2 is + VDD2, the bias gate voltage of Q2 goes from the bias gate to the control gate.
Field is generated, and there is no reaction in the substrate directly below this bias gate.
An inversion layer is formed and a channel is formed in Q2. Therefore, Q2 becomes conductive, and a low resistance state exists between the output terminal and + VDD1. Therefore, the output terminal has a voltage close to + VDD1, and the output is in the "HIGH" state.

[NAND logic circuit] In the NAND circuit of FIG. 5, the bias gates of Q1 and Q3 of the transistor 9 are connected to the terminal GND2 of one of the two power supplies, and the bias of Q2 and Q4 of the transistor 9 is connected. The gate is connected to the terminal + VDD2 of one of the two power supplies. "H" for both inputs of this circuit
When the "IGH" state is input, Q1 and Q3 of the transistor 9 become conductive, and the output is in the "LOW" state. For the other inputs, the output is in the "HIGH" state. A NAND logic circuit can be realized.

[AND Logic Circuit] In the AND circuit of FIG. 6, the bias gates of Q1 and Q2 of the transistor 9 are connected to the terminal GND2 of one of the two power supplies, and the bias of Q3 and Q4 of the transistor 9 is connected. The gate is connected to the terminal + VDD2 of one of the two power supplies. For both inputs of this circuit, "HIG
When the "H" state is input, Q1 and Q2 of the transistor 9
Becomes conductive, and the output becomes "HIGH". For other inputs, the output is "LOW", so
AND logic can be implemented by the circuit shown in FIG. In the conventional complementary logic circuit, it was not possible to realize an AND logic circuit with four transistors, but it is possible to realize a complementary AND logic circuit with four transistors, which is the minimum number of transistors of the present invention. Will be possible.

[OR Logic Circuit] In the OR logic circuit shown in FIG. 7, the bias gates of Q2 and Q4 of the transistor 9 are connected to the terminal GND2 of one of the two power supplies, and Q1 and Q3 of the transistor 9 are connected. The bias gate of is connected to the terminal + VDD2 of one of the two power supplies. Both the two inputs of this circuit are "LO
When the "W" state is input, Q1 and Q3 of the transistor 9
Becomes conductive, and the output becomes "LOW". For other inputs, the output is in the "HIGH" state, so
The OR logic can be realized by the circuit shown in FIG. In the conventional complementary logic circuit, an OR logic circuit could not be realized with four transistors.
The smallest number of transistors of the invention 4
It is possible to realize a complementary OR logic circuit individually.

[Three-State Logic Circuit] In the three-state logic circuit (tri-state logic) shown in FIG. 8, the bias gate of Q4 of the transistor 9 is connected to the terminal GND1 of one of the two power supplies, The drain of Q4 is + VDD2, and the bias gate of Q3 of transistor 9 is the terminal GND1 of one of the two power supplies.
, And the source of Q3 is connected to GND2. VCONT which is the control input of this circuit is "LOW"
In this state, Q3 and Q4 of the transistor 9 become non-conductive, and the output is in a high impedance state regardless of the input. On the other hand, when the control input VCONT becomes "HIGH", Q3 and Q4 of the transistor 9 become conductive,
The output is in a state where the input is inverted and becomes a normal NOT circuit. That is, since the output can be set to a high impedance state in addition to the operation as a normal inverter, a three-state logic circuit is realized. In the conventional three-state complementary logic circuit, the logic could not be realized by four transistors, but in the transistor of the present invention, the minimum number of transistors, four, realizes a complementary three-state logic circuit. Things will be possible.

[Plurality of Gate Electrodes] An embodiment in which the gate is composed of a plurality of facing electrodes is shown in FIG.
Shown in. In the case of FIG. 9, it is an N-channel transistor composed of seven pairs of facing gates, but a P-channel transistor can also be constructed by the method of the present invention. This transistor biases one of several gate pairs
It can be used as a gate, and the drain current can be controlled by the potentials of a plurality of other gate pairs, and can be applied to a neuron element of a neural network or a digital logic circuit.

[0030]

In general, the drain current decreases as the voltage between the drain and source of the field effect transistor decreases. On the other hand, the voltage between the gate and the source decreases with the increase of the source voltage in the conventional transistor, but in the transistor of the present invention, since the voltage of the source is constant, the decrease of the drain voltage is significantly reduced. That is, even if the voltage across the terminals decreases, the decrease in drain current is small, so that the operation can be performed at high speed.

By using the transistor of the present invention, a complementary circuit can be formed without using holes as carriers. That is, a complementary circuit, which is an ideal logic circuit, can be formed by using only electrons having a carrier mobility higher than that of holes and capable of high-speed operation as carriers. By applying a voltage to the bias gate to form an inversion layer just below either of the two gates flanking the channel, it becomes possible to perform a logical operation on the input voltage. This effect almost eliminates the possibility of thyristor current occurring in the PNPN junction.

In the conventional transistor circuit, two inverters are connected in two stages to form a buffer circuit, but when the transistor of the present invention is used, a buffer circuit is also formed in a single-stage transistor circuit. be able to.

A tri-state logic circuit (tri-state l)
Since it is possible to reduce the number of transistors for configuring the circuit) as compared with the conventional one, a circuit with high integration density can be realized.

In the conventional transistor circuit, it was difficult to construct a complementary AND circuit or OR circuit in one stage, but when the transistor of the present invention is used, a complementary AND circuit or OR in one stage is used. It becomes possible to configure a circuit.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a transistor of the present invention and a transistor circuit for connecting two independent power sources.

FIG. 2 is a block diagram of a gallium / arsenic transistor of the present invention and a gallium / arsenic transistor circuit connecting two independent power sources.

FIG. 3 is a buffer circuit according to an embodiment of the present invention.

FIG. 4 is an inverter (inverting) circuit according to one embodiment of the present invention.

FIG. 5 is a NAND circuit according to one embodiment of the present invention.

FIG. 6 is an AND circuit according to one embodiment of the present invention.

FIG. 7 is an OR circuit according to one embodiment of the present invention.

FIG. 8 is a three-state logic circuit according to one embodiment of the present invention.

FIG. 9 is a transistor and a transistor circuit including a plurality of gate pairs according to an embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P-type semiconductor 2 ... Source with heavily doped N-type semiconductor 3 ... Drain with heavily doped N-type semiconductor 4 ... Control gate 5 ... bias gate 6 ... gate oxide film 7 ... first power supply 8 ... second power supply 9 ... transistor 10 ... insulator 11 ... Gate pair

Claims (4)

(57) [Claims] 1. A first and a second N-channel field effect transistor are provided, wherein the first field effect transistor faces a front surface and a back surface of a P-type semiconductor substrate with a gate insulating film interposed therebetween. The formed first and second gates, and the N-type first source and the first N-type source and the first gate formed between the first and second gates across the front surface and the back surface, respectively, in the semiconductor substrate. A second field effect transistor, wherein the second field effect transistor has third and fourth gates formed on the front surface and the back surface of the P-type semiconductor substrate so as to face each other with a gate insulating film interposed therebetween; , And an N-type second source and a second drain formed across the front surface and the back surface in the semiconductor substrate with the fourth gate interposed therebetween, and further, the first field effect transistor. The first drain and the second electric field The second source of the effect transistor is connected to the first source, and "LOW" is applied to the first source.
Means for supplying a potential of "HIGH" to the drain of the first power source, and one of the potentials of "HIGH" and "LOW" from the second power source to the second gate, Means for supplying the other potential of "HIGH" or "LOW" from the second power source to the gate; and "HIG" of the second power source for the first and third gates.
Means for commonly providing an input potential close to the potential of "H" or "LOW", wherein "HIGH" is applied to the second gate and "L" is applied to the fourth gate.
When the "HIGH" input potential is applied to the first and third gates while the OW "potential is applied,
An inversion layer is formed only directly under the third gate, only the second N-type field effect transistor is turned on, “LOW” is applied to the second gate, and “HI” is applied to the fourth gate.
When the input potential of "LOW" is applied to the first and third gates while the potential of GH "is applied, the inversion layer is formed only immediately below the fourth gate, and the second gate is formed.
Complementary transistor circuit characterized in that only the N-type field effect transistor is turned on. 2. The first and third gates are commonly connected to an input terminal, and the first drain and the second source are commonly connected to an output terminal. The complementary transistor circuit according to. 3. The first source is connected to a “LOW” terminal of the first power supply, the second drain is connected to a “HIGH” terminal of the first power supply, and the second gate is connected. Is connected to the "HIGH" terminal of the second power supply, the fourth gate is connected to the "LOW" terminal of the second power supply, and is buffered by the first and second N-type field effect transistors. The complementary transistor circuit according to claim 2, wherein the circuit is configured. 4. The first source is connected to a “LOW” terminal of the first power supply, the second drain is connected to a “HIGH” terminal of the first power supply, and the second gate is connected. Is connected to the "LOW" terminal of the second power supply,
The fourth gate is connected to a "HIGH" terminal of the second power supply, and an inverter circuit is configured by the first and second N-type field effect transistors. Complementary transistor circuit.