JPS6212167A - Manufacture of vertical type semiconductor device with groove section - Google Patents

Abstract

PURPOSE:To form a groove section smoothly, to prevent the generation of the concentration of an electric field and to increase withstanding voltage by selectively oxidizing a semiconductor base body through an opening section for an oxidation-resistant insulating film to shape an oxide film and removing the oxide film through etching to form the groove section. CONSTITUTION:An n-type semiconductor layer 12 in impurity concentration lower than that of an n<+> type semiconductor base body 11 is shaped onto the semiconductor base body 11. An oxide film 13 is formed, and an oxidation-resistant insulating film 14 is shaped selectively. The n-type semiconductor layer 12 is oxidized selectively through opening sections 14a for the oxidation-resistant insulating film 14 to selectively form oxide films 15. The oxidation-resistant insulating film 14 is removed through etching, a p-type diffusion layer 16 is shaped in a self-alignment manner while using the thick oxide film 15 as a mask, an n<+> type diffusion layer 17 is formed selectively, an oxide film 18 is shaped, a resist film 19 is formed selectively and etched, and the oxide films 15 are gotten rid of, thus shaping groove sections. The shapes of the contours of the groove sections are smoothed, and gate oxide films 21 and polycrystalline silicon films 22 are formed.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a vertical semiconductor device in which a V-shaped or U-shaped groove is formed on the main surface of a semiconductor substrate. It is.

(Prior art) A vertical MOS transistor in which a V-shaped or U-shaped groove is formed on the main surface of a semiconductor substrate has excellent high frequency characteristics, and in particular, because the channel width can be made long, the on-resistance is low and the switching speed is high. It has the characteristic of being fast.

FIG. 4 does not show the cross-sectional shape of a conventional vertical MOS transistor having a V-shaped groove, and such a transistor is disclosed in, for example, Japanese Patent Laid-Open No. 193064/1983. The semiconductor body has an n-on-n+ structure comprising an n) silicon substrate 1 and an n- epitaxial layer 2 grown thereon. A V-shaped groove 3 is formed in the main surface of the epitaxial layer 2, and a gate electrode 1! is formed on the surface of this groove with a gate insulating film 4 interposed therebetween. J5 is formed. A p-type first semiconductor layer 6 is formed around the V-shaped groove 3, and an n+-type second semiconductor layer 6 is formed inside the p-type first semiconductor layer 6.
i7 is formed. A drain electrode film 8 is formed on the back surface of the n-type substrate 1, and an epitaxial layer 2
A source electrode 10 is provided on the main surface of the substrate 1 with an insulating film 9 interposed therebetween so as to be in ohmic contact with both the first and second semiconductor layers 6 and 7 .

(Problems to be Solved by the Invention) In a MOS transistor having such a V-shaped groove, the tip 3a of the groove 3 is sharp, so the electric field concentrates and the gate insulating film 4 is destroyed. The disadvantage is that the withstand voltage decreases. Generally, the single-shaped groove is made of silicon epitaxial! Since it is formed by anisotropic etching of m2, the groove light E 3 a inevitably becomes sharp.

In the above-mentioned special rfrJ publication No. 59-193064, p
The second semiconductor layer 6 of the mold is extended downward from the tip of the groove 615 while sandwiching the groove from a predetermined distance away from the groove, and the interval between the portions extending downward from the tip of the groove is partially narrowed. It has been proposed to reduce the concentration of the electric field by However, such a solution is not a fundamental solution because the shape of the tip of the groove remains sharp, and an extra diffusion step is required to obtain the desired profile of the first semiconductor layer. There is a drawback that. Furthermore, it is difficult to precisely control the method of forming grooves by chemical etching.In particular, as elements become smaller and grooves are required to be finer, it becomes difficult to control the process, and it becomes difficult to control the exact dimensions and shape. There is also the disadvantage that it is no longer possible to form grooves.

The present invention has been made in view of the above-mentioned problems, and it is possible to form a groove portion without a sharp tip where an electric field is concentrated with high precision and high reproducibility, thereby manufacturing a vertical semiconductor device with improved breakdown voltage. The purpose is to provide a method that can be used.

(Means for Solving the Problems) The manufacturing method of the present invention includes a semiconductor substrate of one conductivity type, a groove formed on the main surface of the semiconductor substrate, and an M a polar film; a first semiconductor layer of opposite conductivity type and a second semiconductor layer of one conductivity type formed vertically on the main surface of the semiconductor substrate so as to surround the groove and partially overlap with the electrode film; In manufacturing a vertical semiconductor device comprising: a step of forming the groove portion, a step of selectively forming an oxidation-resistant insulating film on the main surface of the semiconductor substrate; This method is characterized by comprising a step of oxidizing the semiconductor substrate through the opening to form an oxide film, and a step of removing the oxide film by etching.

(Function) According to the manufacturing method of the present invention described above, the groove is not formed by chemical etching, but the portion of the semiconductor substrate where the groove is to be formed is selectively oxidized, and the oxidized portion is etched. However, since this oxidation is isotropic, a sharp tip is not formed, and a groove with a smooth contour is formed.
Therefore, no concentration of electric field occurs. Also, the oxidation process is extremely [? Therefore, the dimensions and shape of the groove can be controlled accurately and with high reproducibility. In this way, a vertical semiconductor device with high breakdown voltage can be accurately manufactured.

<Example> Figures 1(a) to <X show the sequential 'FJ manufacturing process of an example of the method for manufacturing a vertical semiconductor device having a groove portion according to the present invention.In this example, a vertical MO8FET is manufactured. It is something to do. An n-type semiconductor layer 12 having a lower impurity concentration is formed on the n++ semiconductor substrate 11 having a higher impurity concentration. In this example, this n-type semiconductor layer 12 is formed by evidaxial growth, but it can also be formed by other methods such as a pulling method. After forming an oxide film 13 with a thickness of approximately 1000 μm on the surface of the n-type semiconductor layer 12, a nitride film 13 with a thickness of approximately 3000 μm is formed thereon, and this nitride film is buttered to resist oxidation. FIG. 1(a) shows a state in which the insulator 1114 is selectively formed.

Subsequently, thermal oxidation treatment is performed to selectively oxidize the n-type semiconductor layer 12 through the opening 14a of the oxidation-resistant insulation layer 14, and selectively oxidize the oxide film 15 having a thickness of about 1.5 μI. Form. Thereafter, the oxidation-resistant insulating film 14 made of a nitride film is removed by etching, for example, by hot phosphoric acid or Freon dry etching at 180°C.
Shown in b).

Next, using the thick oxide film 15 as a mask, a p-type diffusion layer (first semiconductor layer) 16 constituting the channel region is formed in a self-aligned manner, and then a mask is selectively formed using photoetching technology, and a p-type diffusion layer (first semiconductor layer) 16 is formed in a self-aligned manner. FIG. 1C shows how an n + -type scattering layer second semiconductor layer (second semiconductor layer) 17 constituting a source region is selectively formed in the type diffusion layer 16 .

Next, thermal oxidation treatment is performed again to form an oxide film 18 with a thickness of approximately 3,000 yen, and a resist film 19 is selectively formed thereon, as shown in FIG. 1(d).

Next, etching is performed to remove the oxide 1115 and form a groove 20 having a depth of about 0.7 to 0.8 μm. The contour of this groove 20 is smooth, and no sharp parts are formed.Next, a gate oxide film 21 with a thickness of about 1000 mm is formed in this groove, and a gate electrode is roughly formed on top of the gate oxide film 21. Figure 1 (C) shows how the constituting polycrystalline silicon p; J22 was selectively formed to a thickness of about 6000 mm.

This gate polycrystalline silicon 11!22 is a p-type diffusion layer 16.
and n+ type scattering layer 17 are formed so as to partially overlap with each other. Note that in FIG. 1 ((1)), the oxide films 13 and 18 are shown as a single layer oxide film 23.

Next, CVD method k1. After TcVD-8i 021U24 is deposited to a thickness of approximately 5000 mm, heat treatment is performed. After forming contact holes 23a and 24a in the oxide film 23 and the CVD-8i 02 film 24, a metal 'R' electrode film 25 is selectively formed by evaporating A (FIG. 1(f)).
The vertical MOS transistor shown in is completed.

FIGS. 2(a) to 2(e) show the sequential manufacturing steps of another embodiment of the manufacturing method of the present invention. An n-type semiconductor layer 32 is formed on an n++ semiconductor substrate 31, and an oxide #I33 layer having a thickness of approximately 1000 nm is further formed on the main surface of this n-type semiconductor layer 32.
form. Next, on the main surface of the n-type semiconductor layer 32, a p-type diffusion layer 34, which simulates a channel region, and an n++ diffusion layer 11i35, which will later constitute a source region, are formed. After that, an oxidation-resistant insulating film 36 made of a nitride film is selectively formed on the oxide film 33 to a thickness of approximately 3,000 mm, as shown in FIG.
Shown in a). The oxide film 33 is a buffer that prevents defects from being introduced into the n-type semiconductor layer 32 during thermal oxidation treatment. It acts as a.

Next, the buffer oxide film 33 should be formed with grooves.
After selectively removing the material at the "" position, a V-shaped groove 37 is formed using an etchant containing KOH as a main component. Note that the etching depth at this time may be such that the tip of the groove 37 exceeds the boundary between the p-type diffusion WJ 34 and the n-type semiconductor layer 32, or may not reach this boundary.

The state in which the grooves 37 are formed in this manner is shown in FIG. 2(b).

Subsequently, thermal oxidation treatment is performed using the oxidation-resistant insulating film 36 as a mask. This thermal oxidation process is performed at a temperature of about 90 to 150°C at a temperature of 1000°C in an atmosphere pressurized to 7 to 8 atmospheres, for example.
This is done by applying high-pressure hydrogen combustion oxidation for minutes.

As a result, while suppressing the diffusion progress of the p-type diffusion layer 34 and the n+ type wide diffusion layer 35 as much as possible, a thick oxidized Mi layer of, for example, about 1.5 μm is formed! form 38. After that, the oxidation-resistant insulating film 3B
FIG. 2(C) shows how it is removed. In this case, since the oxide film 38 is uniformly formed in the semiconductor 1i132,
Its contour shape becomes clear.

Next, the thick oxide film 38 is removed by etching to expose a groove 39 with a smooth surface shape, and an oxide film 42 is formed in this groove to a thickness of approximately 1000 nm, and a gate electrode is formed on top of the oxide film 42. A polycrystalline silicon film 40 is selectively formed. This situation is shown in FIG. 2(d). In FIG. 2(d), the buffer oxide film 33 and the gate oxide 1I42 are shown as an oxide 11141.

Thereafter, a CVD-8i 02 film 43 is formed to a thickness of approximately 5000 mm, and further this CVD-8i 02 @43,
Contact holes 43a and 4 are formed in the oxide film 41, respectively.
1a is formed, and the 01 type diffusion layer 35 is partially etched away to expose a part of the p type semiconductor layer 34. Finally, the A1 N electrode film 44 is selectively formed to a thickness of about 3.5 .mu.m to complete the vertical MOS transistor, as shown in FIG. 2(e).

FIGS. 3(a) to 3(e) show the sequential steps of still another embodiment of the method for manufacturing a vertical semiconductor device of the present invention. In this example, an n
A type silicon semiconductor layer 52 is formed, and about 1 layer is further formed thereon.
FIG. 3(a) shows a state in which a buffer oxide film 53 having a thickness of 1,000 mm is formed, and an oxidation-resistant insulating film 54 made of a nitride film is selectively formed thereon.

Next, a thermal oxidation treatment is performed to form a thick oxidized WA 55 with a thickness of about 1.0 μm in the opening of the oxidation-resistant insulating film 54, as shown in FIG. 3(b).

Thereafter, the thick oxide film 55 is removed by etching using the oxidation-resistant insulator 1I54 as a mask to form a groove 56, as shown in FIG. 3(C).

Subsequently, thermal oxidation treatment was performed again to form a thick oxide film 57 of about 1.5 to 2.0 μm, as shown in FIG. 3(d)'.

Next, the oxidation-resistant insulation WA54 made of a nitride film, the thin buffer oxide film 53, and the thick oxide film 156 are removed by etching to form an n-type semiconductor 1lI5.
FIG. 3(e) shows a state in which a smooth groove 58 having a depth of approximately 1.0 to 1.5 μm is formed on the main surface of the substrate.

Thereafter, processes similar to those shown in FIGS. 1(e) and 1(f) are performed to complete a vertical MOS transistor.

In this embodiment, after removing the thick oxide film 56, the groove portion 57 is formed by repeating the process of forming a thick oxide film by performing thermal oxidation treatment again without removing the oxidation-resistant insulating film 54. The depth can be any depth.

The present invention is not limited to the embodiments described above, but can be modified in many ways. For example, in the above-described embodiment, a vertical MoS transistor is manufactured, but what about vertical MoS transistors? It can be applied to manufacturing other vertical semiconductor devices such as fi-induced transistors and vertical bipolar transistors. Furthermore, the p-type and the p-type may be opposite to those in the above-mentioned embodiment. Further, as the oxidation-resistant insulating film, an alumina group film or the like can be used in addition to the nitride film. Further, the gate electrode film is not limited to a polycrystalline silicon film, but may also be made of a high melting point metal such as molybdenum, tungsten, chromium, or a silicide thereof. Furthermore, in the embodiment shown in FIG.
Although the resist film 18 is formed before removing the resist film 5, this resist film is not necessarily necessary.

(Effects of the Invention) According to the manufacturing method of the present invention described above, m5IN is not formed by chemical etching as in the conventional method, but by selectively oxidizing the semiconductor substrate through the opening of the oxidation-resistant insulating film. Since the groove is formed by forming an oxide film and removing this oxide film by etching, the contour of the groove is smooth and has no sharp points, so there is no concentration of electrolyte and the withstand voltage is low. can be improved. Further, the oxidation treatment and the etching removal treatment of the oxide film can be performed accurately using relatively stable processes. In particular, recent advances in oxidation technology have made it possible to control the thickness with an accuracy of several tens of orders of magnitude, making it possible to accurately form the groove into a desired shape. Furthermore, by controlling the thickness of the buffer oxide film, the size of the bird's beak can be determined, and the smoothness of the groove can also be controlled accordingly.

[Brief explanation of the drawing]

1(a) to (f) are cross-sectional views showing sequential manufacturing steps 1 of an embodiment of the method for manufacturing a vertical semiconductor device having a groove portion according to the present invention; □ FIG. 2(a) to (e) are Similarly, FIGS. 3(a) to 3(e) are sectional views showing the sequential manufacturing steps of another embodiment, and FIG. 4 is a conventional method. FIG. 2 is a cross-sectional view showing a vertical semiconductor device having a groove portion manufactured in the above. 11... N+ type semiconductor substrate 12... N type semiconductor layer 13... Oxide film 14...
- Oxidation-resistant insulating film 15... Oxide film 16, 17...
First and second semiconductor layers 18... oxide film 2
1... Gate oxide film 22... Polycrystalline silicon film 24, CVD-8i 02 film 25... Electrode film

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, a groove formed on the main surface of the semiconductor substrate, an electrode film formed in the groove with an insulating film interposed therebetween, and the main surface of the semiconductor substrate. a first semiconductor layer of an opposite conductivity type and a second semiconductor layer of one conductivity type formed vertically to surround the groove and partially overlap the electrode film;
In manufacturing a vertical semiconductor device comprising a semiconductor layer, the step of forming the groove includes a step of selectively forming an oxidation-resistant insulating film on the main surface of the semiconductor substrate; 1. A method for manufacturing a vertical semiconductor device having a groove, comprising the steps of: oxidizing a semiconductor substrate through an opening in an insulating film to form an oxide film; and removing the oxide film by etching. 2. A step of selectively forming an oxidation-resistant insulating film on the main surface of a semiconductor substrate of one conductivity type, and selectively oxidizing the semiconductor substrate through the opening of the oxidation-resistant insulating film to form an oxide film. selectively forming a first semiconductor layer of an opposite conductivity type on the surface of the semiconductor substrate surrounded by the oxide film, and a second semiconductor layer of one conductivity type within the first semiconductor layer; a step of etching the oxide film to form a groove having a smooth outline; a step of forming an insulating film on the surface of the groove; and at least the first and second semiconductor layers on the insulating film. 2. The method of manufacturing a vertical semiconductor device according to claim 1, further comprising the step of forming an electrode film so as to partially overlap the electrode film. 3. A patent claim characterized in that the step of selectively oxidizing the semiconductor substrate through the opening of the oxidation-resistant insulating film to form an oxide film, and the step of removing this oxide film by etching are repeatedly performed. A method for manufacturing a vertical semiconductor device according to scope 1 or 2. 4. Before forming the oxidation-resistant insulating film, a first semiconductor layer and a second semiconductor layer are formed on the main surface of the semiconductor substrate, and then the semiconductor substrate is oxidized through the opening of the oxidation-resistant insulating film. The semiconductor body was previously etched through this opening and the V
Claim 1 characterized in that a letter-shaped groove is formed.
A method of manufacturing the vertical semiconductor device described above.