JPS62115574A - Parallel wiring system - Google Patents

Abstract

PURPOSE:To carry out a wiring processing in parallel and at high speed by dividing a wiring object surface into plurals, providing computers carrying out the wiring processing in the division every division and controlling them by a host computer. CONSTITUTION:The host computer 1 divides a wiring area 10 according to the number of cells 2-1-2-n. Then, the host computer 1 feeds wiring information of the division to which the respective cells are assigned to the respective cells 2-1-2-n. Here, the cell is a computer having a communication function with an adjacent computer. The host computer 1 instructs the wiring with respect to the respective cells 2-1-2-n. According to the wiring instruction, the respective cells simultaneously start the wiring and return the result of the wiring processing to the host computer 1. The host computer receives the wiring result from the respective cells 2-1-2-n and when the wiring is not completed, assign the division of the wiring again.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Actions Embodiments (1) Structure of an Embodiment (2) 1 Operation of the Embodiments Effects of the Invention [Summary] When forming circuit patterns on an LSI or a printed wiring board, the electronic circuit divides the circuit pattern forming surface into a plurality of sections and processes the wiring within each section for each section. Allocate computers, first process the parts that can be wired in each section in parallel using these computers, then create sets of multiple adjacent sections, assign a computer to each group, and perform wiring within these same groups. The possible parts are processed in parallel, and then a larger processing area is formed using multiple adjacent pairs, and electronic computers are assigned to this. Parts that can be wired within each processing area are processed in parallel. These steps are performed sequentially, and finally the host computer performs wiring processing.

[Industrial application field]

The present invention relates to a parallel wiring method, and in particular to a method in which wiring processing of circuit patterns of LSIs and printed wiring boards is performed in parallel and at high speed using a plurality of computers.

[Conventional technology]

For example, when wiring between connection points on a VLSI or printed wiring board, a processor is used to perform the wiring. One example will be explained with reference to FIG.

In FIG. 6(a), connection points Pa-Pn on the printed wiring board 30 where wiring prohibited areas 31 and 32 exist, and P
Po-Pa', Pl-PI between a' and Pn'
When wiring between the same subscripts, such as ', first draw a line horizontally from the connection point P o SP o ',
Then, a vertical line is drawn with respect to this horizontal line to perform wiring processing between the connection points Pa and Pa'. These line segments are not created in areas where wiring is prohibited, but are drawn by searching for empty areas. The wiring data thus obtained is held in memory.

Next, from the connection points P+ and P+', similarly search for an empty area and draw a line molecule ls AI' in the horizontal direction. These line segments 11, line segments 1z-r in the direction perpendicular to AI',
1z−z− and β2−1゛,! ! Subtract 2-2'-.

Then, by drawing a horizontal line segment β3 perpendicularly to these line segments, a connection route is created, thus wiring between connection points P1 and Pt' can be performed, and the wiring data obtained in this way to be kept in memory.

Draw a line horizontally or vertically from the connection point like this,
By alternately repeating the process of drawing line segments at right angles to this line while searching for empty areas, a connection route is detected, and connection points P2-Pz', ---Pn-Pn' are sequentially routed. become.

[Problem that the invention seeks to solve]

Conventionally, the process as explained in FIG.
Wiring processing was performed by generating line segments one by one. However, with this automatic wiring method, processing is performed sequentially on a normal computer, so as circuits become more highly integrated and complex, it has become difficult to guarantee sufficient speed and performance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a wiring method that can perform wiring processes between two points in a short time when a large number of wiring processes are performed.

[Means for solving problems]

In order to achieve the above object, in the present invention, as shown in FIG. 1, a surface to be wired, for example, a printed wiring board M, is divided into a plurality of sections A to H, and wiring processing within that section is performed for each section. Computers CMP 1 to CMP 8 are provided, and each of these computers CMP 1 to CMP 8 is controlled by a host computer CMPO.

[Effect]

As shown in Figure 1, the connection points ■-■, ■-■, ■-■, ■
When processing the wiring between -■ and Let it work, first,
Wiring processing is performed between ■-■, ■-■, ■-■, and ■-■ using a method such as line segment generation processing. Next, the host computer CMpo divides the computers CMP 3, CMP 4, CMP into one medium partition by dividing the partitions C, D, , G, and H into one medium partition.
7. One of the CMP8s, for example, the connection point for CMP3 ■
- Process wiring for ■. Data necessary for this purpose is sent from the host computer CMPO to the computer CMP3.

In this way, computers can be operated in parallel to perform wiring processing at high speed.

〔Example〕

(1) Configuration of one embodiment The configuration of an embodiment of the present invention will be explained based on FIG.

In FIG. 2, 1 is a host computer, 2 is a computer (hereinafter referred to as a cell) having a communication function with an adjacent computer, and in this example, 2-1 to 2-n cells are used. 10 is a wiring area such as an LSI or a printed circuit board.

The host computer 1 manages and controls the status of each cell 2-1 to 2-n, and provides each cell with wiring information such as connection points and areas where wiring is prohibited.

Cell 2 has communication path 20 between adjacent cells and communication path 2 between hosts.
1 are provided, and these are used to communicate with adjacent cells and host computers.

Of course, the host computer and each cell are provided with a processor and memory.

(2) Operation of one embodiment The operation of the configuration of one embodiment of the present invention shown in FIG. 2 will be explained based on FIGS. 3 to 5.

FIG. 3 is a flowchart explaining the operation of the host computer 1, FIG. 4 is a flowchart explaining the operation of the cell, and FIG. 5 is a diagram explaining a specific wiring process.

■The host computer 1 connects the wiring area 10 to cells 2-1 to
Divide this according to the number 2-n. Initially this cell 2
−1 to 2−n, that is, the wiring area 10 is divided into sections A,
Divide into n into B, C-, and N.

(2) Next, the host computer 1 sends to each of the cells 2-1 to 2-n the wiring information of the section to which each cell is assigned. That is, cell 2-1 has section A, cell 2-2 has section B, cell 2-3 has section C, cell 2-4 has section E, cell 2-5 has section E, and cell 2-3 has section C. 6 is assigned division F, and cells 2-7, 2-8, 2-9, 2-10, 2-
11=...2-n are the classifications G, H,,I S
-N is assigned to J. The host computer 1 is
For each cell 2-1.2-2-/2-n, data on the connection point and its connection destination within each allocation division,
Send wiring information such as areas where wiring is prohibited.

(2) The host computer] instructs wiring for each cell 2-1 to 2-n.

(2) Based on the wiring instructions from the host computer 1, each of the cells 2-1 to 2-n starts wiring at the same time. For this purpose, the wiring information received from the host computer 1 is first read out from the memory, and wiring processing is performed for those that can be wired within each section. Then, the results of the wiring processing performed in this manner are sent back to the host computer 1.

(2) The host computer 1 receives the wiring results from each of the cells 2-1 to 2-n. The process is finished when all the wiring is completed, but if the wiring is not completed, then the wiring classification is reallocated.

For example, when it is determined that the wiring between sections A, B, C, and D should be treated as one middle section in Figure 2 (C1), the sections A, B, C, and D should be connected as one middle section. One cell of the partition as a partition, e.g. cell 2-1
The wiring information of this medium division is sent to. Of course, such medium partitions are also formed in other parts of the wiring region 10 and cells are allocated to them. The cell 2-1 to which this middle division has been assigned performs the wiring process based on the flow shown in FIG. Based on the wiring processing report for each medium section, if the wiring is not completed, the host computer 1 determines a larger section, for example, a large section indicated by LL in FIG. 2(C), and performs the same wiring processing. Finally, if necessary, the wiring area 10 is treated as one section and wiring processing is performed in the same manner.

Of course, if it cannot be divided, the wiring process ends.

The connection point ■- shown in Figure 5 explains what was explained in the above ■~■
The case of wiring between ■, ■-■, ■-■-, and ■-■ will be explained.

(2) First, as shown in FIG. 5(a), the data of each connection point (2)-(2), (2)-(2)--, (2)--(2) in the wiring area 15 is stored in the host computer.

(2) The host computer divides the wiring area 15 into four in this example according to the number of cells, and divides each cell into 16, 17, .
Assign 18.19. Then, wiring information such as the position of the connection point is sent to each cell.

0th order, each cell performs wiring processing in parallel within each section 16, 17, 18, 19 assigned to each cell. As a result, connection points ■-■ are wired in section 16, ■--■ are wired in section 17, ■--■ are wired in section 18, and ■--■ and ■-■ are wired in section 19, respectively.

- Upon receiving reports of these wiring results, the host computer detects the positions of connection points where wiring has not been completed, and then determines that the entire wiring area 15 should be processed as one section for wiring, and then connects the wiring to appropriate cells. The remaining wiring information is sent to perform wiring processing. In this way, the wiring process can be completed as shown in FIG. 5 (dl).

Note that for long wiring spanning multiple sections, wiring routes can be searched in parallel using the inter-cell communication function.

〔Effect of the invention〕

According to the present invention, since wiring processing is performed using a plurality of computers, the wiring processing of the pattern can be performed in parallel and at high speed.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention. FIG. 2 is a configuration diagram of an embodiment of the present invention. FIG. 3 is an explanatory diagram of the operation of the host computer in the present invention. FIG. 4 is an explanatory diagram of the operation of the cell in the present invention. , FIG. 5 is an explanatory diagram of wiring processing in the present invention, and FIG. 6 is an explanatory diagram of conventional wiring processing. 1.-Host computer 2-.Cell 10--Wiring area 20-.--Communication path between adjacent cells 21.--Communication path between hosts

Claims (1)

[Claims] A wiring method in which a computer is used to perform wiring processing between a plurality of connection points, comprising: providing a plurality of cell computers (2) and a host computer (1) for managing these cell computers; The wiring information necessary for processing is given from the host computer to the cell computer, and the wiring area is first divided into multiple sections, a cell computer is assigned to perform the wiring processing for each section, and the wiring that can be connected within each section is assigned to each section. A parallel wiring method characterized in that a cell computer that performs processing performs wiring processing in parallel, and then performs wiring processing that can be connected in an area constituted by a plurality of sections.