JPH0620010A - Method and device for automatic wiring - Google Patents

Abstract

PURPOSE:To attain the automatic wiring at a high speed and with high quality with an automatic wiring device/method which automatically design the wirings on a multi-layer printed board and an integrated circuit like an LSI, etc., with use of a computer. CONSTITUTION:An initializing part 11 sets the initial value of the load coefficient used for calculation of the wiring cost and the prescribed value used for decision of the cross number. A route searching part 12 searches where the cross is recognized between the different wirings of signals. Then a cross number processing part 13 and a load coefficient changing part 16 compares the largest cross number or the sum total of cross numbers with the prescribed value and change the load coefficient respectively. Thus the routes where the cross number is reduced are repetitively searched. Then a layer assigning part 17 assigns the wiring patterns having the crosses to other layers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is applicable to printed circuit boards and LSs.
The present invention relates to an automatic wiring device and method for automatically designing wiring on an integrated circuit such as I using a computer.

With the recent increase in the packaging density of printed circuit boards, LSIs, etc., higher performance of DA systems is required. Also in the layout design, the reduction of the wiring rate and the increase of the processing time have become problems in the wiring processing of the ultra high density substrate.

Further, a system using such a substrate is required to have a high speed, and a propagation time of an electric signal passing on a wiring pattern of the substrate is required to be shortened. Therefore, there is a demand for a technique for efficiently and automatically wiring a pattern having a short wiring length or a pattern having a small number of vias.

[0004]

2. Description of the Related Art As a method for realizing a high wiring rate, for example, there is an "automatic wiring method" disclosed in JP-A-1-137373. In this method, it is possible to achieve a high wiring rate by recognizing intersections between patterns having different signals in the middle of wiring and gradually reducing the number of intersections.

That is, in this method, after performing the wiring process by recognizing the crossing of the wiring patterns, the wiring process is repeatedly performed so as to eliminate the crossing, thereby minimizing the total wiring cost and reducing the automatic wiring rate. Is intended to improve. That is, the following configuration is adopted.

The wiring cost including the intersection of the paths corresponding to the predetermined load coefficient is calculated, and the path with the smaller wiring cost is searched. If there is a net that intersects on the path searched by this path search, the fact that it is notified is changed, the initially specified load coefficient is changed, and a path that reduces the wiring cost is repeatedly searched based on the load coefficient.

[0007]

[Problems to be Solved by the Invention] The above "automatic wiring system"
Then, it is necessary to record the intersection between wiring patterns with different signals. Therefore, especially when processing a multi-layer substrate, the amount of temporary data required during path search becomes very large. Therefore, when processing a multi-layer substrate, it is more realistic to make several layers into one set and perform the processing for each set.

However, when the processing is performed for each set in this way, the optimization of the wiring pattern is performed only between the layers combined in each set. Therefore, when the quality of the wiring pattern is evaluated in all layers, There is a problem that the length and the number of vias are not always optimized.

Further, the "automatic wiring system" often requires a processing time as compared with other automatic wiring systems, and in particular,
When the number of layers is large, there is a large number of sets for each layer to be processed, and there is a problem that the processing time required to process all layers also increases.

It is an object of the present invention to solve the above problems and further improve the above automatic wiring system to provide an automatic wiring technique suitable for wiring a multilayer substrate.

[0011]

FIG. 1 is a diagram for explaining the principle of the present invention. The processing device 10 is a device that includes a CPU, a memory, and the like, and determines the route of the wiring section based on the number of layers, terminal coordinates, and a netlist having net information.

The initialization unit 11 is a processing means for performing initialization for wiring processing, and in particular, processing for setting an initial value of a load coefficient used for calculation of wiring cost and a predetermined value used for determination processing of the number of intersections. Is to do. Path search unit 12
Is a processing means for calculating the cost of the wiring including the intersection of the paths based on the set load coefficient and searching for the path with the smaller wiring cost.

The intersection number processing section 13 comprises an intersection message transmission section 14 and an intersection number determination section 15. If there is an intersection between different nets in the route searched by the route search unit 12, the intersection message transmission unit 14 sends the maximum value of the number of intersections or the sum of the maximum values of the number of intersections in each layer to the intersection number determination unit 15. Tell. The intersection number determination unit 15 determines whether the maximum value of the number of intersections transmitted by the intersection message transmission unit 14 or the sum of the maximum values of the number of intersections in each layer is the initialization unit 1
If it is smaller than the predetermined value set by 1,
The obtained path is sent to the layer allocator 17. When it is larger, the load coefficient changing unit 16 is notified of the number of intersections and the route searching unit 12 is notified to perform the route search.

The load coefficient changing unit 16 is a processing means for changing the load coefficient and notifying the route searching unit 12 when the maximum value of the number of intersections or the sum of the maximum values of the number of intersections in each layer is larger than a predetermined value. .

The layer allocating unit 17 performs a process of allocating a path of a net having an intersection to each of the other layers when the maximum value of the number of intersections or the total value of the maximum values of the number of intersections in each layer becomes equal to or less than a predetermined value. It is a means.

By the judgment of the number-of-intersections processing unit 13, the load coefficient is changed until the maximum value of the number of intersections or the total of the maximum values of the number of intersections in each layer becomes equal to or less than a predetermined value.
Repeat the path search by.

These are processed as follows. When the number of layers that can be used for wiring is L (L ≧ 3), the load coefficient changing unit 16 changes the load coefficient for an n layer smaller than L while crossing wiring patterns having different signals. Accept and search the path of the wiring. The maximum value of the number of intersections in each layer of the path obtained by this search is set to C _i (i = 1,
2, ..., N), the search by the path search unit 12 is repeated until each of these maximum values C _i becomes equal to or less than a predetermined value. That is, when the predetermined value is V, the wiring path is searched until C _i ≤V.

Further, not only the maximum values C _i individually become equal to or less than a predetermined value, but also the total sum (C ₁ + C ₂ + ... + C _n ) of the maximum values C _i of the number of intersections in each layer of the path obtained by the search.
By determining whether is below a predetermined value,
The process of searching the wiring path is repeated until the total sum of the maximum values C _i of the number of intersections in each layer becomes equal to or less than a predetermined value.
Thus, in some of the total number of layers that can be used for wiring, the number of intersections is reduced until the sum of the maximum number of intersections in each layer is less than or equal to the total number of layers, and then the wiring is not used. The wiring process is completed by allocating wiring patterns with intersections to the remaining layers.

[0019]

In general, the wiring process is performed by dividing each layer in which the wiring is executed into a grid pattern. Finally, only one signal line wiring pattern can be placed in this grid. In the "automatic wiring method" disclosed in Japanese Patent Laid-Open No. 1-137373, the intersection of wiring patterns of different signal lines is recognized in the course of wiring. Therefore, in the course of wiring, a wiring pattern of a plurality of signal lines may exist in one lattice of a certain layer. The number of different signal lines existing in one grid is called the number of intersections.

In the present invention, the problem to be wired is wired with the number of layers smaller than the total number of layers. In this wiring process, the above-mentioned "automatic wiring method" is applied until the total sum of the maximum numbers of intersections in each layer becomes equal to or less than the total number of layers. Then, a wiring pattern having intersections as much as possible is assigned to the remaining layers that are not targeted during the wiring processing. Specifically, it is as follows.

Let L be the number of layers available for a given wiring problem.
(L ≧ 3), the number of layers to which the above “automatic wiring method” is applied is n
(N = 1, 2, ...; N <L). The maximum value of the number of intersections in each layer to which the above “automatic wiring method” is applied is C _i (i
= 1, 2, ..., N) so that C _i is equal to or less than a predetermined value V. Further, the above "automatic wiring method" is executed until the condition of C ₁ + C ₂ + ... + C _n ≤L is satisfied. After this, the intersection remains (C ₁ + C ₂ + ... + C _n −n)
The wiring pattern of the book does not exist (L-
n) Allocate to layers, and finally obtain a pattern without intersections in all layers.

As described above, C ₁ + C ₂ + ... + C _n ≤L
The wiring pattern is optimized until the condition of is satisfied. Therefore, as compared with the case where the wiring problem is simply divided into several layers and the above-mentioned "automatic wiring method" is applied, the wiring pattern is optimized over all layers.

Consider the processing time when the wiring problem is divided into several layers and applied to the above-mentioned "automatic wiring method". The number of sets is m, and the number of layers in each set is l _i (i = 1, 2,
, M; provided that l _i ≧ 0, l ₁ + l ₂ + ... + l _m = L)
And At this time, if the time required to process a certain set i is t _i , the time required to complete the wiring for all layers is t ₁ + t ₂ + ... + t _m . On the other hand, when the processing time according to the present invention is T and the wiring process is performed with the number of layers l _i , T ≦ t _i . Therefore, T ≦ t ₁ + t ₂ +
.. + t _m , the present invention is also advantageous in terms of processing time.

[0024]

FIG. 2 is a processing flowchart of an embodiment of the present invention. Hereinafter, an example of the processing of each unit illustrated in FIG. 1 will be described in accordance with the processing illustrated in FIG.

In the pre-processing, the initialization unit 11 converts the given netlist (terminal information or net information) into a format processed by the path search unit 12, or the path search unit 12 calculates the wiring cost. The load coefficient used for this purpose is initialized. Further, the intersection number determination unit 15 also sets a value used for comparison with the intersection number.

The path searching unit 12 calculates the wiring cost by using the load coefficient currently set, and searches and generates the path in which the wiring cost becomes small. By the crossing message transmission unit 14, the path search unit 12
The maximum value of the number of intersections between different nets in the path generated by is obtained, and the number of intersections determination unit 15 is notified.

The intersection number determination unit 15 determines whether or not the maximum value of the number of intersections between different nets is less than or equal to a predetermined set value, and if this condition is satisfied, the process proceeds to the next layer allocation process. . If not, the load coefficient changing unit 16 is notified of the number of intersections, and the path search processing is repeated again.

The load coefficient changing unit 16 determines whether or not to change the load coefficient (used in the route search process) that is the basis for calculating the wiring cost according to the number of intersections notified from the intersection number determining unit 15, and Change the load factor as needed.

By the layer allocating unit 17, the intersection number determining unit 1
Allocate the paths of the nets that have intersections in the paths received from 5 to each layer. If the intersection remains after the allocation, a new netlist is created based on the data of the layer and is passed to the initialization unit 11. At this time, the wiring pattern data of the layer to be modified and the number of layers are also passed. As a method of allocating a wiring pattern to each layer, a method of allocating so that the number of intersections in each layer is even, or a method of minimizing the number of layers without intersections can be considered. When there is no intersection in all layers, the next process is the ending process.

In the termination process, the obtained path information is extracted and output. In the search in the path search process, wiring is performed in the middle of the wiring in which the intersection between wiring patterns having different signals is recognized. In the processing, for example, the technique of "automatic wiring system" disclosed in the above-mentioned Japanese Patent Laid-Open No. 1-137373 is used. The specific processing contents will be described according to the examples shown in FIGS.

The intersections of the wiring patterns include cross crosses in which the patterns intersect in a cross shape and overlaps in which the paths are overlapped in parallel. Cross cross is generally difficult to avoid because it must bypass the other terminal, while overlap can be easily avoided by translating any of the paths. In many cases.

The path searching unit 12 shown in FIG. 1 searches for a path in which the wiring (net) between designated terminal coordinates has the minimum wiring cost under the set load coefficient. However, this wiring cost is calculated by the cost function f shown in the following expression, for example.

F = α × wiring length + β × via number + γ × cross cross number + δ × overlap number where α, β, γ, and δ represent load factors for each element, and the wiring length is the total wiring of the net. The length (total path length), the number of vias is the number of via holes for changing the wiring layer, the number of crosses is the number of paths crossing in a cross, and the number of overlaps is the number of paths overlapping in parallel.

Initially, the load coefficient γ for the cross cross is initialized to 0 and the load coefficient δ for the overlap is initialized to 0, and a path that minimizes the wiring cost is searched for in a mode in which the cross is recognized.

For example, as shown in FIG. 3A, wiring (net) connecting terminals AA, BB, and CC.
W _A, W _B, the W _C shall be performed in this order. A path is searched with load factors γ = 0 and δ = 0, the above cost function f is calculated, and the minimum wiring cost is found.
As a result, for example, a wiring pattern as shown in FIG. 3B can be obtained. Here, because of the wiring order, the net W _A
However, it crosses the nets W _B and W _C , and the net W
It is assumed that _C crosses the net W _B. φ is an empty set and represents that there are no crosses or overlapping nets.

In order to avoid this cross as much as possible, the load coefficient γ is changed to a positive value (for example, γ = 1),
Similarly, the search is repeated. As a result, a wiring pattern as shown in FIG. 4A is obtained. In this wiring, the cross cross is eliminated, but the net W _B overlaps with the net W _A.

In order to perform a path search for avoiding overlap, further load coefficients are set to γ = 1 and δ = 1 and are substituted into the cost function f to search a path with a small wiring cost. A wiring pattern as shown in (b) is obtained.

As shown in FIG. 4B, there is no problem if a wiring pattern having no intersection can be obtained. However, in general, an intersection remains, and a path search for minimizing the intersection is possible. It takes a very long processing time.

In the present invention, this processing is performed until the maximum value of the number of intersections for each layer or the sum of the maximum values of the number of intersections in each layer becomes smaller than a predetermined value. Since it is shifted to the allocation processing to, it is possible to reduce the particularly time-consuming search processing part.

FIGS. 5 and 6 are wiring example explanatory diagrams showing an example in which the present invention is applied to the problem of all four layers. Circles in the figure represent terminals. First, among the four layers of all layers, the wiring which has been recognized as intersecting is performed on the first layer and the second layer by the path search. At this time, the optimization of the wiring pattern is performed until the sum of the maximum values of the number of intersections in each layer becomes 4.

The result is the wiring pattern shown in FIG. In the figure, the solid line wiring pattern represents the wiring pattern in the first layer, and the dotted line wiring pattern represents the wiring pattern in the second layer. There is an intersection at and in the figure. Here, for example, if the wiring patterns of P1 and P2 can be allocated to the other two layers, it means that the wiring has been completed without any wiring.

Therefore, the wiring patterns P1 and P2 shown in FIG. 5A are transferred to the third layer and the fourth layer, respectively. As a result, the wiring patterns of the first layer and the second layer have no intersection as shown in FIG. 5B.
FIG. 6A shows the wiring pattern in the third layer resulting from this processing, and FIG. 6B shows the wiring pattern in the fourth layer.

That is, (B) of FIG. 5 and (A) and (B) of FIG. 6 show the state where the wiring is completed. The wiring pattern to be assigned to the other remaining layers in each layer after wiring to some of the layers is selected by the following procedure, for example.

(1) Select the net having the smallest number of terminals among the nets where the wiring patterns intersect. (2) If there are multiple terminals with the smallest number of terminals, select the one with the smallest wire length. (3) If there are multiple wires with the smallest wire length, select the one with the terminal coordinates closest to the origin. Or the x coordinate is the minimum,
It is conceivable to select using the condition that the y coordinate is the smallest.

In the example shown in FIG. 5A, the wiring pattern of P1 is the above
It is selected because it corresponds to (1). As for the wiring patterns intersecting with each other, since both the intersecting patterns satisfy the above condition (1), the following condition (2) is examined, and the wiring pattern of P2 is selected.

[0046]

As described above, according to the present invention,
When automatically wiring ultra-high-density multilayer printed circuit boards, etc., it is possible to perform high-speed and high-quality wiring compared to the conventional method of processing several layers at a time.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a processing flowchart of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a path search according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram of a path search according to the embodiment of the present invention.

FIG. 5 is an explanatory diagram of a wiring example according to the embodiment of the present invention.

FIG. 6 is an explanatory diagram of a wiring example according to the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 processor 11 initialization part 12 path search part 13 crossing number processing part 14 crossing message transmitting part 15 crossing number judging part 16 load factor changing part 17 layer allocation part

Claims (4)

[Claims] 1. An automatic wiring apparatus for determining a route of a wiring section by a computer, wherein an initialization unit (11) for setting an initial value of a load coefficient used for calculation of a wiring cost and a predetermined value used for determining the number of intersections.
Based on the set load coefficient, the cost of the wiring including the intersection of the routes is calculated, and the route search unit (12) that searches for the route with the smaller wiring cost, and the route searched by the route search unit. When there is an intersection between different nets, the intersection number processing for comparing the maximum value of the number of intersections or the sum of the maximum values of the number of intersections in each layer with a predetermined value used for the determination processing of the number of intersections set by the initialization unit Section (13) and a load coefficient changing section (16) for changing the load coefficient and notifying the path search section when the maximum value of the number of intersections or the sum of the maximum values of the number of intersections in each layer is larger than a predetermined value. A layer allocation unit (17) that performs processing for allocating the path of a net having an intersection to each other layer if the maximum value of the number of intersections or the maximum value of the number of intersections in each layer becomes less than a predetermined value. ， Maximum number of intersections or The sum of the maximum value of the number of intersections in the layers by changing the load factor decreased below a predetermined value, an automatic wiring device which is characterized in that so as to repeat the path search by the route search unit. 2. An automatic wiring method in which wiring is carried out by a computer for three or more layers, and when the number of layers usable for wiring is L (L ≧ 3), for n layers smaller than L, The process of searching the path of the wiring pattern in the state where the intersection between the wiring patterns having different signals is recognized, and the maximum value of the number of intersections in each layer of the path obtained by the search is C _i (i = 1, 2, ... , N), a process of determining whether or not each of these maximum values C _i has become a predetermined value or less, and wiring until the maximum value C _{i of the} number of intersections in each layer becomes a predetermined value or less. An automatic wiring method characterized in that the process of searching the path of is repeated. 3. An automatic wiring method in which wiring is performed for three or more layers by a computer, and when the number of layers usable for wiring is L (L ≧ 3), for n layers smaller than L, The process of searching the path of the wiring pattern in the state where the intersection between the wiring patterns having different signals is recognized, and the maximum value of the number of intersections in each layer of the path obtained by the search is C _i (i = 1, 2, ... , N), a process of determining whether the sum (C ₁ + C ₂ + ... + C _n ) of the respective maximum values C _i is less than or equal to a predetermined value, and the maximum number of intersections in each layer. An automatic wiring method, characterized in that the process of searching a wiring path is repeated until the total sum of the values C _i becomes a predetermined value or less. 4. The automatic wiring method according to claim 2 or 3, wherein the sum of the maximum values of the number of intersections in each layer is less than or equal to the total number of layers in some of the total number of layers that can be used for wiring. The automatic wiring method is characterized in that the wiring process is completed by reducing the number of crossing until the number becomes, and then allocating the wiring pattern having the crossing to the remaining layers not used for wiring.