JPH06266801A - Logical synthesis method considering floor plan - Google Patents

Abstract

PURPOSE:To easily obtain a logically synthesized result matched with a final loading format and the purpose of performance at the initial time of logical synthesis and to reduce the backword operation of a design process as less as possible by executing logical synthesis considering a floor plan. CONSTITUTION:Temporary floor plan information 42 is prepared from the function level specification 41 of a logical device, inter-block approximate wiring information 46 is prepared based upon the information 42 and the line length of a network laid among blocks is estimated from the information 46 to prepare inter-block network line length information 43. Then constraint information 44 is prepared based upon the information 43. A logical synthesis means 9 prepares the gate level specification 45 of this logical device from the specification 41 by a method for using a high power gate having high driving capacity as the output side gate of a network laid among blocks and having a long line length so that the information 44 is satisfied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the design of logic devices such as LSIs and PCBs, and in particular, creates a temporary floor plan from the functional level specifications of the logic device to be designed, and considers the created floor plan. The present invention relates to a logic synthesis method in consideration of a floor plan, in which a gate level specification is created by logic synthesis.

[0002]

2. Description of the Related Art Conventionally, LSI and PCB are manufactured by logic synthesis.
When designing a logic device such as, for example, the functional level specifications of the logic device to be designed that was created in the function design stage (what kind of functional block the logic device is composed of Gate level specifications (level specifications in units of logic gates such as inverters and flip-flops) are generated by logic synthesis from information indicating how they are connected by lines), and then layout design (floor It is generally adopted to carry out (including plan design), and to evaluate the delay and the like, and if there is a problem, go back to the logic synthesis process or layout design process and redesign again.

In particular, depending on the shape and location of each block constituting the logic device determined by the layout design, that is, the floor plan, a net connecting blocks that are far apart from each other may occur. Since the line length is long, the signal propagation delay time may not satisfy the delay constraint of the net. Even in such a case, conventionally, when it is found by delay evaluation, the output side gate of the net generated by logic synthesis is replaced with a high power gate with high driving capability, or a high output buffer is newly inserted. We are dealing with it by changing the design.

[0004]

L according to the logic synthesis method
In SI and PCB design, process return such as returning to the previous process and redesigning cannot be avoided to some extent, but when process return occurs frequently or the amount of work to be performed in the returned process increases. Increases the design time and increases the risk of human error.

For this reason, the number of process returns is as small as possible, but in the past, since the floor plan was created for the first time after performing logic synthesis, the shape of the block obtained by the floor plan and the location of the block can be obtained. Cannot be used for logic synthesis.Therefore, as described above, there is a high probability that there will be a backtrack in the process of replacing the output side gate of the path that violates the delay constraint with a high power gate with high driving capability, which will take a long This is one of the causes of humanization and human error.

Therefore, an object of the present invention is to create a tentative floor plan from the functional level specifications of the logic device to be designed, and create a gate level specification by logic synthesis in consideration of the created floor plan. As a result, it is possible to take measures such as configuring the output side gate of the net that spans distant blocks with high-power gates with high driving capability at the time of the first logic synthesis, and to minimize the backtracking of the process in logic device design. It is to provide a logic synthesis method that takes into consideration the floor plan.

[0007]

In order to achieve the above-mentioned object, the present invention creates a temporary floor plan of the logical device from the function level specifications of the logical device to be logically synthesized, and creates the temporary floor plan. The rough wiring route between the blocks forming the logical device is determined based on the floor plan of the above, and the line length of the net spanning the blocks forming the logical device is estimated based on the determined rough wiring route, and the estimation is performed. The constraint information at the time of logic synthesis is set based on the line length of the net, and the set constraint information is taken into consideration to perform the logic synthesis to specify the gate level specifications from the function level specifications of the logic device to be the logic synthesis target. I am trying to generate.

[0008]

Originally, the floor plan of a logic device can be accurately performed only after the gate level specifications of each block constituting the logic device are determined, but a skilled designer can use the floor plan of each logic device based on many years of experience. It is possible to create a required shape and location for each block, that is, a floor plan with a certain degree of accuracy, from the specifications of the functional level of the block. Similarly, the line length of the net that spans between blocks cannot be accurately performed until after the layout is completed, but if a floorplan is created as described above, a skilled designer can position the I / O terminals of each block. So you can guess
If the wiring path connecting the estimated input / output terminals is determined and this wiring path length is set to an approximate value of the line length of the net extending between the blocks, the prediction can be performed with a certain degree of accuracy.

The present invention has been made paying attention to such a point. First, a tentative floor plan is created from the specification of the function level of the logic device, and then the inter-block is designed based on this tentative floor plan. By determining the rough wiring route of, and estimating the line length of the net spanning the blocks from this rough wiring route, and performing logic synthesis under the constraint information set based on the estimated line length of the net, A logic synthesis that takes floorplan into consideration, such as automatically generating a high power gate with high driving capability as an output side gate of a net with a long line length that spans between blocks so that floor synthesis is considered. Is.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings.

Referring to FIG. 1, an example of an apparatus used to implement a logic synthesis method in consideration of a floor plan of the present invention is a graphic display 1, a keyboard 2, and
A mouse 3, a storage device 4, a block diagram creating means 5,
Floor plan creating means 6 and inter-block schematic wiring means 1
1, an inter-block net line length calculation means 7, a constraint information generation means 8, a logic synthesis means 9, and a signal line 10 interconnecting these. Each means 5-9,11
Is realized by various programs executed on the central processing unit constituting the EWS, for example, and the storage device 4 is constituted by its main storage device or auxiliary storage device.

The block diagram creating means 5 is a means for providing an environment in which a designer can create a function level specification of a logical device to be designed on the screen of the graphic display 1 by operating the keyboard 2 and the mouse 3. It is a kind of editor. The information created by using the block diagram creating means 5 is stored in the storage device 4 as the function level specification 41 of the logic device.

The floor plan creating means 6 is a means for providing an environment in which a designer can create a floor plan of a logical device to be designed on the screen of the graphic display 1 by operating the keyboard 2 or the like, which is also a kind of It is an editor. The information created by using the floorplan creating means 6 is stored in the storage device 4 as the floorplan information 42 of the logical device.

The inter-block rough wiring means 11 is based on the floor plan information 42 and the temporary input / output terminal position information of each block inputted from the designer through the keyboard 2 and the like, and the rough wiring route between each block of the logic device. Is a means of seeking. The obtained route information is stored in the storage device 4 as the inter-block schematic wiring information 46.

The inter-block net line length calculating means 7 is a means for calculating the inter-block net line length based on the created inter-block schematic wiring information 46. The calculated result is stored in the storage device 4 as the inter-block net line length information 43.

The constraint information generating means 8 is means for generating constraint information at the time of logic synthesis based on the inter-block net line length information 43. The generated information is stored in the storage device 4 as constraint information 4
Stored as 4.

Under the constraint information 44, the logic synthesizing means 9
It is means for automatically generating the gate level specification of the logic device from the function level specification 41 of the logic device. The generated information is stored in the storage device 4 as the gate-level specification 45 of the logic device.

A logic synthesis method considering a floor plan according to this embodiment will be described below.

First, the designer activates the block diagram creating means 5 by operating the keyboard 2 or the like, and using this block diagram creating means 5, the function level specifications of the logic device to be designed are displayed on the graphic display 1. For example, create it on the upper half of the screen.

FIG. 2 is a functional block diagram showing an example of functional level specifications of the logic device created by the designer. The specifications of the function level of the logic device of this example are the specifications of the input terminal groups IN1, IN2, IN3 and a plurality of blocks BLK1, BLK2, REG that represent a certain logic group.
1, REG2, SEL1, SEL2 specifications, output terminal group OUT specifications, connection information PQ having a bit width for connecting the input / output terminal group to the blocks and the blocks to each other
(0:32), ABC (0:32), DEF (0: 3)
2), ABCX (0:32), DEFX (0:32),
RST (0:32), XYZ (0:32), GH (0:
32) and the specifications of OUT (0:32) (numerical values in parentheses indicate bit width).

When the designer finishes the specification of the function level of the logical device to be designed and gives an instruction to that effect with the mouse 3 or the like, the block diagram creating means 5 stores them in the storage device 4 as the functional level of the logical device. It is stored as the specification 41 of.

Next, the designer activates the floorplan creating means 6 by operating the keyboard 2 or the like, and using this floorplan creating means 6, the temporary floorplan of the logical device to be designed is displayed graphically. For example, it is created on the screen of the lower half of 1.

The floor plan is created by referring to the block diagram of FIG. 2 displayed on the screen, for example, the LSI substrate or the print displayed on the screen of the lower half of the graphic display 1 by the floor plan creating means 6. This can be proceeded by sequentially creating a figure showing the shape of each block forming the logic device in a frame showing the outer shape of the board.

FIG. 3 is a block B of the logic device shown in FIG.
LK1, BLK2, REG1, REG2, SEL1, S
An example of a provisional floor plan at the time when the shape and the arrangement of EL2 are determined is shown.

Here, as described above, the floor plan of the logical device is such that the blocks BLK1, B constituting the logical device are
Unless the gate level specifications of LK2, REG1, REG2, SEL1, and SEL2 have been determined, the size of each block cannot be determined accurately, so it cannot be performed accurately. It is possible to determine the shape and placement location required for each block with a certain degree of accuracy from the specifications of the functional level of each block. That is, even in the logic design to which the method of the present invention is applied, it is necessary to create an accurate floor plan after logic synthesis, but a skilled designer can use a temporary floor plan similar to the floor plan created after logic synthesis. It is possible to create a floor plan, and there is no fear that logic synthesis will be performed in consideration of an irrelevant temporary floor plan.

When the designer finishes the creation of the temporary floor plan of the logical device to be designed and gives an instruction to that effect with the mouse 3 or the like, the floor plan creating means 6 stores it in the storage device 4 as the floor plan information 42. Store.

Next, the designer activates the inter-block schematic wiring means 11 by operating the keyboard 2 or the like. The activated inter-block rough wiring means 11 displays on the graphic display 1 a message prompting to input the position of the input / output terminal for each block in the floor plan.

In response to the prompt message, the designer designates the position of the input / output terminal of each block on the graphic display 1 by operating the mouse 3 or the like. At this stage, there is no layout information in the block, so
Although the positions of the input / output terminals for connecting the blocks cannot be determined exactly, a skilled designer can use FIG.
It is possible to roughly determine the position of the input / output terminal of the block from the connection relation and the positional relation of each block which are found in the floor plan as shown in FIG. 2 and the functional block diagram as shown in FIG.

FIG. 4 shows an example of the positions of the input / output terminals of each block designated by the designer. In the figure, i
1, i2 are input / output terminals used to connect the blocks BLK1 and BLK2, and i3 and i9 are block BLK
2 and the input / output terminal used to connect the block SEL2,
i4 and i6 are input / output terminals used for connecting the block REG1 and the block SEL1, and i5 and i7 are block RE.
Input / output terminals used to connect G2 and block SEL1, i8 and i10 are block SEL1 and block SEL
Input / output terminal used for connection with 2.

When the designer finishes designating the input / output terminals of each block, the inter-block rough wiring means 11 obtains a wiring path connecting the input / output terminals having a connection relationship, and the result is used as the inter-block rough wiring information 46. It is stored in the storage device 4. In the case of FIG. 4, the inter-block schematic wiring means 11 uses L1 as the wiring path between the input / output terminals i1 and i2, L2 as the wiring path between the input / output terminals i4 and i6, and the wiring between the input / output terminals i5 and i7. L3 is used as the path, and the input / output terminal i
L4 is used as a wiring path between the input terminals 3 and i9,
L5 is determined as a wiring route between i10. In this embodiment, the wiring route connecting the input and output terminals is automatically obtained, but the designer himself may draw the wiring route on the graphic display 1 to manually obtain the wiring route.

Next, the designer activates the inter-block net line length calculation means 7 by operating the keyboard 2 or the like. The activated inter-block net line length calculation means 7 inputs the inter-block schematic wiring information 46 stored in the storage device 4 and calculates the wiring length of each wiring route L1 to L5. Then, the obtained wiring lengths of the respective wiring paths L1 to L5 are stored in the storage device 4 as the inter-block net line length information 43 as the line length of the net between the blocks having the connection relationship.

After finishing the calculation of the line length of the net between the blocks, the designer next activates the constraint information generating means 8. The activated constraint information generation unit 8 inputs the inter-block net line length information 43 from the storage device 4, compares the net line length between the blocks with a preset limit value, and exceeds the limit value. For a net with a line length or a net that does not exceed the limit value but has a small margin, create constraint information indicating that logic synthesis is performed using a high power gate with high driving capability as the output side gate of the net, This is stored in the storage device 4 as the constraint information 44.

When the setting of the constraint information is completed, the designer activates the logic synthesizing means 9 by operating the keyboard 2 or the like.

The activated logic synthesizing means 9 is the storage device 4
From the logic device function level specification 41 and the constraint information 44 are input, the logic device function level specification 41 is generated from the logic device gate level specification, and the logic device gate level specification 45 is generated in the storage device 45. Store as.

At this time, the logic synthesizing means 9 checks whether or not the constraint information 44 includes constraint information about the net at the time of logically synthesizing each net of each block. Logically synthesize to satisfy information. Therefore, in the case of this embodiment, a high power gate having a high driving capability is logically synthesized as an output side gate of a net for which constraint information is set. A gate with standard capability is used as the output side gate of the net without such constraint information.

As described above, in this embodiment, the logic synthesis in consideration of the floor plan is enabled.

[0037]

As described above, according to the present invention, a tentative floor plan is created before logic synthesis, and then a schematic wiring route between blocks is determined from this tentative floor plan, and blocks are determined by the route length. Estimate the line length of the net spanning,
Then, since the logic synthesis is performed under the constraint information set based on the estimated line length of the net, it becomes possible to perform the logic synthesis in consideration of the floor plan. There is an effect that a measure such as configuring the output side gate with a high power gate having high driving capability can be achieved at the time of the first logic synthesis. As a result, logic synthesis suitable for the final mounting form and performance target can be performed from the beginning, and it is possible to minimize backtracking in the process of designing the logic device.

Further, in the present invention, the rough wiring route between the blocks is determined, and the line length of the net extending between the blocks is estimated based on the rough wiring route. Therefore, for example, the Manhattan length between the centers of gravity of the blocks is calculated as the net line. The line length of the net can be estimated more accurately than the method of setting the length.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of an apparatus used for implementing a logic synthesis method in consideration of a floor plan of the present invention.

FIG. 2 is a diagram showing an example of a functional block diagram expressing functional level specifications of a logical device to be designed.

FIG. 3 is a diagram showing an example of a temporary floor plan created.

FIG. 4 is an explanatory diagram of a schematic wiring path between blocks and a net line length between blocks.

[Explanation of symbols]

 1 ... Graphic display 2 ... Keyboard 3 ... Mouse 4 ... Storage device 41 ... Functional level specification of logic device 42 ... Floor plan information 43 ... Net line length information between blocks 44 ... Constraint information 45 ... Gate level specification of logic device 46 ... block-to-block schematic wiring information 5 ... block diagram creation means 6 ... floor plan creation means 7 ... inter-block net line length calculation means 8 ... constraint information generation means 9 ... logic synthesis means 10 ... signal line 11 ... block-to-block schematic wiring means

Claims (2)

[Claims] 1. A temporary floorplan of the logical device is created from specifications of a function level of the logical device to be logically synthesized, and an outline between blocks configuring the logical device is based on the created temporary floorplan. A wiring route is determined, a line length of a net that spans the blocks forming the logic device is estimated based on the determined rough wiring route, and constraint information at the time of logic synthesis is set based on the estimated line length of the net. A logic considering a floor plan, characterized in that the gate level specifications are generated from the function level specifications of the logic device to be logic-synthesized by considering the set constraint information. Synthesis method. 2. Constraint information is set for a net in which the line length of the net straddling between the blocks violates a preset limit value or a net with a small margin, and the net of the net is set according to the set constraint information. 2. The logic synthesis method according to claim 1, wherein a high power gate having a high driving capability is logically synthesized as the output side gate.