JPH05108753A - Logical simulation system - Google Patents

Abstract

PURPOSE:To improve simulation accuracy by realizing a more accurate propagation delay time again by updating the propagation delay time during the execution of a simulation. CONSTITUTION:In an event driven system describing the circuit structure of a gate instance C to be a simulation object within a simulator and performing the simulation of the gate instance C based on the describing content, the propagation delay time of the gate instance C is made into a function and the function is preliminarily stored in the simulator. During the execution of the simulation, the function is called every time an event occurs in the gate instance C, etc., the value of the propagation delay time is successively updated and the simulations of the gate instance C, etc., are performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation method using an event driven method in a digital circuit, and in particular, the addition of a propagation delay time to each gate instance (gate instance, a logic circuit to be simulated). It is about the method.

[0002]

2. Description of the Related Art Conventionally, this kind of logic simulation method has been described in the following documents, for example. References: Shige, Asada, Karatsu, "VLSI Design II" (1
985-5-10) Iwanami Shoten, P.P. 193-205 As described in the above document, the logic simulation method includes a compile method and an event driven method. The compile method is a method in which an instruction code corresponding to the operation is generated for each gate instance and the instruction code is executed in an appropriate order to obtain the value. Although this compilation method can be evaluated in terms of speeding up execution speed from the way of making it,
It lacks accuracy in the effects of delays, etc., and its application range is also limited. On the other hand, in the event driven method,
In this method, each gate instance is faithfully represented in the computer, including its connection relationship, and the simulation is performed based on that. In other words, in this event-driven method, the circuit structure of each gate instance, including its connection relationship, is described in a simulator composed of a computer, and the gate instance is simulated based on the description. ..

In simulation, we track how changes in input values propagate to the output. This signal value change is an event (event)
Say. Let V ₀ be the set of pairs of signal lines and signal values that change at the current point of time, and let V ₁ be the set of pairs of signal lines and signal values that change under the influence of V _0. The steps (i) to (vi) are performed.

(I) Prepare V _a and V _b , and a ← 0, b
← Set to 1. (Ii) Set the initial state value. (iii) Read the input value. The changed signal line and its value are registered in V _a . (Iv) If V _a is an empty set, return to (iii). (V) The value of V _a is simulated, and the changed signal line and its value are registered in V _b . (Vi) The roles of V _a and V _b are switched by setting a ← 1 and b ← 0. At this time, it is checked whether oscillation has occurred. If there is no oscillation, return to (iv).

Unlike the compilation method, the event driven method does not require leveling of the gate instance. Moreover, even if a loop exists in the circuit, it can be simulated as it is.

In the gate level simulation, the most important factor that determines the accuracy of the simulated circuit with respect to the actual circuit is the delay time of the gate instance. If this modeling is not suitable for the actual situation. Would lead to inaccuracies in the simulation of timing etc. As the delay, the propagation delay caused when the signal propagates in the gate instance is a problem.

The propagation delay time of each gate instance in the circuit for executing the event-driven simulation is determined by calculating its value in advance by some method and adding it to each instance before executing the simulation. It is being appreciated. Specific examples thereof are shown in FIGS.

FIG. 2 is a diagram showing an example of a circuit which is a target of the logic simulation, and FIG. 3 is an operation explanatory diagram thereof.

The circuit of FIG. 2 has a configuration in which a buffer gate B is connected to the output 3 of a 2-input OR gate A for obtaining the logical sum of the two inputs 1 and 2, and an output 4 is obtained. In FIG. 3 showing this operation, 1 and 2 are inputs, 3 and 4 are outputs, and t0 to t0.
t7 is time, and Δt1 to Δt6 are times.

The propagation delay time of the gate is usually a rising propagation delay time t _pd (LH) and a falling propagation delay time t _pd (H
L) and, but here, for simplification of description, t
_{Let pd} (LH) = t _pd (HL) = t _pd . The OR gate A and the buffer gate B are called gate instances A and B, respectively.

For example, the propagation delay time t _pd of the path from the input 1 to the output 3 of the gate instance A is t _pd (1 →
3), the propagation delay time t _pd of the path from the input 2 to the output 3 is t _pd (2 → 3). Also, the propagation delay time t _pd of the path from the input of the gate instance B to the output 4 is t _pd (3
→ 4), the operation shown in FIG. 3 is simulated by the following processes (i) to (vi).

(I) Gate instance A at time t0
An event that is a change in the signal value occurs at the input 1 of the. (Ii) Since the output 3 changes due to the event of (i), the event is scheduled at time t1 (= t0 + Δt1). (iii) At time t1, an event occurs at the input of the gate instance B, and the output 4 of the gate instance B is changed by this event. Therefore, at time t2 (= t1 +
The event is scheduled at Δt4). (Iv) The output 4 changes at time t2. (V) At time t3, an event occurs at input 2 of gate instance A, but this event is ignored because output 3 does not change accordingly. (Vi) At times t4, t5, ... After that, the same operation as described above is performed.

In the conventional simulation by such an event driven method, the propagation delay time t _pd (1 →
The values of 3), t _pd (2 → 3) and t _pd (3 → 4) were fixed. That is, time t _pd (1 → 3) = Δt1, t _pd (2 →
3) = Δt2 = Δt3, t _pd (3 → 4) = Δt4 = Δt
5 = Δt6.

[0014]

However, the conventional logic simulation method has the following problems. A circuit having a characteristic that the propagation delay time t _pd of the gate instances A, B, etc. changes with the progress of the simulation times t0, t1, ... (For example, the times Δt4, Δt5, Δt6 in FIG. 3 have different values. In the circuit), since the propagation delay time t _pd of each gate instance A and B is fixed, an error occurs in the simulation, and sufficient simulation accuracy cannot be obtained. The present invention provides a logic simulation method which solves the problem that the conventional technique has, because the value of the propagation delay time is fixed during execution of the simulation, and thus sufficient accuracy cannot be obtained. ..

[0015]

In order to solve the above-mentioned problems, the present invention describes the circuit structure of a gate instance to be simulated in a simulator composed of a computer or the like, and based on the description contents, In a logic simulation method by an event driven method for simulating the gate instance, the propagation delay time of the gate instance is made into a function, the function is executed by the event driven method, and the value of the propagation delay time is sequentially updated to I am trying to simulate a gate instance.

[0016]

According to the present invention, since the logic simulation method is configured as described above, the function is called each time an event occurs in the gate instance during the simulation, in response to the change in the propagation delay time of the gate instance. Be done. Then, the value of the propagation delay time is sequentially updated by calculation and replacement of the value of the propagation delay time, and the accurate value of the propagation delay time is always reproduced (maintained) over the entire execution time of the simulation. As a result, the accuracy of the logic simulation can be improved and the above problems can be solved.

[0017]

1 (a) and 1 (b) are explanatory diagrams of a propagation delay time t _{pd in} the case of a buffer gate as a gate instance showing an embodiment of the present invention, and FIG. FIG. 6B is a signal waveform diagram of the circuit example.

Propagation delay time t of the gate instance
_pd generally changes as the simulation time t progresses. As an example of the propagation delay time t _pd , referring to FIG.
The case of expressing is explained.

Here, the signal waveform is represented by a rising time t _r or a falling time t _f of a signal with respect to a net on an input side or an output side. For simplification of explanation, t _r = t _f = t
_in .

As shown in FIG. 1A, when the buffer gate C is taken as an example of the gate instance, the signal waveform diagram of the net i on the input side and the net j on the output side is shown in FIG. 1B. ing.

_Let t _pd (i → j) be the propagation delay time of the path of the gate instance C from the net i to j.
_pd (i → j) is the rise time t _in of the signal waveform on net i
It is represented as a function Ft _pd (i → j) (t _in (i)) of (i). The signal waveform on the net j is represented as a function Ft _in (i → j) (t _in (j)) of the rising time t _in (j). The characteristics of such propagation delay time t _pd are the same for other gate instances not shown, and these functions are added to each gate instance.

In order to reflect such characteristics of the propagation delay time t _{pd in} the logic simulation, the gate instance C, etc. are updated as the simulation time t progresses by the following updating procedures (i) to (iii). The propagation delay time t _{pd of} is to be updated sequentially.

(I) If an event occurs in the net i on the input side of a certain gate instance C using a simulator composed of computers, that is, if a change occurs in the net i on the input side. , Or a signal is input to the net i), the function Ft _pd (t _in (i)) = t _pd stored in the simulator.
Call (i → j), Ft _in (t _in (j)) = t _in (j). This is called "event driven function call". Here, Ft _pd and Ft _in are arbitrary functions.

(Ii) Based on the function Ft _pd , the simulator updates the value of the propagation delay time t _pd . (iii) the value of the function Ft _in the time t _in is also updated,
This new value is the function Ft of the next-stage gate instance.
It becomes an argument of _pd and Ft _in .

Using the above propagation delay time updating method, for example, when the circuit of FIG. 2 is simulated,
The propagation delay times t _pd of the gate instances A and B are expressed by the following equations (1) to (3), respectively.

[0026]

[Equation 1]

As can be seen from the equations (1) to (3),
Propagation delay time t _pd (3 →) for paths 1 → 3 → 4 and paths 2 → 3 → 4 from inputs 1 and 2 to outputs 3 and 4 in FIG.
4) has a different value. Which path the signal goes through depends on the signal at input 1 or 2. That is, the propagation delay time t _pd (3 → 4) of the gate instance B changes with the progress of the simulation time t. Therefore, as described above, the propagation delay time t _pd is converted into a function, the function is stored in the simulator in advance, and each time an event occurs in the instances A and B, the stored function is called to propagate the propagation delay time t _pd. The value of is sequentially updated by the updating method. Thereby, it is possible to flexibly cope with a complicated temporal change of the propagation delay time t _pd represented by the input waveform effect of the gate instances A and B, and the simulation accuracy is improved.

The present invention is not limited to the above embodiment,
Various modifications are possible. For example, the method of storing the function stored in the simulator can be stored using any hardware or software, and the calling or updating process of the function can be executed by any means. The gate instance to be simulated is an AND gate,
It can be applied to various logic circuits such as a NAND gate and a NOR gate.

[0029]

As described above in detail, according to the present invention, the propagation delay time is made into a function, and the function is called every time an event occurs in the instance during the simulation execution to obtain the value of the propagation delay time. I am trying to update it one by one. Therefore, it is possible to reproduce a more accurate propagation delay time and flexibly cope with complicated temporal changes in the propagation delay time represented by the input waveform effect of the gate instance, thereby improving the simulation accuracy. Can be expected.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an example of the present invention.

FIG. 2 is a diagram showing an example of a circuit to be simulated.

FIG. 3 is an operation explanatory diagram of FIG. 2;

[Explanation of symbols]

1, 2 inputs 3, 4 outputs A, B, C Gate instance (logic circuit) i Input side net j Output side net

Claims (1)

[Claims] 1. A logic simulation method by an event-driven method, in which a circuit structure of a logic circuit to be simulated is described in a simulator, including its connection relationship, and the logic circuit is simulated based on the description. A logic simulation method characterized in that a propagation delay time of the logic circuit is converted into a function, the function is executed by the event driven method, and the value of the propagation delay time is sequentially updated to simulate the logic circuit.