JPH05165916A - Parallel logic simulation system - Google Patents

Abstract

PURPOSE:To enable simulation for a logic circuit equipped with the multifunctional circuit of a microprocessor or the like by a parallel logic simulator in level sort and event driven systems. CONSTITUTION:The information of input priority orders for multifunctional circuit chips is registered on a library in a control processor 0 beforehand. The control processor 0 adds the priority information in the library to a simulation event result at a maximum level obtained from plural processors 1-4 to simulate a circuit model according to the level sort and event driven systems, and the information is transmitted to a real chip simulator 6. This real chip simulator 6 simulates the multifunctional circuit chips while impressing the respective values of the simulation event results to corresponding inputs according to the priority information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel logic simulation method, and more particularly to a level sorting method and an event driven method.

[0002]

2. Description of the Related Art A conventional logic simulation method of this type will be described. FIG. 5 is a system configuration diagram of a parallel logic simulator. For each line (described later) of a logic circuit model to be simulated, a plurality of processors 1 to 4 (which sequentially execute simulation at a circuit level (described later) in parallel). (In this example, four processors are used.)
And a control processor 0 that manages these processors 1 to 4, and a network 5 that forms a path for event communication between the processors 0 to 4.

Then, level start signals 21 to 24 for sequentially advancing the logic simulation of each of the processors 1 to 4 for each level are output from the level management section 03 of the control processor 0, respectively.
Level end signals 31 to 34 notifying that the one level logic simulation has ended are
4 to level management unit 03 of control processor 0
Are output respectively. The level management unit 03 commonly outputs a level clear signal 20 for returning the levels of all the processors 1 to 4 to the initial levels.

FIG. 6 is an example of a circuit diagram of a logic simulation target, which shows input terminals 101 to 104 and an inverter gate.
111, 113, AND gates 112, 114, 116, delay gate 115, and microprocessor (multifunctional circuit) 120
And output terminals 141-143. In this example, the microprocessor 120 has three inputs (A to C),
Although it is shown that it has two outputs, it is needless to say that it has a large number of inputs and outputs for simplification and actually.

The inverter gate 111 is an AND gate 112.
Inverter gate 113, which is a faster operating gate
A delay gate 115 irrelevant to the logic is inserted in the output of the input signal, and even if the input terminals 101 to 103 change simultaneously, the input condition of the microprocessor 120 shown in FIG. ) "Input A is input B
Input B is set earlier than Input C ”.

FIG. 7 is a circuit obtained by removing the microprocessor 120 from the circuit shown in FIG. 6, and the conventional logic simulator shown in FIG. 5 cannot perform simulation because the microprocessor 120 has multiple functions. Except for this microprocessor, output terminals 201 to 203 corresponding to the inputs A to C are added, and a simulation is performed by the circuit of FIG.

FIG. 9 shows a model of the circuit shown in FIG. 7, which is modeled by the parallel logic simulator for simulation. The model shown in FIG. (Level 4 in the example)
Has been converted to be located in. Furthermore, each line 1
Nodes 312, 313, 322, 3 to match the level of each 4
23, 332, 333, and 341 are added respectively, and all lines 1 to 4 are set to the maximum level 4.

Each of the lines 1 to 4 is one of the attributes assigned to each signal propagation direction by paying attention to the propagation direction of each signal from the input terminal, and the corresponding processors 1 to 4 are provided for each line. , The simulation of each node (level) of the corresponding line is sequentially performed in parallel.

Each level 0 to 4 is one of the attributes given to each node, paying attention to the order of signal propagation which is sequentially propagated through each node for each line. The simulation is sequentially performed toward the maximum level 4, and the simulation is a level sort method.

The simulation operation will be described. First,
Control processor 0 from input storage 01 to route 4
0, the network 5, and the routes 51 to 54, respectively, to input nodes 310, 320, 330 of the processors 1 to 4, respectively.
, 340 propagates the first input value (logical value “0”), respectively.

Next, the control processor 0 turns on the level start signals 21 to 24, and each processor 1 to 24 is turned on.
4 simulates level 1 nodes 311, 321, 331, 341. When the simulation is completed, each of the processors 1 to 4 turns on the level end signals 31 to 34 and outputs it to the control processor 0.

When the level management unit 03 confirms that the level end signals have been input from all the processors, the level start signals 21 to 24 are turned on again, and the level 2 node 31 is turned on.
Simulate 2, 322, 332, 342. Similarly, the simulation is repeated up to the maximum level 4.

The simulation results of each output node of the maximum level 4 are routed from the routes 41 to 4 by the processors 1 to 4.
It is transmitted to the output storage unit 02 of the control processor 0 via 44, the network 5 and the route 50.

The result of this simulation is shown in FIG.
Each processor 1 to 1 according to the event format shown in
4 are generated and stored in the output storage unit 02.
In this event format, "processor number" indicates the destination processor number of the simulation result, "output destination node number" indicates the destination node number of the simulation result, and "output destination pin number" indicates the output in the circuit of FIG. The terminals are shown. “Value” indicates the logical value of the signal at the output terminal at that time.

In the paths 350 to 352 extending between the processors (lines), the routes 43 to 5 and 52, and the routes 43 to 5 and 53 are routed according to the event format of FIG. 11A.
From the route 43 via the network 5 and the route 52 to the input nodes 330 to 321 and 331 to 342, respectively.
Propagate values from 32 to 343 respectively.

In a conventional parallel logic simulator of this type, if a simulation target circuit has a multifunctional circuit such as a microprocessor, the circuit without the simulation must be used for simulation, so that the entire target circuit can be accurately measured. I can't simulate.

That is, in a multifunctional circuit such as a microprocessor, there are many restrictions (time restrictions) on the input signal conditions at the input thereof, and therefore the information of the input priority, which is the time restriction, is also included. This is because it cannot be included in the simulation.

[0018]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a logic simulation method for a circuit model including a multifunctional circuit having a limited input priority.

[0019]

DETAILED DESCRIPTION OF THE INVENTION Parallel logic simulation according to the present invention.
The method is that the signals are sequentially propagated from multiple input terminals through each node.
Paying attention to the signal propagation order that is assigned to each node
And the level of each signal from the input terminal
Focusing on the propagation direction, the attributes assigned to each signal propagation direction
One line is pre-defined and
At the Nth level (N is an integer of 4 or more)
Node a multifunctional circuit having priority with respect to temporal order
Regarding the circuit model of the simulation target included as
Corresponding line stains provided for each of the lines
Multiple lines that are installed in parallel to create
The simulation processor sequentially
Level sort method that evaluates the node belonging to each line for each
A parallel logic simulation method of a multi-function
The level of the generation node of the supply signal to each input to the functional circuit is
All are at level N-1 and all of the processors are
Note that the N-1th level simulation was completed.
In response, at the end of these
After receiving the simulation result information, this information
Of the multi-functional circuit
It sends it to the processor that makes the simulation,
The above-mentioned multifunctional circuit was simulated.
It is characterized by

In another parallel logic simulation method according to the present invention, the level which is one of the attributes given to each node in consideration of the signal propagation order sequentially propagated from a plurality of input terminals through each node, A line, which is one of the attributes given to each signal propagation direction by paying attention to the propagation direction of each signal from the input terminal, is defined in advance, and the Nth level (N is an integer of 4 or more) among the levels. In regard to the circuit model to be simulated, which includes, as nodes, a multifunctional circuit having a priority with respect to the temporal order of input application, it is provided corresponding to each of the lines and provided in parallel to perform the simulation of the corresponding line. A parallel logic simulation method of a level sort method for evaluating a plurality of nodes, wherein a generation signal of a supply signal to each input to the multifunctional circuit is generated. The circuit level is configured such that the maximum level becomes the (N-1) th level by adding the circuit model element for the adjustment node according to the priority, and each of the processors has the maximum level of the corresponding line. When the simulation is completed, the simulation result of each processor at that time is sent to the processor that simulates the multifunction circuit, and thereby the simulation of the multifunction circuit is performed.

[0021]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a system block diagram showing an embodiment of the present invention, and the same parts as those in FIG. 5 are designated by the same reference numerals. In this embodiment, in addition to the conventional parallel logic simulator configuration, a real chip simulator 6 is provided, and the real chip simulator 6 simulates only a multifunctional circuit chip (real chip) device such as a microprocessor. ..

An example of the block of the control processor 0 in this case is shown in FIG.
The input / output converters 04 and 05 for exchanging event information with the real chip simulator 6 and the library 0 for converting the level of the conventional parallel logic simulator into the time information that the real chip simulator 6 can recognize.
6 and 6 are added to the configuration of FIG.

Also in this example, the circuit shown in FIG. 6 is used as a simulation target, and the model shown in FIG. 10 is shown in FIG. 17A when the parallel logic simulator models the circuit. It is converted so that the output terminal is located at the maximum level (level 4) through the compiler. Then, the microprocessor 120 is placed on the line 0 as the node 390, and the node 390 is arranged at the level 3.

Nodes 312, 322, and 332 are added so that the levels for generating the respective inputs to the node 390 of the microprocessor are all level 2.

In this example, assuming that the simulation is executed according to the input patterns shown in FIG. 12, that is, the patterns and the order shown in (a), (b), and (c) of FIG. 18, the input patterns are stored in advance. The input value “0000” is propagated to the nodes 310, 320, 330, 340 from the input storage unit 01 of the control processor 0 to the processors 1 to 4 via the network 5, and the level management unit 03 transmits the level start signals 21 to 24. Is turned on, and level 1 of each line is simulated.

As a result, the results obtained by executing the simulations by the processors 1 to 4 are as shown in level 1 of FIG. 18 (b). At this time, the processor that has completed the simulation turns on the level end signal, the level management unit 03 confirms that the level end signals from all of the processors 1 to 4 are turned on, and again checks the level start signal 21 to
Turn on 24 to simulate level 2. The result is shown in level 2 of FIG. 18 (b).

The initial values of the nodes 312, 322 and 332 are "XX.
Since it is indefinite in X "and has changed to" 101 "after the simulation, the processors 1 to 4 respectively generate the events 1 to 3 in FIG. 11B according to the event format in FIG. 11A. Then, it is stored in the output storage unit 02 of the control processor 0 via the network 5.

After all the level end signals are turned on, the input conversion unit 04 receives all event 1 from the output storage unit 02.
3 to 3 (the simulation result shown in FIG. 11B),
Further, the pattern management unit 08 outputs the pattern number (in this case, the input pattern is “0000”, so this pattern number is shown as “0”), and the library 0
The input propagation priority information is read from 6 respectively.

In this library 06, the time priority information of the inputs A to C of the microprocessor 120 is registered in advance. In this case, A is the highest priority, B is the next priority,
C has the lowest priority (see FIG. 8).

Therefore, the input conversion unit 04 causes the events 1 to 3 to occur.
Event 1 based on the contents of the library 06
Is determined as the highest priority, the output destination pin number and the value of the event 1 are merged, the pattern number of the pattern management unit 08 is further merged, and the priority is merged as in the event format shown in FIG. 11 is generated. This event 11 is route chip 60 via real chip simulator 6
Is input to. Based on this event 11, the value "1" is propagated to the input 201 of the node 390 which is the microprocessor 120.

Similarly, the events 12 and 13 are sequentially generated, and the real chip simulator 6 sequentially generates the event 1
Input the values "0" and "1" of 2 and 13 to the node 390 202
, 203.

Next, a simulation is executed based on the pattern number "1" (the input pattern in this case is "1111") from the pattern management unit 08. In this case, the level clear signal 20 is turned on again and all the levels of the processors 1 to 4 are returned to 0. Then, the input pattern "1111" is propagated from the input storage unit 01 of the control processor 0, and all the level start signals 20 are turned on. Hereinafter, levels 1 and 2 are simulated as in the case of the pattern number 0 described above. The result at this time is shown in FIG.

The values of the nodes 321 to 324 change from "101" to "010" as shown in FIG. 18C, and the processor "1" changes the value "0" of the node 312 to the node 32 as an event.
The value of 2 is “1” and the value of processor 2 is “0” of the node 332.
Are output to the output storage unit 02 of the control processor 0 via the network 5, respectively.

Thereafter, as in the case of the pattern number "0", the events 14 to 16 in FIG. 13C are respectively generated, and the real chip simulator 6 similarly simulates the node 390 of the microprocessor 120. Of.

FIG. 3 is a block diagram showing another embodiment of the control processor 0, and the same parts as those in FIG. 2 are designated by the same reference numerals. In this example, the library 06 is removed from the configuration of FIG. 2, and the event format in this example is shown in FIG.

In this event format, FIG.
A parameter is added to the event format of (a), and this parameter means the input priority information in the node 390 of the processor 120.

The process up to the level 2 simulation of the model shown in FIG. 10 is the same as in the above embodiment. Events 17 to 19 shown in FIG. 14 are input to the output storage unit 02 of the control processor 0 via the network 5 from the nodes 312, 322, and 332 of level 2.
Each parameter in the events 17 to 19 and 20 to 22 indicates the temporal priority of the corresponding event, where 0 indicates the highest priority, 1 indicates the second priority, and 2 indicates the second priority. It is assumed that the temporal priority information is input in advance in each of the processors 1 to 4.

The parameters of these events are read by the input conversion unit 04, converted into the events 11 to 13 of FIG. 13, and input to the real chip simulator 6. The following operation is the same as that of the above embodiment.

FIG. 4 is a block diagram of a control processor 0 in another embodiment of the present invention, and the same parts as those in FIGS. 2 and 3 are designated by the same reference numerals. In this example, the level start signal is independently distributed for each processor.

FIG. 15 shows a model created through the compiler shown in FIG. 17B. One level of the node 323 for adjusting the input priority is adjusted to the input 202 of the node 390 corresponding to the microprocessor 120 by using the library at the time of compilation. , A model in which nodes 333 and 342 for adjusting the input priority are added to the input 203 for two levels.

The simulation up to level 2 of this model is the same as in the embodiment of FIG.
Event 1 shown in FIG. 11B is input from the level 3 node 312 to the output storage unit 02 of the control processor 0 via the network 5.

The input conversion unit 04 reads the value 2 of the current level from the pattern management unit 08, and the event 23 according to the event format 4 of FIG. 16A from the pattern number, the pin number and the value as in the embodiment of FIG. Is created and input to the real chip simulator 6.

The real chip simulator 6 executes the simulation at that time and the output unit 05 stores the result. Since the simulation of the processor 1 is completed up to this point, at the next level 3, the level start 22, 2 is performed in order to simulate only the processors 2, 3, 4.
Turn on only 3,24.

At level 3, the event 2 is input from the node 323 to the output storage unit 02. The input conversion unit 04 reads the current level value 3 from the pattern management unit 08, creates an event 24 according to the event format 4, and inputs it to the real chip simulator 6. The real chip simulator 6 executes the simulation at that time, and the output unit 05 stores the result. Similarly, level 4 and subsequent simulations are repeated.

[0046]

As described above, according to the present invention, the signal application order that can be recognized by the real chip simulator is included in the simulation event information for the multifunctional circuit chip in which the input order of the input signal of the microprocessor or the like is limited. Since the time information shown is added, the real chip simulator has an effect that it is possible to execute the simulation for the multifunction circuit chip to be simulated by this time information.

[Brief description of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a control processor used in the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a control processor used in a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a control processor used in a third embodiment of the present invention.

FIG. 5 is a block diagram of a conventional parallel logic simulator.

FIG. 6 is a circuit diagram of a simulation target in the present invention.

FIG. 7 is a conventional simulation target circuit diagram.

FIG. 8 is a diagram showing input priority of a microprocessor.

FIG. 9 is a model diagram of a conventional simulation target.

FIG. 10 is a simulation target model diagram in the first and second embodiments of the present invention.

FIG. 11 is a diagram showing an example of an event format.

FIG. 12 is a diagram showing an input waveform example of a logic simulation.

FIG. 13 is a diagram showing another example of an event format.

FIG. 14 is a diagram showing another example of an event format.

FIG. 15 is a simulation target model diagram in the third embodiment of the present invention.

FIG. 16 is a diagram showing still another example of an event format.

FIG. 17 is a flowchart for modeling a simulation target circuit.

18A is an initial state diagram of the model before simulation, FIG. 18B is a diagram showing a simulation result of the model when the input pattern is “0000”, and FIG. 18C is a model when the input pattern is “1111”. It is a figure which shows the simulation result of.

[Explanation of symbols]

 0 control processor 1 to 4 processor 5 network 6 real chip simulator 01 input storage unit 02 output storage unit 03 level management unit 04 input conversion unit 05 output conversion unit 06 library 08 pattern management unit

Claims (2)

[Claims] 1. A level, which is one of the attributes given to each node, paying attention to a signal propagation order sequentially propagated from a plurality of input terminals through each node, and the propagation of each signal from the input terminal. A line, which is one of the attributes given to each signal propagation direction by paying attention to the direction, is defined in advance, and relates to the temporal order of input application at the Nth level (N is an integer of 4 or more) among the levels. Regarding a circuit model to be simulated which includes a multifunctional circuit having a priority as a node, a plurality of line simulation processors provided corresponding to each of the lines and provided in parallel to perform simulation of the corresponding line sequentially A parallel logic simulation method of a level sort method for evaluating nodes belonging to each line for each level, In response to the fact that all the generation nodes of the supply signal to the input are set to the (N-1) th level and all the processors finish the simulation of the (N-1) th level, these processors at this end time point are processed. Upon receiving the simulation result information, the priority information regarding the temporal order is added to this information, and the information is sent to the processor that simulates the multifunction circuit, thereby performing the simulation of the multifunction circuit. Characteristic parallel logic simulation method. 2. A level, which is one of the attributes given to each node, paying attention to the order of signal propagation which is sequentially propagated from a plurality of input terminals through each node, and the propagation of each signal from the input terminals. A line, which is one of the attributes given to each signal propagation direction by paying attention to the direction, is defined in advance, and relates to the temporal order of input application at the Nth level (N is an integer of 4 or more) among the levels. A level sort for evaluating a plurality of nodes which are provided corresponding to each of the lines and which are provided in parallel to perform simulation of the corresponding line, regarding a circuit model to be simulated including a multifunctional circuit having priority as nodes. In the parallel logic simulation method of the method, the level of the generation node of the supply signal to each input to the multi-function circuit is adjusted according to the priority of the adjustment node. By adding a circuit model element for the above, the maximum level becomes the N-1th level, and when each of the processors finishes the simulation of the maximum level of the corresponding line, the simulation result of each processor at that time Is sent to a processor that simulates the multi-function circuit, thereby simulating the multi-function circuit.