JPH04250570A - Data control system by high-level composition - Google Patents

Abstract

PURPOSE:To perform the high-level composition of logic design in consideration of layout information and enable efficient design by evaluating the result of high-level scheduling, allocation, and floor planning according to a control/data flow graph. CONSTITUTION:Path information 1-1 is added to the path of the control/data flow graph 1 and the scheduling, allocation, and floor planning are performed according to them; and the delay time of their result is evaluated and path delay information accompanying the floor planning is fed back path delay information 1-1 repeatedly to perform the composition of operation description level wherein the violation of path delay depending upon the layout is eliminated.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is a data management method in high-level synthesis, which manages path delays associated with layout at a high level of abstraction, eliminates path delay violations, and enables synthesis. It concerns data management methods in synthesis. As we enter the ASIC era, the need for logic design support is increasing. As automatic logic synthesis technology for combinational circuits has reached the level of practical use, there is an increasing demand for design support and automatic synthesis from a higher algorithm level.

0002

[Prior Art] The flow of conventional high-level synthesis is shown in Figure 4 (
Shown in a). Here, the behavioral description that is input to the system is given in a hardware description language such as VHDL as shown on the left side of FIG. 4(b). The translator converts the behavioral description language as shown on the left side of FIG. 4(b) into an internal representation schematically shown on the right side of FIG. 4(b) that does not depend on the syntax of the language. This internal representation is typically
A control/data flow graph is used that expresses data dependencies and order relationships between operations. For example, the algorithm shown on the left side of FIG. 4(b) can be expressed by the graph shown on the right side.

High-level synthesis deals with data path allocation problems, such as how to allocate facilities such as registers and calculation modules to variables and operators that appear in behavioral descriptions, and how to determine the execution order of each operation. It consists of several scheduling issues. Since these tasks are interdependent, data paths and data control are determined by considering both simultaneously or by repeatedly performing both. Once scheduling and allocation are completed, specifications for the data path and its corresponding control circuit are generated, and the final circuit is then generated using a layout tool.

0004

[Problems to be Solved by the Invention] Conventional scheduling/allocation reduces the circuit scale as much as possible.
Allocate facilities in a way that reduces the number of steps required for operation. At this time, the circuit scale and delay time were evaluated using information about each facility stored in the library. However, the path delay time that reflects the layout such as placement was not taken into consideration. Therefore, when the actual layout is done,
A situation occurs where the delay in the circuit becomes large and exceeds the delay time allowed for one stage, and something has to be corrected. Feedback for this correction should be as short as possible, and it is better to have as little feedback as possible, but since the scheduling and other aspects of the design stage were corrected by going back through a long feedback loop, there was a problem in that it was difficult to design efficiently.

[0005] The present invention evaluates the results of high-level scheduling, allocation, and floor planning based on the control/data flow graph, and feeds back the path delay time due to the layout to the paths of the control/data flow graph. The aim is to perform synthesis that takes layout information into consideration and to enable efficient design.

[0006]

[Means for Solving the Problems] FIG. 1 shows a diagram illustrating the principle of the present invention. In FIG. 1, a control/data flow graph 1 represents a behavioral description using an internal representation that does not depend on the syntax of a language. Scheduling part 2
is for determining (scheduling) the execution order of operations.

The allocation unit 3 allocates facilities such as registers to variables and operators represented by the control/data flow graph 1. The floor plan unit 4 is for arranging assigned facilities. Layout information addition is to add path delay information 1-1 associated with the layout to the control/data flow graph 1.

[0008] The data management section 5 has the scheduling section 2.
, the delay time, etc. of the results of scheduling, allocation, and floorplanning performed by the allocation unit 3 and floorplanning unit 4 are evaluated.

[0009]

[Operation] As shown in FIG. 1, the present invention provides path delay information 1 for paths of a control/data flow graph 1, which is an expression that does not depend on the syntax of a language for describing the behavior of a logical design.
-1 is added, and based on this control/data flow graph 1 and path delay information 1-1, the scheduling unit 2, allocation unit 3, and floor planning unit 4 perform scheduling, facility allocation, and floor planning, and manage the data. Unit 5 repeatedly evaluates these results and feeds back the path delay information associated with the layout to the path delay information 1-1 of the control/data flow graph 1, resulting in a synthesis that eliminates layout-dependent path delay violations. I try to do this.

[0010] Therefore, by adding path delay information during layout obtained at the scheduling, allocation, and floor planning stages to the paths of the control/data flow graph and feeding it back, and repeating the evaluation of delay time, layout can be achieved at a high level. It becomes possible to perform efficient design by taking the information into consideration and performing synthesis without violation of delay time.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the structure and operation of an embodiment of the present invention will be explained in detail with reference to FIGS. 1 to 3. Figure 1 (a)
The control/data flow graph 1 is a graph expressed by the internal representation described on the right side of FIG. 4(b), which does not depend on the syntax of the behavioral description language described on the left side.

Path delay information 1-1 is provided in this embodiment and added to the path of control/data flow graph 1, and is used to provide feedback on the path delay time obtained when adding layout information, which will be described later. It will be updated accordingly. Scheduling/allocation is
This is performed by the scheduling unit 2 and allocation unit 3 in (b) of FIG. Allocate facilities such as registers and calculation modules to children, determine connection relationships,
It generates control signals to registers, etc. (see (a) and (b) in FIG. 2). Since these tasks are mutually dependent, both should be taken into consideration at the same time. Specifically, these operations are performed based on a correspondence table showing whether each operation can be realized, data on the execution delay time of each facility, and circuit scale data.

Floor planning is carried out by the floor planning unit 4 shown in FIG. In addition, a floor plan is created (a floor plan showing where to place registers, etc.) (see (c) in FIG. 3).

[0014] Adding layout information involves, after floorplanning, calculating the path delay time between each floorplanned block based on the distance between the blocks, and adding this to the corresponding path in the control/data flow graph 1. It is set in such a manner that it is fed back as path delay information 1-1. The evaluation is performed by the data management unit 5 in FIG. The result is evaluated (for example, by calculating the delay time between control steps and evaluating whether it falls within a pre-specified clock time). If a violation is detected as a result of the evaluation, such as a delay time that is too long to fit within one clock, the scheduling and allocation for operations related to that path are corrected. These loops are repeated automatically or according to operator instructions until the conditions are met (
(described later using FIG. 3).

As described above, the behavioral description converted into a control/data flow graph 1 that does not depend on the syntax of the language is used as input, and scheduling, allocation, and floor planning are performed, and each block is determined from the floor planning results. Control the path delay time between / Path delay time of the corresponding path in data flow graph 1 1-1
Based on these, the delay time is evaluated (for example, whether it falls within one clock or not), and when a violation is detected, the scheduling and allocation related to that path are automatically corrected. By repeating this based on the target or instructions from the operator, it becomes possible to design at an early stage that does not violate the path delay time due to the layout at a high level.

FIG. 1B shows a block diagram of the present invention. Here, the scheduling section 2, the allocation section 3,
The floor plan unit 4 and data management unit 5 are programs that perform the processing described in the scheduling/allocation, floor plan, and evaluation section (a) of FIG. The design data 6 is various data as shown in (a), (b), (c), and (d).

(a) A control/data flow graph 1 representing the order relationship between operations. (b) The result of scheduling the control/data flow graph 1 in (a), in which, for example, operation "+" is scheduled at step i.

(c) A data path resulting from allocation of facilities such as arithmetic modules and registers, and its control circuit. (d) This is a floor plan created based on the data path in (c). The correspondence relationship between each data item (b) of FIG. 1 explained above is specifically shown in FIG. 2.

FIG. 2 shows the correspondence between data according to the present invention. FIG. 2(a) shows the correspondence between operations and facilities. Control/Data Flow Plan 1
The correspondence relationship is shown using arrows in the upper row, the middle row where facilities are assigned to each operation, and the lower row where facilities are floorplanned. For example, the operation "+" in the upper row is associated with "ALU (adder)" in the middle row, and then with "ALU" in the lower row.

FIG. 2B shows the correspondence between edges representing dependencies of operations and paths on the floor plan. As shown in the upper part, registers s1, s2, and s3 for holding values are introduced at points in the control/data flow graph 1 at which edges associated with operations pass through control steps, as shown in the diagram. . Signals for controlling register transfer are input to these registers s1, s2, and s3. Therefore, paths related to register transfer also include paths from the control circuit to the registers. In the lower stage, a facility is assigned to the control/data flow graph 1 in the upper stage, the path delay time is calculated for the path path between these assigned facilities, and this path delay time 1-1 is applied to the corresponding path in the control/data flow graph 1. Set. This evaluates whether the total delay time, which is the time required to execute the operation sequence to be executed within the control step and the path delay time set in this embodiment, falls within the time of one clock. , when the total delay time is not within one clock, modify the scheduling and allocation, re-evaluate, and repeat until the total delay time is within one clock. As a result, in the past, the time required for a control step was evaluated based on the delay time of only the operation, ignoring the path delay time, but in this embodiment, the path delay time after floorplanning is further added. By evaluating the total delay time, it is possible to perform efficient design that takes layout-related delays into consideration at an early stage of floor planning. In addition, by incorporating the delay time of the signal line from the control circuit into the path delay time,
These can also be inspected and designed so that the delay time is within one clock.

Next, FIG. 3 shows a configuration diagram of one embodiment of the present invention. FIG. 3(a) shows the specifications of the synthesis target. This is a control/data flow graph 1, which is an internal representation unrelated to syntax, for the behavioral description language described below. t1=a+b d=t1×c Further, operations + and × represent addition and multiplication, respectively.

FIG. 3(b) shows the scheduling/allocation results. Here, p1 is a register and +
(adder), p2 is a path between + (adder) and × (multiplier), and p3 is a path between × (multiplier) and the register. FIG. 3(c) represents the floor plan result. This is the scheduling/
This represents the floorplanning results for the allocation results. Here, p1, p2, p3 represent paths p1, p2, p3 in FIG. 3(b), and registers 1, 2, 3, 4
represents registers 1, 2, 3, and 4 in FIG. 3(b), the adder represents + in FIG. 3(b), and the multiplier represents registers 1, 2, 3, and 4 in FIG.
), and the control circuit represents a circuit that sends control signals to registers 1, 2, 3, 4, etc.

FIG. 3(d) represents a modified example of scheduling/allocation. This is shown in (b) in Figure 3.
) in the control step p1, + (adder),
As explained below, the total delay time of the routes of paths p2, × (multiplier), and path p3 cannot be accommodated within one clock, so register 5 is provided to modify the delay to two control steps. be. This will be explained in detail below.

(1) Clock cycle: 45 ns Operation + delay time: 10 ns. (2) Scheduling unit 2, allocation unit 3
The control steps and facilities are allocated as follows: Σ(delay time of operation within one step)≦clock cycle・■. At this time, (+ delay time) + (× delay time)
=10+30=40...■, clock size 4
Since it is smaller than 5ns, as shown in FIG. 3(b),
Control steps are assigned to perform + and × within one step, and a data path consisting of adders, multipliers, and necessary registers 1, 2, 3, and 4 is generated.

(3) Based on the data path generated in (2), a floor plan is created as shown in FIG. 3(c). Then, on this floor plan, the delay times of paths p1, p2, and p3 between each facility are determined. (4) Path p1 between each facility found in (3)
, p2, and p3 are added to each path, ■ becomes
It will look like ■ below.

Σ (delay time of operation within one step) + Σ (delay time of path) ≦clock cycle
...■ Therefore, for example, the path delay time of p1+p2+p3 = 10ns...
If ・・・・・・・・・・・・■, the total delay time of the path P shown by the arrow in FIG. . In order to eliminate this violation, as shown in FIG. 3(d), the scheduling and allocation are changed by newly providing register 5 between the adder and the multiplier. This means that it has been modified to satisfy the constraints.

[0027]

[Effects of the Invention] As explained above, according to the present invention,
The layout-time path delay time obtained during the scheduling, allocation, and floor planning stages is added to the control/data flow graph path and fed back, and the delay time evaluation is repeated, allowing for a high-level layout. By taking the information into consideration, it is possible to efficiently perform synthesis without violation of delay time. This allows for faster and higher-level corrections, which would previously have required delay time violations to be detected after logic synthesis and actual layout and had to go back through a long feedback loop, resulting in more efficient design. It becomes possible to do so.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is an explanatory diagram of the correspondence between data according to the present invention.

FIG. 3 is a configuration diagram of one embodiment of the present invention.

FIG. 4 is an explanatory diagram of the prior art.

[Explanation of symbols]

1: Control/data flow graph 1-1: Path delay time 2: Scheduling section 3: Allocation section 4: Floor planning section 5: Data management section 6: Design data

Claims (1)

[Claims] Claim 1. In a data management method in high-level synthesis of logic design, path delay information (1-1 ) is added, and based on this control/data flow graph (1) and this added path delay information (1-1), scheduling, allocation, floor planning, and evaluation of the delay time of these results are performed. The path delay information associated with the above path delay information (1-1)
1. A data management method in high-level synthesis, characterized in that the data management method is configured to perform synthesis that eliminates path delay violations depending on the layout at the behavioral description level by repeatedly feeding back as follows.