KR100594593B1 - Parallel simulation method for rapid verifying design of semiconductor - Google Patents

Abstract

The present invention implements a hardware accelerator and a software algorithm for its optimal operation to overcome the limitations of the conventional software verification method. The present invention relates to a high-speed parallel verification method for designing a semiconductor device that can be calculated in time and immediately reflected in a design.

Semiconductor device, design verification, high speed parallel verification method, hardware acceleration device.

Description

       Parallel simulation method for rapid verifying design of semiconductor             

1 to 28 are views for explaining a conventional technology.

29 to 50 are diagrams for explaining the technique of the present invention.

The present invention implements a hardware accelerator and a software algorithm for its optimal operation to overcome the limitations of the conventional software verification method. The present invention relates to a high-speed parallel verification method for designing a semiconductor device that can be calculated in time and immediately reflected in a design.

Compared to a conventional system, several semiconductor chips have a small size by eliminating separate control signals and synchronization elements by incorporating inefficient elements due to control signals and synchronization signals between the chips into one chip. SoC (System on a Chip) is used to meet the needs of consumer electronics industry and consumers who demand low power.

However, the SoC design goals are defined in terms of production cost and efficiency rather than solving technical limitations as a way to bridge the gap between functional demand and design efficiency. to be.

The SoC needs to be developed and produced in a timely manner, which is required by the market due to its functional characteristics, and the shortening of the verification time is a shortening of the verification time since about 40% of the total time required for designing such a SoC is spent on chip characteristics verification. It is the most important factor in.

Logic gate simulation, compiled simulation and event simulation are mainly used as a verification method of a conventional semiconductor design.

Logic simulation analyzes a design drawing written in logic and assigns a virtual input from a computer and compares the output of the design drawing with expected outputs before implementing the functions on the design drawing directly on the chip. As a verification method, the expected output value of each logic is used, so the simulation order of the gates may not be performed correctly for the entire circuit.

Figure 1 is an example for explaining the logic model and timing of the logic simulation, it is a simple feedback and shows that the output O is completely different according to the model. In other words, in case of zero-delay, the output is kept as 1 from time 0, but in case of unit-delay or multi-delay, oscillation occurs from 2, 3 unit time respectively. . In this case, the simulator notifies the designer of this possibility and provides information to prevent circuit malfunction. As such, problems not found in zero-delay can be found in unit-delay or multi-delay models. In addition, problems such as Static and Dynamic Hazard, which are hard to find in the unit-delay, can be found in the multi-delay, but the disadvantage is that the simulation is complicated and the simulation takes a long time.

2 is a basic logic gate circuit, and FIG. 3 is an example of a pseudo simulation program for analysis of the circuit of FIG.

Since the simulation program of FIG. 3 is used before the value of variable X2 is stored, there may be a problem with the result of execution. For example, if all variable values are initialized to "0", the computer simulation is correct. Can't do it.

That is, if the input A = 1, B = 0, C = 0, D = 1, E = 1, the simulation result in Figure 13 is Q1 = 0, Q2 = 0 and the correct results Q1 = 0, Q2 = 1 and Shows different results.

In order to solve the above problems, leveling is performed to determine the order of performing the gate simulation, and a level number is assigned to each gate and the net.

Figure 4 is an example of the stepping operation, the start of the step number assignment method is to give a level value 0 to the primary (primary input), collect the value of each gate input net and extract the maximum value to the maximum value + 1 Is specified as the level of the gate.

If a level value is assigned to each gate, the levels are sequentially sorted according to the level value, and computer simulation is performed according to the level order. In the example of FIG. 2, {G1, G4} ?? G2 ?? {G3, Simulation is performed in the order of G5} to solve the X2 problem that caused an error in the simulation program of FIG.

5 is an example of a staged work program for level designation of each gate.

In addition, for the computer simulation, the necessary data structure is constructed through the analysis of the circuit internally and stored in a table form.

6 is an example of a gate table of a circuit analysis result of the example circuit of FIG. 2.

Logic gate simulation is performed by using the circuit diagram and input vectors through the above procedure, and then compares the values of the output net with the expected values to verify design drawings and functions, and to perform functional errors. Redesign and revalidation procedures are followed.

7 illustrates an algorithm of an interactive simulation which is a logic gate simulation method.

However, since the above-described simulation of the interactive method has to execute each operation element for each gate, and in particular, it performs a complicated process such as storing each output value according to the change of all input values in a table, The high density SoC analysis method is very difficult to optimize.

In order to make up for the shortcomings of the interpretive method, the compiled simulation method simulates the entire circuit using the repetitive syntax of C language or assembly language, thereby optimizing and speeding up the interpretive method.

9 is an example of a program using the improved compiled simulation method, and FIG. 9 shows an algorithm of the compiled simulation method.

FIG. 10 is a gate simulation program for the example circuit of FIG. 2 using a compiled simulation method.

However, the above-described interpretive and compiled methods must perform all the cases according to the number of input variations, and even if there is no output change due to the input change, all the unnecessary operations of simulating are performed.

Event-based simulation is a method of high-speed verification by eliminating these unnecessary motion elements.

The event method simulation method will be described with reference to the circuit of FIG.

In the circuit of FIG. 2, when each input value is (A, B, C, D) = (0,0,0,0) and (0,0,0,1), A, B, C values change. Since the gates G1 and G2 do not need to be simulated, the simulation of G4 can be omitted without testing X1 and X2.

12 shows a data structure for implementing an event, which is composed of scheduling information, bit information, and a new bit value.

Unlike the level method, the event method has a dynamic scheduling method. Since the dynamic method cannot predict the order of the gates in the circuit at the time of circuit analysis, it uses a queue. To enable dynamic scheduling.

That is, if an event is detected due to a change in the input value of the circuit, an event data structure (FIG. 12) is generated with the information of the corresponding input net, and an event queue stores the generated event data and waits for processing. will be.

13 is an example of a program showing a method of processing an event of an input value.

14 will be described in more detail by applying the program of FIG. 13 to the example circuit of FIG. 14.

Assuming two input values are (1,1,0,0,1,0) and (0,0,0,0,1,1), three of the two input values A, B, and F change Therefore, three events occur, and each event processing must be performed after being queued, so the first step of event processing is to copy the net value from the event data structure to a permanent value.

After that, all gates connected to the net are simulated, and the queue that processes all the gates is a gate queue.

15 is an example of a program for event processing, in which processing of an event is performed until all generated events are processed, and the performed event is removed from the queue and at the same time, the corresponding gate is stored in the gate queue. Several gates are stored in the gate queue.

Figure 16 shows the contents of the gate queue created as a result of this performance.

Figure 17 shows that after all events have been processed, each gate of the gate queue is simulated and the output of the gate, the output of the net, and the scheduling of this output net are performed. Do this.

In this way, the gate processing program generates a new event, stores the event in the event queue, and repeatedly calls the event processing program to process these events until there are no events to process.

At this time, the simulation of the input value is composed of an input processing program, a plurality of gates and an event processing program.

18 is a main program of such a simulation program and shows the overall configuration.

Referring to the timing model for implementing the above-described event simulation is as follows.

By default, level-based simulations simulate using a 0-delay model, while event-based simulations use a unit-delay or multi-delay model.

19 illustrates an example of performing an event simulation. A unit delay (1-delay) model simulates all gates having a delay value of 1, while an arbitrary delay model delays according to the characteristics of the gate, the number and type of inputs. The simulation is defined by defining the value as an integer, and shows an example of using an event-based algorithm when (A, B) is changed from (0,0) to (1,1).

The important point of event-based simulation is that first, gate G2 performs simulation immediately according to the change of input value A, which is the same as level simulation. Secondly, G2 performs two simulations, which is different from level-based simulations, where net Q has two events, so the Q value is converted from 0-> 1-> 0 to the net Q. If the input of the T flip-flop, the simulation results are different from the level method and the event method.

The two phases used in the event-based algorithm, the event (or net) and gate processing program phases, represent one time flow of the simulation. Therefore, the execution of the event processing program indicates the flow of one unit time, and the execution of the first event processing program is time 0, and the time is incremented by 1 for each execution of the event processing program.

Unlike the unit delay model described above, the multi-delay model simulates by assigning a random delay value to the gate. The difference in gate characteristics according to the number of inputs and fanout should be considered.

FIG. 20 shows a simple circuit using an arbitrary delay circuit. For example, if the values of A and B were changed at t = 0, the value of net F was not changed before t = 3. The value remains unchanged until t = 4, which can cause problems in event-based algorithms.

In the event-based algorithm, when t = 0, gates G1 and G4 are scheduled for simulation, and the scheduled gates G1 and G4 perform simulation and are scheduled when the events of nets C and E are t = 1. . However, action is needed to change the change in net E value at the right time. This is one way to delay the simulation of gate G4 until t = 3, but if net B changes its value at t = 1, 2, or 3, the simulation of gate G4 will run with an incorrect input. There is this. For the correct simulation, the gate G4 should be performed at t = 0 and the time to process the net event should be performed at t = 4. This difference between the generated time and the execution time is caused by the delay value of the gate. Two times exist in the simulation.

Inappropriate algorithms in the event simulation have a significant impact on simulation performance and results, which are used in unit-delay simulation for multi-delay simulation. In case of using a simple event queue, the event is stored in the event queue every time it is created.If the time is T and the event is processed, the simulator searches the queue to find the event of the corresponding time. Minimum sort algorithm) as well as take time O (n ^2), an event is generated and do takes O (n ²⁾ time time (Insertion sort) that is stored. Where n is the number of events.

In addition, since events are not generated in chronological order, in order to prevent this, the events must be sorted according to execution time before they are processed so that the correct results can be obtained. Bucket sort (bucket sort; A timing wheel, a variant of the O (n)) algorithm, and a priority queue, a variant of the heap sort (O (nlog ₂ n)) algorithm, are used.

The basic concept of the timing wheel is to identify an event queue as a set of several event queues representing one queue per unit time, that is, a data structure.

21 illustrates an example of a structure of a timing wheel. When a simulation is performed at a current T time when a maximum value of a delay of a gate is D, a maximum time at which an event I is performed is T + D. Therefore, there can be no events at times above T + D + 1, and because the gates are not simulated until all events have been processed, the maximum number of queues is D because no events are queued before time T or T. Can be defined as Events that occur at the simulation time T can be found using the syntax "Q position = T% D,% is modulation" to find the index of the queue. The simulator records and stores the "current time" based on the start time of the simulation, and the event processing program is the same as that of the unit delay model.

FIG. 22 is an example of a program showing a configuration of a simulation algorithm for a random delay model. The underlined part is a part changed from the unit delay model.

23 is an example of a gate simulation program for performing a gate.

However, in the above simulation, a problem occurs when two events of the same net are stored in a queue for processing.

24 is a circuit illustrating an example of such a problem, and means that the gate G is part of a large circuit. Assuming that the input and output values of gate G are generated at t = 100, the event is processed at t = 101 and the value of net a is converted from 1 to 0, which means that net b is processed at t = 105. It is scheduled, which indicates that at value t = 105, b will be converted from 0 to 1. However, if an event occurs at t = 102 and the value of net a is converted from 1 back to 0, the event at t = 105 is still in the queue and before the net b value is converted, and G is t = 102. Simulates using input 1 in, and does not raise a new event because the output of G is already zero. If a new event does not occur in this manner, an event is performed at t = 105 to convert the net b value to 1, and as a result, there is a problem that the input and output values of the gate G are all 1.

This problem occurs because the result of the gate simulation is compared with the value of net b at t = 102, because the net b value is converted at t = 106. One way to solve this problem is to examine the event in the queued net b and compare it with the new value, or alternatively, delay the comparison of the old and new values in the net and handle the latter. The method is simpler and easier to implement than the former method.

25 is an example of a program for processing by comparing the delay between the old value and the new value of the net.

FIG. 26 is an example of an arbitrary delay model of an event method for a more detailed description, in which the delay value of each gate includes G1 for two time units, G3 for two units, and G2 for one. Suppose there is a gate delay in units, the inputs are given randomly, and the value of the input assumes two 0, 1 values and the logic simulation of the event-driven type is performed. The simulator algorithm for doing this is as follows.

(a) input TEST (GET A, B, C); Input event processing

(b) Net_D: Net D unit program

(c) if new_value! = net_value then event processing (net validation) steps

(d) PUSH Gate_G3; Connecting gate of net D

(Fanout Gates)

(e) goto WHEEL [current_time]-> procedure timing wheel

(f) endif

(g) POP GATE_QUEUE

(h) Gate_G3: gate simulation step

(i) temp = net_D &net_E; Perform logic function

(j) QUEUE_INDEX = (current_time + GATE_DELAY)

          MOD Size_of_Queue

(k) PUSH net_O and temp onto

          WHEEL [QUEUE_INDEX];

(l) goto Gate_Handler

The algorithm is functionally divided into four parts, firstly, the part of (a) which interprets the input and verifies whether a given vector is an event, and the second is a unit program corresponding to net D. The part and the third are the unit programs corresponding to the respective gates (h) to (l), and the fourth is the gate and the net corresponding to the compiled programs (compiled simulation) of the (g) to (l) parts. A scheduler that manages and operates unit programs. Here, the net E of the circuit has a structure similar to the second part, and the entire simulator is composed of unit programs corresponding to E and O in addition to the net D. As described in the related art, the compiled method refers to a method of verifying a drawing by analyzing a circuit, expressing and interpreting the internal structure of a simulator, and generating an optimized C language code.

In the example circuit, gates G1 and G2 are performed by all input vectors. After that, the value of D is changed by the output of the gate G2, and this is verified in (c), and in the case of the event, the Gout, which is a fanout gate, is stored in the gate execution unit to perform the logic function in (h). Perform.

The main components of the simulator include a timing wheel for storing events and a gate cue. The timing wheel simulates the value of the input terminals (values of A, B, and C) or the gate output. It has the function to save the terminal value (net D, E, O value). In order to save memory in the simulator, the size of the timing wheel is set to the largest value of the gate delay value on the circuit plus 1, and the index of the timing wheel means unit time.

27 to 28 show the components of the simulator for performing the above algorithm. The hatched portion indicates the current time, and when the current time is larger than the size of the wheel, the first of the timing wheel using the operator of the MOD is shown. Specify again to use. That is, the representation of the wheel with respect to the current time in the example is "current time MOD 4" (wheel size).

In FIG. 27, according to the change of the input C of FIG. 26, G2, which is a gate of C, is stored in the gate queue and stored for use in step 2, and C, which is the current event, is removed. If there are no more events at the current time zero, it changes to the gate verify phase. This is the change condition to step 2, and this step simulates this gate if there is something stored in the gate queue. Gate G2 is performed and its output, value 1 of net E, is stored at the wheel position of current time 0 plus the delay value of gate 1 and processed in the next net verify step. As represented in step 3, net E is stored at time 1 of the wheel, where the current value of the net and the gate simulation values are stored, and if there are no more gates, the current time is incremented and net verification step 3 is performed. Is performed. In step 3, the net values are compared as in step 1, and in another case, the gate G3 having the net as an input is stored in the gate queue, and the same procedure as in the above steps 1 and 2 is performed.

In Fig. 28, when there are no nets or gates stored as in steps 5 to 6, only the respective net and gate simulation steps are repeated, and only the current time is increased. If step 9 is performed and there are no more events or gates, then the simulation for the input given in step 1 of FIG. 27 ends.

As such, the current logic simulation repeats the net verification step and the gate execution step, and if there is nothing stored in each queue, the simulation of one input is terminated and the required output is performed.

As described above, methods for faster and more accurate simulation have been devised and used through various methods, but most of them are by analysis of software programs, which still takes a long time for analysis.

The present invention has been made to solve the above problems of the prior art, by using a hardware method and an optimized software method for the functional verification of the semiconductor circuit drawings to enable a very quick verification compared to the prior art. have.

In order to achieve the above object, the high-speed parallel simulation method for design verification of a semiconductor device according to the present invention is characterized by verifying a circuit faster by applying hardware parallel processing and improved software accordingly.

Hereinafter, the most preferred embodiments of the present invention will be described in detail so that those skilled in the art can easily implement the technical idea of the present invention.

The event verification processing program of the logic circuit of the semiconductor circuit diagram is composed of a main program that manages input / output processing, event processing program execution, simulation program execution and simulation time, time increase, and simulation termination. In particular, the main program not only plays a role in managing the timing wheel that handles the scheduling of events and gate simulations, but the timing wheel and scheduling determine the performance of the simulation. The reason for this is that the number of times of scheduling, preparation for the execution of the gate simulation program and preparatory work for the execution of the corresponding event processing program are larger than the number of execution of the actual gate simulation and the event processing program.

The PC-set (Potential Change Set) algorithm applied in the present invention uses a level technique and a static scheduling technique for applying to a random delay simulation and a unit delay (Multi-delay and Unit-delay Simulation). The technical technique required to use the static scheduling technique is to determine the simulation time.

The method of determining the simulation is determined in a similar way to determining the level. The reason for determining the time of the simulation is that each net extracts the time during which the simulation is likely to be performed inside the circuit.

Similar to the method of determining the level, the calculation of the PC-Set starts from the input terminal. Since the probability that the input at the input stage changes (the occurrence of an event) is t = 0, the value of the PC set at each input stage is {0}. Since the random delay model includes the unit delay model (delta = 1), the unit delay model is included and each gate delay is defined as D. If the input of the gate is changed at time t, the output is likely to change at time t + D. Also, if all inputs did not change at time t, the output t + D would have the same value without change. In order to calculate the PC-set of the gate output, we need to know the PC-set of the gate input.

29, a PC set of gates and nets in a circuit is obtained and determined. Nets connected by wired-OR connection or by more than one source can be calculated by using both the gate and the PC-set of the net simultaneously. If a net is driven by more than one gate, the PC-set of that net can be obtained by the union function of set theory.

30 is an example of such a method, where a PC-set of gates is used to generate a simulation program.

Here, the PC-set of gate and net is used as an element for dynamic simulation, but additional work has to be performed to cover all the time that the gate's input net can be converted.

As can be seen in the example of FIG. 31, there is a factor of "4" in the PC-set of the gate. This means that at t = 4 the gate needs to perform the simulation. Therefore, the gate uses the value of the input net of t = 3 for the simulation. However, the value of the other input net on the gate does not need a new value until t = 7. Therefore, the net input of t = 4 should be obtained from the previous input vector. In this case, a "zero insertion" tag is used to define a net that preserves the previous input and add "0" to the PC-set argument to that net.

33 shows an example of the PC-set and an example of the "0" insertion correction, in which the element "0" of the corrected PC-set does not propagate along the circuit diagram. If "0" is inserted in the net of the circuit, only the gate G has two or more inputs, and the smallest element value of the PC-set of the gate G is the smallest element of the PC-set of the input net. Corresponds to the case where the value is larger than the value.

Fig. 32 shows the algorithm of the " 0 " insertion rule of the PC-set showing such a method.

Generation of the simulation code using the PC-set is to first generate a variable for the value of the net. An array of variables is created for each net, as well as variables with a "0" insertion rule.

34 shows an example in which the variable array is generated, in which the name of the generated variable has the form of N_k, where N represents a net name and k represents an element of a PC-set.

The variable N-k is used by the PC-set of gates to generate a simulation program. The analysis of gates is processed in the order of levels, and the number of syntax of gate simulation is generated by the number of elements of the PC-set of gates. Each simulation statement is performed by taking the value of the gate's input net. Each input net is selected by selecting the value of the largest element of the PC-set. Insertion of "0" ensures that there is the largest element value of the PC-set.

FIG. 35 shows an algorithm for generating a simulation code. The reason why the algorithm is an AND gate having two inputs as an example is for simplicity of explanation, and a method for another type of gate is similar. This can be done through a procedure.

Here, although the PC-set supports an arbitrary delay model, it is mainly a structure and a theory suitable for the unit delay model. As described in the related art, the unit delay model has an advantage in expressing the characteristics of the circuit as compared to the zero delay model. However, there are still problems in verifying the state of complex circuits and correct functioning. Therefore, a random delay model is used to verify complex circuit conditions, and the PC-set also applies an improved EPC-set (Enhanced or Extended PC-set).

The EPC-set algorithm denotes a set with three ordered elements per gate. The first element is the same as the meaning of the PC-set, and the second and third elements mean the path minimum and maximum values of the signal reaching the gate. The value of the PC-set element means the path of the signal from the primary input to the same gate or net-the number of gates.

36 shows an example of an EPC-set.

The EPC-set algorithm starts by assigning a value {(0,0,0)} to the Primary Input. As with the method of obtaining the PC-set, the EPC-set is defined with the elements of the gate after the EPC-set of all input nets of the gate is defined. The EPC-set of the gate is first calculated as the union of the EPC-sets of the input nets. If the first element in the EPC values of the input nets is the same, only one value is accepted and the rest are removed. However, the second element is specified by selecting the minimum value among the second elements among the same first element. Similarly, the third element selects the maximum of the third of the same first element. After the first element has been dealt with, the first element of the EPC-set is increased by 1, and the second and third elements are increased by the delay of the gate to obtain the gate's EPC-set.

Table 1 describes the algorithms for obtaining the EPC-set of the example of FIG. 36 for each step.

Calculation step of EPC-set Step 1 Step 2 Step 2 Step 3 Step 3  A-{(0,0,0)} B-{(0,0,0)} C-{(0,0,0)} D-{(0,0,0)} E-{(0, 0,0)}  G1-{(1,1,1)} G2-{(1,2,2)}                                                   G3-{(1,3,3)}  I1-{(1,1,1)} I2-{(1,2,2)}                                                   I3-{(1,3,3)}  G4-{(1,1,1), (1,2,2), (1,3,3)}  Q-{(2,5,7)}  G4-{(1,1,3)}  G4-{(2,5,7)}

After all the EPC-sets are calculated, the width of the required bitfield is calculated using Equation 1 below.

[Equation 1]

Wi = Mi-mi + 1

Where i is the PC-set value, Mi is the maximum delay length, and mi is the minimum length.

Among the values of W generated by the above operation, the maximum value is the size of the bitfield used for the simulation. All nets and gates use this bitfield because the size of the fixed bitfield is simple and easy to process.

The alignment of the net along with the size of the bitfield is a fundamental requirement of the simulation. This is because the alignment of the net is closely correlated with time. When processing an event on the net, use the value of EPC-set based on the simulator's current time. Therefore, the nets are sorted according to the minimum delay value d of the EPC-Set, and the value of the new net is stored in the bitfield.

However, there is a problem with this procedure. If the aligned time of the current net is larger than the current time, there is a problem that a past value should be generated by the shift operation. However, since it is impossible to generate past information, the EPC-set algorithm added k as a new element, and each k value has the same meaning as in Equation 2 below.

[Formula 2]

ki = min ({mj | j <i})

Here, the ki value has a value that increases with the PC-set value. Similarly, if i> j, Mi <Mj, the problem occurs. In other words, if an event occurs at time j, there is a possibility that the bitfield at time i will disappear. Therefore, when shifting to the left, j information is lost (left shift problem). In order to solve this problem, the EPC-set algorithm is prevented by using the new element Mi and is expressed as Equation 3.

 [Equation 3]

Ki = max ({Mj | j <i})

For the calculation and processing of k and K values, it is easy to see using Table 2 below. Each line illustrates one EPC-Set value, with k and K added.

Example of EPC-set  PC  m M k K One 2 2 2 2 2 7 9 5 9 4 5 6 5 9 8 6 10 6 10 9 8 9 8 10

When simulating the nets and gates of the circuit, the fixed bitfield size is used to represent the time and net values using the shift function. When the gate simulation is performed, the bitfield of the input net of the gate should be aligned with the value ki. This sort can be sorted by the "path-tracing" algorithm, eliminating the left shift.

The path-tracing algorithm performs processing toward the input terminal starting from the gate connected to the output terminal of the circuit. For each PC value i-the first element of the EPC-set-we distinguish among the ki values that the PC value of i-1 is small. At this time, in order to avoid left shift, the k value of the EPC-set should be smaller or larger than ki-d (d is a delay value of the gate). If the k value of such a condition is not satisfied, the element value of the EPC-set is designated as the value of ki-d to satisfy this condition. In addition, in order to prevent the size of the bitfield from expanding, the K value is reduced to the same value. This seems to lose the value of the higher bits, but in reality it is not. Because all bitfields are the same size, and because the m and M values of the EPC-set are propagated on the input nets of the gate, the new Ki can hold all the events of the input net.

37 shows an example of a path tracing algorithm, and the "path tracing" algorithm is performed with k and K values from the output terminal Q. The alignment of output net Q and gate G4 is t = 5 (see Table 1), and the input nets of gate G4 minus the delay value from k of G4, t = 1. On the other hand, the k values of I2 and I2 nets do not change, but the value of I3 must be changed to avoid left shift operation. Therefore, the value of k in I3 should be converted to one. This converted operation is propagated to the input terminal E which is the input net of G3 to convert the k value of E to -2.

Adjustment of the k value for a particular time i is complicated. That is, if one EPC-set is changed at t = i and the rest of the EPC-sets are gates composed of different nets, one of the values of the other nets must be found to be equal to or smaller than i. In addition, if the value of k is changed in the EPC-set element, the property corresponding to the time before this time must be changed to maintain the property that the value of k is not reduced. Therefore, the simulation algorithm using the EPC-set can be expressed as follows. In the event processing simulation method, a program having an input value and an output program are the same and only the changed part is indicated.

Gate_simulation Program: Gate Simulation Program:

Locate EPC-set at time = i

A = k value of EPC-set

3.for all Input net if alignment! = A

Align N = A;

4.R = Simulation function of all Input

5.Scheduling Event with R

Process_Event Program: Event Processing Program:

Locate EPC-set at time = i of net N

A = k value of EPC-set

3. Align N = A

4.Event = Compare N with R

5.If event = 0 discard

else copy N = R

6. Scheduling the fan-out Gate

Table 3 shows the results of the MDP simulation using the EPC-set and path tracing.

Comparison of results Circuit Existing Method (Interactive)  MDP Simulation  Time  Bitfield size Performance improvement rate C432 30.0 seconds 14.1 seconds 8 2.1x C499 30.1 seconds 14.6 seconds 3 2.1x C880 50.2 seconds 32.9 seconds 8 1.5 times C1355 107.0 seconds 62.0 seconds 4 1.7x C1908 206.2 seconds 115.9 seconds 13 1.8x C2670 222.0 seconds 139.2 seconds 11 1.6x C3540 373.0 seconds 208.3 seconds 18 1.8x C5315 595.4 seconds 367.2 seconds 12 1.6x C6288 5666.4 seconds 2663.5 seconds 5 2.1x C7552 962.7 seconds 573.1 seconds 14 1.7x

In this case, the SUN Workstation was used to perform the simulation, and the example circuit used the ISCAS-85 combination circuit example provided by the IEEE Association for benchmark test. This circuit has been used for benchmarking for over a decade and is a good example for performance comparison between research and developers.

The simulation method of the PC-set and the "0" insertion rule is an event-based dynamic scheduling (or oblivious) simulation. The best advantage of this method is that you can pack several input values (PI values) into one word and perform simulation simultaneously. If there is no association between the simulated input and the next input, then a combination of common inputs would be the ideal solution. However, the correlation between successive input values must be taken into account because the consideration of correlation is absolute in the random delay model or the unit delay model. In other words, retrieval of static and dynamic hazards is possible by analysis of successive input values, so the association between successive input values is essential.

FIG. 38 assumes that 16 input values (A, B, C, ..., N, O, P) are added to the circuit diagram in order to explain the above problem, and an example is given. For the sake of simplicity, the method of combining general vectors (i.e. input values) when the length of each word is 4 bits is described. When four input values are composed of one word, the input value F Since the input value becomes the input value B instead of the E, the relationship between the continuous input values cannot be maintained. Therefore, since the combination of general and horizontal input values as in the example circuit of FIG. 37 cannot preserve the association between the input values, the vertical input values as shown in FIG. 38 are used.

 However, there is still a problem, because the relationship between input values D and E, namely (D, E), (H, I), (L, M), can not be preserved.

FIG. 39 illustrates that the continuous association problem of FIG. 38 is solved by adding an input value initially to solve such a problem. The input value packing method uses an initial input value to maintain an association between input values at the beginning of a simulation. After generating and executing, the actual input value is executed.

Since the word size of the system that performs the actual simulation is 32 bits, one additional input value is generated for every 32 input vectors to perform the simulation. Accordingly, by packing the input values as shown in FIG. 39, the execution time of the simulation can be performed by about 32 times faster.

The simulation technique of the present invention described above requires several gate simulation programs per gate. This additional gate simulation program is very time consuming for processing SoCs or large VLSI drawings. In order to reduce such time consumption, a parallel processing method was devised in addition to the simulation method of the present invention.

In the parallel processing scheme, each bit of a word represents a unit time of a simulation, the LSB of a word has a minimum time, the MSB has a maximum time information of a simulation, and each bit has a simulation result.

Fig. 40 shows the structure of the above word, where each bit position represents time, starting with the time t from the position of LSB (bit 0), and the next digit represents time in relation to t + 1 or the like. . The time of the simulation is represented by the size of the bitfield rather than the word unit, and the size of the bitfield is determined by analysis of the circuit diagram (M + 1). Here, the M value represents the time-based net value that each net information should have in the analysis result of the circuit diagram in bit size, and is a bit size required when simulating one vector input.

41 shows an example of a parallel processing method of a gate simulation. As shown in the example circuit, an AND function having an 8-bit size is shown as an input and an output. An AND gate having two inputs has two input net values of t. It is set from = 0, and the output passes through the gate delay (d = 1), and then the simulation result of the gate function is displayed starting with t = 1 on the output net. Each bit represents the AND function result of the corresponding time. Therefore, after the simulation is performed, it is necessary to readjust the bitfields. That is, it is necessary to adjust the start time to t = 0 by performing the bitwise AND, shifting the values of all the bits to the left. Since the value of t = 0 means the time at which the input vector value of the current simulation is input, the value applied to the position of the LSB through the shift function is the result of the previous input vector value corresponding to t = -1.

For this reason, the values of all net bitfields in the circuit diagram must be initialized each time the simulation is carried out. Initialize

Fig. 42 shows adjustment simulation of the bitfield shifted to the left side above.

One gate simulation program is generated for each gate in the level order. The input port is initialized and the net value is initialized before the gate simulation program is executed. In the case of an input port (PI), the input value of the simulation (input vector) is expanded to the position of every bit to specify the input value, while the internal net value of the circuit is the value of the net performed using the previous input vector. The final result is initialized to the LSB position on the net. That is, in the initialization method of the internal net and the output net of the circuit other than the input net, the MSB value of the bit field may be moved to the LSB by the shift operation. This is because the final value of the simulation is stored in the MSB position of the bitfield.

For input nets, use a different method. This means that the net value is set when the input net is t = 0, and the value does not change during the simulation using this input. Therefore, the value of each bit of the bitfield has the same value.

Fig. 43 shows a simple example of the simulation using the parallel processing method. It is assumed that this circuit has already been performed using input values (input vectors) A = 0, B = 1, and C = 1 to explain the operation of the parallel simulation. The new input value (A = 1, B = 1, C = 0) is used to simulate. The bitfield size " M " of this circuit is 2, and the maximum bitfield size is 3. Even if a larger bitfield is used, all the bits of the third and subsequent bits have the same value.

FIG. 44 shows the net value change and the simulation result of the operation of the AND gate corresponding to step 1 in the initial value of the net and the example circuit according to the bitfield position. In addition, the OR gate simulation results in static hazards.

45 shows generated simulation code of the example circuit. The generated code reads an input value and stores an input corresponding to a lower digit of a variable.

In the above method, the elimination of the shift operation further improves the performance of the simulation. The problem of bit field alignment and left shift can be eliminated by using the EPC-set and path-tracing algorithms.

The software for hardware implementation and optimal operation in the present invention is composed of input test function hardware device, gate simulation hardware device, event processing hardware device, and four basic functional blocks.

FIG. 46 shows the overall structure of such a hardware accelerator. For this operation, an internal operation is performed using the above-described parallel processing technique (MDP method).

FIG. 47 shows the internal data structure of the hardware accelerator. The basic information for the operation of the accelerator should be given a gate, a net, and connection information therebetween. The data representation technique used to express this basic information uses a descriptor. Before performing the simulation function, the host computer generates descriptors as a result of analyzing the semiconductor drawings and stores them in the memory of the hardware accelerator. One descriptor is generated for each gate and net of the semiconductor drawing.

The interface between the hardware accelerator and the host computer uses memory based queue operation to perform data exchange and start and end of simulation. Hardware accelerators and host computers operate using host queues, and within the accelerators, use separate universal queues.

The host computer sends the net value of the input end to the accelerator using the host queue.

48 illustrates a data transfer operation of the host queue. The host queue is composed of three elements, a previous value of an input terminal, a current value, and a pointer of a net descriptor. The host queue stores data and is transferred to a hardware accelerator to simulate the data. Will be performed. "Qstart" and "Qend" specify the start and end of the information to be delivered.

Fig. 49 shows the operation between the general purpose queue of the hardware accelerator and the internal device. The operation of the general purpose queue is similar to that of the host queue, and the start and end of the queue are indicated by the pointers of "Qgate" and "Qnet". The start and end of the information is designated as a mechanism for transferring information between the gate simulation device and the event processing device. The gate simulation device and the event processing device (net processing device) are generated as a result of performing the gate simulation using a general-purpose queue. Deliver events from the net using queues.

In the same way, the event processing device delivers the fanout gates generated after the net event processing to the gate simulation device by using the queue, and the termination of the simulation is because there is no further processing if there is no data stored in this general-purpose queue. Will cause an interrupt to the host computer.

FIG. 50 illustrates the basic structures of the gate simulation apparatus, the net verification (event processing) apparatus, and the initialization apparatus among the entire structures of the hardware accelerator for logic simulation of FIG. 46. The structures of the three apparatuses are identical, and Depending on the structure of the program and SUBCIRCUIT, the operation is divided into three parts. That is, the gate simulation device is composed of circuits that SUBCIRCUIT and FIRMWARE are in charge of performing the gate function and storing the result in the general purpose queue, and the net verification (event processing) device is the value processing of the net in the general purpose queue and the net and It is composed of the device to keep the simulation by saving the event processing result in the connected gate processing and the general purpose queue, and the initialization device is also configured in the same structure. When one simulation is finished, the previous net value, alignment value and initial value By using the above basic structure, the following simulation can be performed by repositioning.

In addition, the input device of the overall structure of the hardware accelerator processes the value of the input stage from the host queue and connects to the general queue, and the function that the first event processing apparatus can perform, and the circuit structure of the three It is not as complex as it consists of simple comparators and registers.

As described above, in the method for analyzing the voltage drop and the power consumption value of a semiconductor device according to the present invention, the present invention is not limited by the embodiments and drawings disclosed herein, and various modifications may be made by those skilled in the art within the technical scope of the present invention. Modifications may be made, which should be construed as being included in the scope of the present invention.

 In the high-speed parallel simulation method for design verification of a semiconductor device as described above, by applying a hardware accelerator and optimized software, the design verification speed of the semiconductor device can be increased. For example, the C432.CKT circuit, which is a circuit for benchmarking ISCAS-85, is used. If the hardware accelerator is operated based on 25MHz, it has the ability to process 523,000 events per second, which can process 905,000 gates per second. This hardware accelerator is implemented and verified using HDL, and because the Net Descriptor can be expressed in 32 bits, the maximum processing power is 16,730,000 events per second (29,000,000 gates per second), so all benchmarking circuits compared in Table 3 are 1 second. This can be done in less than five seconds, which is up to 5,600 times faster than software verified.

Claims (9)

In the analysis method for design verification of a semiconductor device, High-speed parallel simulation method using hardware-designed accelerator and analysis method by software that processes event-based simulation in parallel by applying EPC-set algorithm and path-tracing algorithm. The method of claim 1, The EPC-set algorithm recognizes only one value if the first element is equal to the value of the input nets, and removes the rest. The second element selects and specifies the minimum value of the second element among the same first element. The first element selects the maximum value of the third element of the same first element, and when the overlapping first element is processed, the first element of the EPC-set increases by 1, and the second and third elements use the delay value of the gate. Analytical method for design verification of semiconductor device to increase EPC-set value of corresponding gate by increasing by. The method of claim 1, The path-tracing algorithm performs processing in the direction of the input terminal starting from the gate connected to the output terminal of the circuit, and verifies the design of the semiconductor device so that the past information generated by the left shift can be applied to the EPC-set algorithm without being destroyed. Method for analysis. The method of claim 1, And the hardware accelerator comprises an input test function, a gate simulation, an event processing and an initialization device. In the analysis for design verification of a semiconductor device, Hardware acceleration device comprising an input test unit, a gate simulation unit, an event processing unit and an initialization unit. The method of claim 5, The input test unit is a hardware accelerator for processing the value of the input terminal of the analysis target circuit from the host queue to connect to the general purpose queue and the first event processing device can be performed. The method of claim 5, The gate simulation unit is a hardware acceleration device for allowing the accessory circuit and the firmware to perform the gate function, the result stored in the general purpose queue. The method of claim 5, The event processing unit is a hardware acceleration device for the simulation to continue by processing the net value in the universal queue, the processing of the gate connected to the net and the event processing result in the universal queue. The method of claim 5, The initialization unit is a hardware acceleration device that allows the next simulation to be performed by returning the previous net value, the alignment value and the initial value when one simulation is completed.

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