JPH0896016A - Logical simulation method - Google Patents

Abstract

PURPOSE: To provide a logical simulation method which can perform the logical simulation with no pin-to-pin delay error and based on the existing logical connection and a delay data base that covers from an input pin through an output pin. CONSTITUTION: The presence or absence of a remaining event is checked in response to the input change of an input pattern (102). If the presence of a remaining event is decided, this even is taken out (106). A logical operation is carried out through the corresponding gate (107) and it is checked whether an event is generated or not (108). If an event is generated and this event shows the output information, the reference is given to the delay data stored in a delay data base 12 (111). Then the scheduling data are processed based on the delay data (112). The processing is repeated until no remaining event nor remaining scheduling data exist any more. Thus the simulation processing is completed when both remaining event and scheduling data are recognized no more (EXIT 104).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation method, and more particularly to a logic simulation method used as an event driven delay simulation.

[0002]

2. Description of the Related Art In the conventional logic simulation method of this type, as one method, a method of allocating a delay amount to a gate which is a constituent element of an internal logic macro is used. In this logic simulation method, when the delay data from the input pin to the output pin of the internal logic macro is to be reflected in the delay simulation, the delay value is forcibly assigned to each gate, or Moreover, there is no method other than modeling the internal logic macro itself as one large gate and expressing the delay value. In this way, in the method of forcibly allocating the delay value, it is necessary to properly distribute the delay value to the gate, but it is difficult to perform this allocation without error, and Although it is possible to accurately model the delay value of one of the paths, it is difficult to accurately model the other paths, which often results in distortion. It is the actual situation. In order to solve this problem, delay values are conventionally assigned by generating dummy gates. With this method, however, it is necessary to perform logic simulation for the number of dummy gates. There is a problem that

Further, as another conventional method, there is a method of modeling as one large gate. In this method, it is easy to allocate the delay value and the error can be reduced. Although there are advantages, modeling is becoming more difficult as the number of gates of the internal logic macro in the semiconductor integrated circuit is increasing remarkably. As an example of the prior art of this method, Japanese Patent Application Laid-Open No. 3-15
In "2673", a "logic circuit simulator" is proposed. In the proposal by the above-mentioned Japanese Patent Laid-Open Publication, the output value and the delay value of the internal logic macro are all stored in the storage area in the ROM for each combination of input values, and the value of the address of each storage area is stored. A technique is shown in which the logical operation is performed by matching with a binary number expressed by connecting the block number and each input value. Originally, as the internal logic macro, in many cases, the logic connection that was designed and verified before that was diverted as one independent circuit, and the timing part was changed and used, and this modeling method was used. The delay allocation method has the drawback that the logical part must be rewritten. For this reason, the diversion or use of conventional design assets is limited.

A conventional procedure for simulating a logic circuit will be described with reference to FIG. First, in processing step 601, the input pattern signal input to the input pin is changed. Next, in processing step 602, it is checked whether or not there is an event remaining, and if there is a remaining event, the processing moves to processing step 606 and event extraction processing is performed. Also, processing step 60
If there is no remaining event in 2, the presence or absence of schedule data is checked in processing step 603, and if schedule data exists, event registration processing is performed in processing step 605,
Next, in process step 606, the event extraction process is similarly performed. When the event extraction processing is performed in processing step 606, processing step 607
Then, the gate to be operated is specified by referring to the logical connection information, and a predetermined operation process is performed. Next, in processing step 608, it is checked whether or not an event has occurred according to the calculation processing result in processing step 607. If an event has occurred, processing step 609 is performed.
In, the delay value assigned to the gate is referred to, the scheduling process is performed in process step 610, and the process returns to process step 602. If the event does not occur and disappears in processing step 608, scheduling processing is not performed and processing step 60
Return to 2. In this way, the logical simulation is repeatedly processed through the processing steps 602 and 603 until the events and the schedule data are exhausted, and when the events and the schedule data are exhausted, the logical simulation ends ( EXIT 604).

[0005]

In the above-described conventional logic simulation method, in the case of the first method for forcibly assigning the delay value to the gate of the constituent element of the logic macro, the delay There is a drawback that an error is likely to occur in the value allocation, the simulation time increases by the number of dummy gates, and the time required for the logic simulation increases, and in the case of the second method of modeling as one large gate. Has a constraint that modeling becomes difficult as the number of gates increases, and has a drawback that the diversion or use of the logical portion by past design assets is limited.

The problems of the conventional technique will be clarified below by taking the case of the logic circuit shown in FIG. 2 as an example. In FIG. 2, for convenience of description, the reference numerals of the pins are added to the pins, but the pins 1, 2, 3,
The inside of the rectangle surrounded by 7, 8 and 9 is a so-called internal logic macro 22. The four gates that are the constituent elements of the internal logic macro 22 are designated as A, B, C and D, respectively. A delay database from the input pin to the output pin in the internal logic macro 22 is shown in FIG.

In the case of the first method described above, delays are assigned to the respective gates A, B, C and D according to the delay database of FIG. For example, as shown in FIG. 3, in the path 1, the delay value 6 is assigned to the pins 1 to 7, and in the path 2, the delay value 10 is assigned to the pins 1 to 8. In the path 3, the delay value 10 is assigned from the pin 3 to the pin 8. As a result, in the path 4, the delay value should be 6 from the pin 3 to the pin 9, but the delay value is 7 in the delay database, so the dummy gate should be placed between the pin 5 and the pin 9. On insertion, delay 1 is assigned.
This insertion gate requires extra calculation processing in the simulation, and the processing time increases accordingly.

Further, in the second method, when the case of the logic circuit shown in FIG. 2 is treated as an example, description conversion processing for describing four gates as one gate is required. For example, in the case of the proposal according to Japanese Patent Laid-Open No. 3-152673, all combinations of 3 inputs / 3 outputs are RO.
It is necessary to save the data in the storage area in M and to hold the delay data in a form corresponding to each combination.
In other methods, if the connection information of the circuit held as 4 gates is handled as 1 gate,
Inevitably, connection conversion or rewriting will occur, resulting in an increase in processing time.

Therefore, in both the first method and the second method, modeling and conversion become practically difficult as the circuit scale increases. Therefore, in the present invention, it is an object to be solved to realize a pin-to-pin delay simulation based on an existing logical connection and a delay database from an input pin to an output pin.

As a method for realizing the pin-to-pin delay simulation based on the existing logical connection and the delay database from the input pin to the output pin, there is another proposal by Japanese Patent Laid-Open No. 3-250371. However, this proposal has the following problems. That is, JP-A-3-2
In Japanese Patent No. 50371, the time wheels for controlling the event propagation in the internal logic macro and the event propagation between the internal logic macros are individually provided, but this causes an overhead in processing,
The simulation time tends to increase. In addition, although a method of preliminarily storing the delay of the block in the input terminal of the internal logic macro is adopted, it cannot be dealt with as the circuit becomes large and the path becomes complicated,
There is a drawback in that there is a risk that the time required to search for a delay becomes a bottleneck.

According to a logic simulation method of the present invention, a logic circuit model equivalent to a logic circuit is constructed on a computer, and an input test sequence signal for the logic circuit is applied to the logic circuit model to obtain a logic circuit. In a logic simulation method of displaying and outputting the operation result by simulation, it is possible to determine the presence or absence of a residual event in a pin of an internal logic macro included in the logic circuit model, in response to a change in the input test sequence signal. In the processing step and the first processing step, when a residual event exists in the pin of the internal logic macro, a second processing step for extracting the residual event and an event extracted in the second processing step Corresponding to, the target logic in the internal logic macro is referenced by referring to the predetermined logic connection information. A third processing step of performing a calculation process using a road element; determining whether or not an event has occurred due to the calculation process of the third processing step; and returning to the first processing step if no event has occurred When an event occurs in the fourth processing step and the fourth processing step, the pin of the event occurrence is referred to as a pin corresponding to the output pin of the internal logic macro by referring to predetermined BOUNDARY information. Fifth processing step for determining whether or not there is, and in the fifth processing step, when it is determined that the pin is not the output pin of the internal logic macro, the corresponding event is registered and A pin corresponding to the output pin of the internal logic macro in the sixth processing step returning to the first processing step and the fifth processing step. If determined, a seventh processing step of searching for a delay value between corresponding pins by referring to a predetermined delay database, and a scheduling process according to the delay value obtained by the search of the seventh processing step. And at least an eighth processing step of returning to the first processing step after processing while outputting the logical simulation result, and there is no remaining event in the first processing step, and the remaining schedule data If none exists, the process ends.

In the seventh processing step, the delay value between corresponding pins may be retrieved by referring to a predetermined delay database via a hash table.

[0012]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a flow chart showing a processing procedure in an embodiment of the present invention. Hereinafter, for the logic circuit of FIG.
As input signals, the input 1 of FIG. 5A and the input 1 of FIG.
The processing procedure according to the present embodiment will be described by taking as an example the case where the input 2 is applied. In addition, FIG.
(D), (e), (f), (g), (h) and (i)
Are timing diagrams of the signals on pins 1, 2, 3, 4, 5, 6 and 8 corresponding to the application of inputs 1 and 2, respectively, and FIG.
It is a figure which shows the pin table which stores the change time corresponding to 2, 3, 4, 5, 6 and 8, the state value of a pin, BOUNDARY information, and the information of a propagation origin. The BOUNDARY information in this pin table contains the internal logic macro 2
Information including a distinction between two input pins and output pins is stored. In addition, information indicating which input pin of the internal logic macro 22 the latest event has passed through is stored in the propagation source while the simulation is in progress.
In the pin table of FIG. 4, BOUNDARY
In the column, "input" represents the input pin of the internal logic macro 22, "output" represents the output pin, and "-" represents the others. This BOUNDARY information is information obtained by the circuit connection expansion processing which is the preprocessing of the logic simulation.

In the following, referring to FIGS. 1, 2 and 5,
Focusing on the internal logic macro, a simulation procedure by signal application will be described. In the example of the logic circuit shown in FIG. 2, the input 1 and the input 2 are respectively at time T1.
Consider the case where the voltage is applied at (see FIG. 5). As a result, in process step 101, a RISE event occurs at the input pin 1 of the internal logic macro 22 via the inverter 21 at time T1 in response to the application of the input 1 (500 in FIG. 5C). Internal logic macro 2 corresponding to the application of input 2.
At the input pin 2 of No. 2, a RISE event occurs at time T2 (see 501 in FIG. 5D). At this point, in processing step 102, it is checked whether or not an event remains. In this example, time T
Since the RISE event is registered at 1 and time T2, it is determined to be YES, that is, there is a remaining event, and the process proceeds to processing step 106 to perform the event extraction processing. In this case, the R at the earliest time T1
ISE events are retrieved. The propagation destination of this event is given by the logical connection information, but in this example, since the propagation destination is the gate A as is apparent from FIG. 2, in the next processing step 107, the logic gate operation by the gate A is performed. Done. Then process step 10
In 8, the presence / absence of an event is checked. In this example, the input value to the gate A changes from the combination of 0 and 0 to the combination of 0 and 1 due to this RISE event. The result of the calculation is 0, the state value at pin 4 of the gate A does not change, and the event disappears. Therefore, it is determined that the event has not occurred and the process returns to step 102. Next, in the processing step 106, the RISE event at the time delay time T2 is retrieved. In this case, the combination of the input values to the gate A by this event is 1 and 1, and as a result of the arithmetic processing in the processing step 107, the RISE event occurs at the pin 4 at time T3 (FIG. 5 (f)).
502). That is, in process step 108, it is determined that an event has occurred, and the process proceeds to process step 109. In processing step 109, the BUN
Referring to the DARY information, pin 4 is the internal logic macro 22.
Since it is not the output pin of the event, it is determined that the event is not output information, and in process step 110, event registration processing corresponding to the event is performed. In the event registration process, information such as the change time (T3) and the state value change (RISE) is stored, and the change times of the pin 1 and the pin 2 which are the input sources of the gate A are also compared. The pin 2 which is the input source with the later change time is determined to be the trigger of the event of the pin 4, and 2 is stored as the propagation destination of this event. In this case, since pin 2 is an input pin of the internal logic macro 22, it is stored as it is (401 in FIG. 4).
See). Then, the process returns to the process of checking the presence / absence of an event in process step 102.

When it is determined that there is an event remaining in processing step 102, in processing step 106,
The event of pin 4 that has just been registered is taken out, and then in processing step 107, according to the logical connection information,
Although the arithmetic processing by the gate B and the gate D is performed,
By this arithmetic processing, the event disappears without changing the pin 5 of the gate D, and the pin 6 of the gate B changes from 1 to 0 at time T4 (see 503 in FIG. 5 (h)). That is, in process step 108, it is determined that an event has occurred, and the process proceeds to process step 109. In processing step 109, since the pin 6 is not the output pin of the internal logic macro 22 by referring to the BUNDARY information, it is determined that the event is not the output information as in the case described above, and the processing step 110 At, event registration processing corresponding to the event is performed. Since this gate B has one input, pin 6
The fact that the event is triggered by the pin 4 does not need to look at the change time information. As is clear from FIG. 4, since the BUNDARY information of pin 4 is “−”, the number 2 stored in the propagation source information is copied to the propagation source information of pin 6 (see 402 in FIG. 4). .

Then, the process returns to the processing step 102 again,
The existence of the event is checked. In response to the determination that there is an event remaining, in process step 106, the event of the pin 6 that has just been registered is taken out, and then in process step 107, the arithmetic processing by the gate C is performed based on the logical connection information. By this arithmetic processing, the pin 8 of the gate C changes from 0 to 1 at time T5 (see 504 in FIG. 5 (i)). That is, in process step 108, it is determined that an event has occurred, and the process proceeds to process step 109. In the processing step 109, since the pin 8 is the output pin of the internal logic macro 22 by referring to the BUNDARY information (4 in FIG. 4).
03), the event is determined to be output information, and the process proceeds to processing step 111. In processing step 111, the change time of the input source is checked,
It is given from the propagation source information that the trigger of the RISE event of the pin 8 is the event of the pin 6, and the event of the pin 6 is due to the propagation of the event from the pin 2 (see 403 in FIG. 4). Therefore, the delay data from pin 2 to pin 8 is referenced from the delay database. In this case, in the present invention, in order to perform this search at high speed, the delay data is referred to from the delay database 113 via the hash table 112. Next, in processing step 114, the scheduling data is processed according to the delay data, and after the processing, a predetermined simulation result is output.

Then, the process returns to the processing step 102. At this point, however, there is no remaining event and no scheduling data, so that the simulation process ends (EXIT 104).

[0018]

As described above, according to the present invention, a logic circuit model equivalent to a logic circuit is constructed on a computer, an input test sequence signal for the logic circuit is applied to the logic circuit model, and a logic simulation is performed. Applied to the logic simulation method of displaying and outputting the operation result, has the pin progress information of the event propagating in the circuit of the internal logic macro, and corresponds to the propagating event of the output pin of the internal logic macro. Then, a pin-to-pin delay database of the internal logic macro is searched by referring to the pin progress information, and a delay is assigned by referring to the search data, thereby performing a logic simulation that reflects the pin-to-pin delay without error. Can be performed, existing logic circuit connections can be reused, and no additional arithmetic processing is required. In order, there is an effect that it is possible to compress the processing time required for logic simulation.

[Brief description of drawings]

FIG. 1 is a flowchart of logic simulation according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a logic circuit to which this embodiment is applied.

FIG. 3 is a diagram showing an example of a delay database in the present embodiment.

FIG. 4 is a diagram showing a pin information table of an example of a logic circuit to which this embodiment is applied.

FIG. 5 is a timing chart showing the operation of an example of a logic circuit to which this embodiment is applied.

FIG. 6 is a flowchart of a logic simulation in a conventional example.

[Explanation of symbols]

 11 Hash Table 12 Delay Database 21 Inverter 22 Internal Logic Macro 101-112, 601-610 Processing Steps

Claims (2)

[Claims] 1. A logic simulation in which a logic circuit model equivalent to a logic circuit is constructed on a computer, an input test sequence signal for the logic circuit is applied to the logic circuit model, and the operation result is displayed and output by a logic simulation. In the method, in response to a change in the input test sequence signal, a first processing step of determining the presence / absence of a residual event in a pin of an internal logic macro included in the logic circuit model; and the first processing step, When there is a remaining event in the pin of the internal logic macro, the predetermined logical connection information is referred to in correspondence with the second processing step of extracting the remaining event and the event extracted in the second processing step. And a third processing step of performing arithmetic processing by the target logic circuit element in the internal logic macro, A fourth processing step of determining whether or not an event has occurred by the arithmetic processing of the third processing step, and returning to the first processing step when no event has occurred; and an event in the fourth processing step. And a predetermined BOUNDARY information is referred to, it is determined whether or not the pin of the event occurrence is a pin corresponding to the output pin of the internal logic macro. A sixth processing step in which, when it is determined in the fifth processing step that the pin is not the pin corresponding to the output pin of the internal logic macro, the corresponding event is registered and the process returns to the first processing step; When it is determined in the fifth processing step that the pin corresponds to the output pin of the internal logic macro,
A seventh processing step of searching for a delay value between corresponding pins by referring to a predetermined delay database, and a scheduling processing according to the delay value obtained by the search of the seventh processing step to obtain a logic simulation result. An eighth processing step that outputs the data and returns to the first processing step after processing; and, in the case where there is no remaining event in the first processing step and there is no remaining schedule data, Is a logic simulation method that terminates processing. 2. The logic simulation method according to claim 1, wherein in the seventh processing step, a delay value between corresponding pins is searched by referring to a predetermined delay database via a hash table.