JPH02122337A - Accelerator - Google Patents

Abstract

PURPOSE:To realize a logical simulation approximate to an actual circuit action by setting the different delay times at every different simulation subject for an accelerator which performs the logical simulation applying an event-driven system. CONSTITUTION:A simulation part 7 performs the logical simulation of a logic circuit with use of the information on its own logic circuit in an event-driven system and at a gate or element level. In this logical simulation, an input pattern is supplied to the part 7 from an input part 6 and an output pattern is outputted and stored in an output part 8 as a result from the part 7. The part 7 performs the logical simulation by reference to the delay time stored in a memory part 9. In other words, the delay time is obtained for the corresponding event and the generation of the event is delayed by an extent equal to the delay time. Thus an approximately actual circuit action is obtained as the simulation result.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to an accelerator that executes event-driven logical simulation in hardware.

By making the delay time variable, the aim is to enable logic simulations that are close to actual circuit operations.

An accelerator that performs event-driven logic simulation of a logic circuit includes an input section that stores an input pattern, a simulation section that stores information about the logic circuit, an output section that stores an output pattern, and an output section that stores an output pattern of the logic circuit. and a memory section for storing the delay time obtained from the logic circuit for each of the elements, and the simulation section obtains the delay time obtained by referring to the memory section in the case where the input pattern is input to the logic circuit. Perform element-level logic simulation using delay time.

The result is configured to be stored in the output section as the output pattern.

[Industrial application field]

The present invention relates to an accelerator, and more particularly to an accelerator that executes event-driven logic simulation in hardware.

During logic design, logic simulation is performed to verify the logical behavior of the designed circuit.

[Conventional technology]

Logic simulation has conventionally been performed using software. However, as the scale of the simulation increases, there is a problem in that the execution time for software processing becomes too long.

Therefore, a dedicated processing device using hardware, ie, an accelerator, has been developed and is mainly used in large-scale simulations. In order to perform high-speed processing with a simple configuration, many accelerators use an event-driven algorithm as their algorithm. According to this method, logic simulation is performed by repeatedly transmitting information about a gate where an event has occurred to the next gate.

[Problem to be solved by the invention]

In the above-mentioned accelerator, zero-delay simulation and/or unit delay simulation has conventionally been performed. The former is a method in which the delay time at each gate in the circuit to be simulated is set to zero in advance, and the latter is a method in which a (unit) delay time is given to each gate in advance.

However, in actual circuits, it is impossible for the delay time to be zero or to be a single delay time.

That is, the delay time of the gate varies depending on, for example, whether the change in the signal is a rising edge or a falling edge.

It also varies depending on the wiring length of the signal line.

Therefore, the above-mentioned accelerator has a problem in that it is not possible to simulate the details of the circuit operation, especially the timing relationship. Also.

It still takes software software to handle different delay times.
There was a problem that a simulator had to be used and the processing time was long.

An object of the present invention is to restore an accelerator that enables logic simulation close to actual circuit operation by making the delay time variable.

[Means to solve the problem]

FIG. 1 is a basic configuration diagram of the present invention, and shows an accelerator and EWS according to the present invention.

In Figure 1, 1 is an engineering workstation (EWS) and 2 is an accelerator.

3 is a central processing unit, 4 is a control processor, 5 is a bus control section, 6 is an input section, 7 is a simulation section, 8 is an output section,
9 is a memory section.

Accelerator Lake or Simulation Processor (SP
) 2 is hardware added to EWS 1,
Logic simulation is performed using an event-driven method for a certain logic circuit as a target of logic simulation.

For this purpose, the input unit or input processor (IP) 6
An input pattern (waveform diagram) input to the logic circuit for logic simulation is stored.

A simulation unit or gate processor (GP) 7 performs event-driven simulation at the element level and stores information about the logic circuit. This information is.

For example, it includes circuit connection (wire connection) information of the logic circuit, element function information, and the like.

An output unit or output processor (OP) 8 stores an output pattern (waveform diagram) for the input pattern of the logic circuit as a result of logic simulation.

A memory section 9 is provided in the simulation section 7 and stores the delay times of each of the elements of the logic circuit in a table format. This delay time is determined by the configuration of the logic circuit (wiring length of the signal line).

For each of the input terminal and output terminal of each element, cases in which the signal waveform is rising and falling are determined and stored in advance based on the type of element, etc.

Note that the central processing unit 3 of the EWSI is an accelerator 2.
The host processor has data regarding the logic circuit in a file (not shown). Then, based on the data, the central processing unit 3 creates information about the logic circuit to obtain the delay time, and the accelerator 2
Send to.

Further, the central processing unit 3 sends the large pattern to the accelerator 2 and takes in the output pattern sent from the accelerator 2.

Transmission and reception of data between the central processing unit 3 and the accelerator 2 is mainly performed by the control processor 4 via the control processor (CP) 4 and the bus control section 5.

[Effect]

The simulation unit 7 uses the information about the logic circuit that it owns to perform logic simulation of the logic circuit in an event-driven manner.
For example, this is done at the gate or element level. That is, gates or elements (in which an event occurs in which a change in input and/or output occurs) are evaluated at five time steps according to the time wheel.

In this logic simulation, an input pattern is supplied from an input section 6 to a simulation section 7, and an output pattern as a result is outputted from the simulation section 7 to an output section 8 and stored therein. That is.

Logic simulation is performed for the case where the human pattern is input to the logic circuit, and an output pattern corresponding to the input pattern is obtained.

The simulation unit 7 performs this logic simulation by referring to the delay time stored in the memory unit 9. When an event occurs in a gate or an element at a certain time step, the simulation unit 7 searches the memory unit 9 and performs the logic simulation. , find the delay time for that event. That is, the delay time is determined from the table based on what kind of change (rising or falling) occurred for which terminal (input or output terminal) of which gate or element. For this purpose, the table in the memory unit 9 stores delay times for all possible events.

The simulation unit 7 delays the occurrence of the event by the calculated delay time.

As a result, the output pattern becomes very close to the actual circuit operation when the input pattern is input to the logic circuit, and it becomes possible to simulate the circuit operation in detail, such as timing relationships.

When performing logic simulation for other logic circuits,
Prior to this, the table in the memory section 9 is updated.

That is, the delay times for all events that may occur in the other logic circuit are newly determined. A logic simulation is then performed with reference to the contents of this new table.

Therefore, by setting different delay times for different simulation targets, the hardware accelerator 2 can perform high-speed logic simulation.

〔Example〕

FIG. 2 is a block diagram of an embodiment, showing an accelerator.

In FIG. 2, 6 is an input pattern sending section, and the input section 6
61 is an input pattern section.

62 is an input pattern memory. 71 is a change net pursuit section, 72 is an evaluation gate pursuit section, 73 is a gate output evaluation section, and 74 is an output event schedule section, which constitutes the simulation section 7. 711 is a net value control section;
12 is a net value memory.

721 is a connection gate pursuit section, 722 is a circuit connection information memory, 723 is an input delay pursuit section, 731 is a gate evaluation section, and 732 is a gate function memory. 91 is an input rise/fall delay memory, and 92 is an output rise/fall delay memory, which correspond to the memory section 9. 8 is an output pattern storage section which corresponds to an output section, 81 is an output pattern section, and 82 is an output pattern memory.

The input pattern section 61 stores the large pattern transmitted from the EWSI via the control processor in the manual pattern memory 62, and also stores (changes in) the input pattern for each step time.
is read out from the input pattern memory 62 and sent to the change net pursuit section 71. The input pattern memory 62 stores the large pattern as a relationship between (change in) input signal level and step time.

The change net pursuit unit 71 searches for a change net.

That is, based on the input pattern at a certain step time from the input pattern section 61 and the event memory (not shown), the net value control section 711 extracts a net that changes at that time and defines it as a changing net. At the same time, the net value memory 712 is rewritten according to this change. Net value memory 712 stores the state of each net at a predetermined step time.

The evaluation gate pursuit unit 72 determines the gate (or element) to be evaluated based on the change net from the net value control unit 711.
Find the set of and the input delay for each of them.

That is, the connection gate pursuit unit 721 refers to the circuit connection information stored in the two-circuit connection information memory 722 to find a set of gates connected to the changed net, that is, a gate to be evaluated. The input delay pursuit unit 723 searches the input rise/fall delay memory 9 according to the change net.
1, find the input delay time for each gate to be evaluated, and calculate this as the input delay time.
Stored in a stack (not shown).

The gate output evaluation unit 73 determines when the output of the gate to be evaluated changes based on the contents of the net value memory 712, the gate to be evaluated from the evaluation gate pursuit unit 72, and the input delay time from the input delay stack. seek. That is, the gate evaluation section 731.

Referring to the gate function information stored in the gate function memory 732, determine whether there is a change in the output of the gate to be evaluated and whether the change is rising or falling, and then determine the output rising or falling based on this. With reference to the delay time stored in the downlink delay memory 92, the output delay time of the relevant output is determined. on the other hand.

The gate evaluation unit 731 determines when the output changes based on the change net in the net value memory 712.

The output event schedule section 74 feeds back the results obtained by the gate output evaluation section 73 (scheduled change net and expected change time) to the input pattern, and sends it to the output pattern storage section 8 as an output pattern.

The output pattern unit 81 stores (changes in) the output pattern for each step time in the output pattern memory 82, and also retrieves the output pattern from the output pattern memory 82 and stores it in the EWS 1.
is sent to the control processor 4 through the control processor 4.

Example of Simulation (Object of Simulation, etc.) FIG. 3(A) shows a logic circuit that is the object of simulation. In the figure, Gl is a two-man-powered OR gate, and G2 is a three-man-powered AND gate. Each terminal of gates CI and G2 is represented by symbols a to e as shown in the figure.

FIG. 3(B) shows an input pattern input to the logic circuit shown in FIG. 3(A). Signals applied to terminals a to C are represented by signals a to C. Signals a to C are expressed using step time Δt as a basic unit, as shown in FIG.

(Processing of EWSI and accelerator 2) fll First, preprocessing is performed in EWSI.

That is, EWSI creates one circuit connection information and gate function information from a logic circuit input in the form of one circuit diagram, and creates 9 pieces of information for each circuit.
Circuit connection information memory 722 and gate function memory 732
Store in. In addition, EWSl calculates the rise and fall delay times for each terminal a to e, and
, c and d (inputs of gate G2) are stored in an input rise/fall re-delay memory 91, and terminals d (outputs of gate Gl) and e are stored in an output rise/fall re-delay memory 92.

(2) Next, the accelerator 2 performs simulation, that is, the input pattern from the ESWI is stored in the input pattern memory 62. Then, simulation is performed using the input pattern sent out every step time Δ, and the resulting output patterns for every step time Δ, that is, signals d and e are stored in the output pattern memory 82.

(3) Next, post-processing is performed in EWSl.

That is, the EWSI takes in the contents of the output pattern memory 82 and displays them on the screen together with the input pattern as a time chart.

(Details of Processing of Accelerator 2) The processing (2) will be further explained using FIG. 5. Note that FIG. 5 shows the state of the accelerator 2 at the time the simulation ends.

■ The initial state of the accelerator 2 is as described above (.

Provided by EWSI (host processor 3).

For example, circuit connection information such as "The gate Gl inputs the signals S and C and outputs the signal d" and gate function information such as "The function of the gate Gl is OR" are given. Further, for example, a delay time is given such that the terminal of G1 has a delay time of 2Δt at the rising edge and lΔt at the falling edge. As a result, as an initial state,
It can be said that a simulation model as shown in FIG. 4 is constructed. In addition.

In FIG. 4, for example, "2Δt/lΔt" indicates that the delay times at the rising edge and the falling edge are 2Δ and lΔt.

■ The input pattern is stored in the input pattern memory 62.

At this time, the signal a changes from "0" to "1'" at one time t1, and the signal a changes from "0" to "1" at one time t2.

It is stored as follows.

As a result, the portion corresponding to one time t to t6 in the column of the input pattern sending section in FIG. 5 is obtained.

(2) Based on (changes in) the input pattern from the input pattern sending unit 6, the change net pursuit unit 71 finds a change net, that is, a set of terminals whose levels have changed.

Modify net value memory 712. Since there are terminals a to e, the net to pursue is (a, b, c, d
, e).

As shown in the column of change net pursuit section in Figure 5.

The net value memory 712 at time t1 is in the initial state B (
0, O, O, x, x) to (1, 0, O.

x, x), and the net value memory 712 at time t2 is in the state (1, 0, O.

x, x) to (1, l, 0.x, x). Here, rxJ represents indeterminacy, and the change net is 9 times 1. At time t2, a(0-1) becomes b(0→1
).

■ By the change net from the change net pursuit department 71,
The evaluation gate pursuit unit 72 determines the gate connected to the changed net and the input delay time corresponding to the gate.

As shown in the evaluation gate pursuit section column of FIG.

At time t, since there is a rising (0→1) input to gate G2 connected to terminal (net) a, the input delay time is required to be 2Δt. Also 2
At time t2.

Since there is a rising (0-1) input for the gates CI and G2 connected to the terminals, the input delay time of each is required to be 2Δt.

(2) Evaluation Based on the results obtained by the gate pursuit section and the contents of the net value memory 712, the gate output evaluation section 73 determines whether or not there is a change in the output of the gate and the expected change time.

As shown in the column of gate output evaluation section in FIG.

At time t1, gate G2 is an AND gate and the net value is (a, b, c, de) = (1, 0,
0, x, x), so the output of gate G2 (net)
It is required that e does not change. Note that the output delay time is set to 2Δt because the output is 0'' at this time and has fallen first.Furthermore, at time t2, the output of gate G2 does not change for almost the same reason. However, an output change occurs in gate Gl. That is, gate Gl is an OR gate and the net value is (1, 1, 0,
x,
Since the input delay time is 2Δt and the output delay time is 3Δt, it can be determined that the expected change time is 5Δt (t, +5Δt) after t8.

(2) The output event schedule section 74 outputs the above results to the output pattern memory 82 and the input pattern memory 62.

As shown in the column of the output event schedule section of FIG. 5, at time t 2, it is written in the output pattern memory 82 that there is no change in the output even though there is a change in the input to the gate G2. At time t2, it is written in the output pattern memory 82 that there is no change in the output of gate G2, and that the output d of gate Gl changes to z-hl after 5Δ.

On the other hand, since the output d of the gate Gl is the input d of the gate G2, the signal (net) d changes from "X" to "l" at time t2+5Δt, as shown in the column of input and output section in FIG. ” is stored in the input pattern memory 62. This allows the event to be extracted as a new event at one time t2+5Δt. Note that new events are stored in the order of occurrence time.

Processes (1) to (2) are repeated for each time t1 to [, respectively. Furthermore, as a result of this, the newly stored times t2+5Δ1, 1 . Similarly, for +8Δt, tS+5Δ, and t, +2Δt, process ■ or ■
is performed repeatedly.

The execution order is the order of occurrence time of the event. In addition.

Changes in the signal e at times t2+8Δ and t, +5Δt are also set in the input pattern memory 62 as events.

As a result of the above, the output pattern memory 82 has 5 time tz+5.
At ΔL, the signal d changes to “1” and becomes 1 time Lx.
At +8Δt, the signal e changes from “X” to “1” and at time 2
, +5Δt, the signal e changes from “1” to “0”, and at time 2 t&+2Δt, the signal d changes from “1” to “0”.

Thereafter, by performing the above-mentioned process (3), a time chart screen as shown in FIG. 6 is obtained as a simulation result. Note that in this simulation, the step time Δt, which is the minimum unit of one hour, is the greatest common divisor of the delay times of the rise and fall of the input and output of each gate. Thereby, substantially actual circuit operation can be obtained as a simulation result.

〔Effect of the invention〕

As explained above, according to the present invention, different delay times can be set for different simulation targets in an accelerator that performs event-driven logic simulation.

Hardware accelerators allow high-speed logic simulations that closely resemble actual circuit operations.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention Fy1. FIG. 2 is a diagram showing the configuration of an embodiment. FIG. 3 is a diagram showing simulation objects, etc. FIG. 4 is a diagram showing a simulation model. FIG. 5 shows the state of the accelerator, and FIG. 6 shows the simulation results. 1 is an engineering workstation (Ews),
2 is an accelerator, and 3 is a central processing unit. 4 is a control processor, 5 is a bus control section, 6 is an input section, 7
8 is a simulation section, 8 is an output section, and 9 is a memory section. Patent applicant Pfn Co., Ltd.

Claims (1)

[Claims] An accelerator (2) that performs event-driven logic simulation of a logic circuit, comprising: an input section (6) that stores an input pattern; and a simulation section (7) that stores information about the logic circuit. and an output section (8) that stores an output pattern; and a memory section (9) that stores delay times obtained from the logic circuit for each of the elements of the logic circuit, the simulation section (7) However, when the input pattern is input to the logic circuit, the memory section (9
), the accelerator performs a logic simulation at an element level using the delay time obtained by referring to the above, and stores the result in the output section (8) as the output pattern.