JPH10340283A - Method and device for designing and verifying lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the reliability of design and to make flexibly adaptable to specification alternations by designing a circuit of RT level from specifications of algorithm level and verifying it through a consistent data base. SOLUTION: When specifications of an LSI are give, a data flow is analyzed on the basis of them and division candidates for the circuit are listed (S1 to S3). Functional inspection is performed according to them to estimate its hardware and also device that the circuit is to be divided (S4 to S6). According to the decision result, actual division is performed (S7) and then subdivision is also performed (S2). When the designer decides that the circuit is not subdivided any more, the final division results are converted into a hardware description language (S8) and the description language of RT(register transfer) level is outputted (S9). On the basis of the estimation result of the hardware, restriction conditions at the time of logical synthesis are outputted (S10). Thus, the processes are performed consistently.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for verifying an LSI design, and more particularly, to inputting and verifying specifications from an algorithm design stage in an initial stage of LSI design, and to register transfer level based on these data. (RT level) LS output circuit
The present invention relates to an I design verification method and apparatus.

[0002]

2. Description of the Related Art Conventionally, in LSI design, it takes enormous cost and time to manufacture an actual circuit. Therefore, cut and try is not allowed, and it is necessary to reliably suppress from the specification to the final circuit at the design level. .

For this reason, in LSI design, at the algorithm level, circuit specifications are described in C language, and this is verified on a computer. Then, based on this specification,
The circuit is manually designed using the description at the RT level.

[0004] The above-described LSI design techniques include, for example,
It is disclosed in JP-A-5-181925.

On the other hand, in the LSI design stage, there is rarely a situation where specification changes do not occur at all. In some cases, specification changes cannot be avoided depending on the relationship with external circuits and devices, customer requirements, and the like.

In such a case, it is possible to add or change a circuit from the outside by dividing the circuit block efficiently. Such a design method is disclosed in, for example, Japanese Patent Application Laid-Open No. 5-25037.

[0007]

According to the conventional LSI design verification method, as described above, the reliability of the design is improved by performing verification at the algorithm level in the initial stage, and the specification is performed by a circuit block construction method. Although it is possible to cope with the change, the following problems remain.

[0008] The description conversion from the specification to the RT level requires manual intervention, so that the conversion process is unclear. For this reason, if a specification change occurs after conversion to the RT level, it cannot be dealt with.

[0009] Further, since the quality of the description at the RT level depends on the skill of the designer, the reliability is poor and errors easily occur.

[0010] In addition, the circuit is also verified at the specification stage,
Since the verification at the RT level and the verification at the RT level are performed individually, they are discontinuous, unrelated, and poor in reusability.

For this reason, despite the method of introducing a mechanical design into an LSI design, and evaluating and verifying the design while proceeding with the design, due to human intervention and process discontinuity, the reliability of the design has been reduced. There is a limit to the performance, and problems remain from the viewpoint of shortening the design period.

The present invention solves the above-mentioned problems of the prior art, and designs and verifies an RT-level circuit from an algorithm-level specification based on a consistent database. The purpose of the present invention is to provide an LSI design verification method that can improve the design reliability, can flexibly respond to specification changes, and can shorten the design period by being able to try the description at the RT level. I do.

[0013]

To achieve the above object, the present invention provides a first step of inputting an algorithm level specification, a second step of analyzing a data flow based on the specification, A third step of listing division candidates based on the analysis result in the second step, a fourth step of performing function verification based on the candidates listed in the third step, and a third step. A fifth step of estimating hardware based on the enumerated candidates, and a sixth step of judging whether it is necessary to divide the specification into functional blocks based on the results of the function verification and the hardware estimation.
And, if the judgment in the fourth step is to divide, a seventh step of dividing and then passing the result to the second step. It is.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention.
5 is a flowchart of a process for explaining an SI design verification method.

First, when an LSI specification is given in step S1, a data flow is analyzed in step S2 based on the specification. In step S3, circuit division candidates are listed. Based on this, function verification is performed in step S4, and hardware estimation is performed in step S5. At the same time, in step S6, a decision to divide the circuit is made.

Then, based on the result of the determination, after the division is actually performed in step S7, the flow returns to step S2, and the flow is to perform further division.

If the designer's selection in step S6 is that there is no further circuit division, the final division result is converted into a hardware description language in step S8, and the RT (register transfer) level description language is used. To step S
Output at 9.

Then, based on the result of the hardware estimation performed in step S5, a constraint condition at the time of logic synthesis is output in step S10.

As described above, in this embodiment, the specification division is determined and the actual division is performed based on the results of the data flow analysis, the function verification, and the hardware estimation, and the data flow analysis is further performed based on the determination. And circuit conversion by hardware estimation, and based on the final division result,
Since the hardware description language is output, the processing is performed consistently, the design reliability and design efficiency are improved, the specification can be flexibly dealt with, and the design period can be shortened.

FIG. 2 is an explanatory diagram showing an example of a case where a certain specification is divided. FIG. 7A shows a process of dividing the specification, and FIG. 6B shows a state transition of the data structure in each layer corresponding to the division of the specification.

Now, as shown in FIG.
Is divided into two blocks A and B, and block A
Is further divided into blocks C, D, and E, and the block B is further divided into blocks F and G, and the block E is further divided into H, I, and two blocks. That is, FIG. 2A shows the process of specification division, and each node shows a functional block that performs a certain process. The parent-child relationship of the nodes indicates the state before and after the division, and the specification given initially is finally divided into six functional blocks of C, D, H, I, F, and G Will be.

On the other hand, as shown in FIG. 1B, when dividing the functional block FB, a state transition of the data structure occurs. For this reason, processing and data are transferred between the functional blocks, and the conditions and states are indicated by arrows in FIG.

FIG. 3 is a detailed description of routines for data flow analysis, function verification, and hardware estimation, including how to give information to a designer.

First, in the data flow analysis, a location where the flow of data is sparse is searched for and output as a candidate for a division location.

For this purpose, for a certain functional block,
The internal function is displayed in a state transition diagram as shown in FIG. 2 (B), and the process flow of the functional block is captured, and a portion where the data flow is sparse is set as a divisible portion candidate as shown in FIG. Is displayed as a dotted line DL.

Next, when the division is actually made at the division candidate, whether or not the circuits are functionally equivalent before and after the division is verified. As a result, if it is determined that the circuits before and after the division in a certain candidate are not functionally equivalent, the division is deleted from the candidates.

Next, hardware estimation is performed. As shown in FIG. 3, the function block FB in the case where division is actually performed at a dividable candidate portion is displayed by surrounding it with a dotted line. This is done by displaying the area and processing speed of each functional block at that time.

As shown in FIG. 3, the data can be provided to the designer by the data flow analysis and the hardware estimation as described above, so that rational specification division can be performed irrespective of the skill and individuality of the designer. it can. In addition, since the result of specification division can be output immediately by simulation, it is possible to prompt a reliable determination.

Next, when a specification change occurs during the processing, functional block division as shown in FIG. 4 is performed. First, it is assumed that functional blocks are divided in a tree structure as shown in FIG.

Then, if a specification change such that the function block E is changed to E 'is entered on the way, this influence also spreads to the function blocks H and I having the function block E as a parent.
However, the effect may be considered only in the portion surrounded by the dotted line.

Then, based on the functional block E ', specification division is performed as shown in FIG. 3B, and division into three functional blocks J, K, and L with E' as a parent is performed. This operation is also performed only in the portion surrounded by the dotted line in FIG.

That is, by replacing the portion surrounded by the dotted line in FIG. 4A with the portion surrounded by the dotted line in FIG. 4B, the response to the specification change is completed.

According to the present technique, since the circuit is divided while maintaining the hierarchical structure, the function verification may be performed only on the changed part, and it is not necessary to verify the entire circuit.

There is a trade-off decision as to whether the emphasis is always on processing speed (type TP1) or chip area (type TP2) in LSI circuit design. The functional block division in this case is shown in the explanatory diagram of FIG.

First, the specification is divided into two functional blocks A and B, which are further divided into three functional blocks C, D and E, respectively.
It is assumed that the function block is divided into one functional block and two functional blocks F and G.

Now, the function block E has a processing speed of 4
0 means that there is a portion where resources can be shared, and there is a possibility that the chip area may be reduced.

When the processing speed is emphasized, the functional block E is parallel-processed P and divided into two functional blocks H and I at the processing speed 20.

As a result, functional blocks are divided with emphasis on processing speed.

On the other hand, in the case where the chip area is emphasized, it is more reasonable to perform resource sharing of these functional blocks E and remove unnecessary circuits in this portion, rather than dividing the functional blocks E into H and I. Therefore, the reduction of the chip area is selected without dividing the functional block E.

As described above, even in the case of a trade-off, the data flow analysis and the hardware estimation can be easily performed in each process of division into functional blocks, so that the time required for the determination is short. A reliable decision can be made.

As described above, in dividing the specifications,
The simulation of the data flow and the estimation of the hardware at each division level are simulated, and the verification based on this is performed, so that the designer can reliably determine the specification division, and the specification division at each level is also possible. By storing the verification results in a database, the validity of the division results can be judged by comparing the verification results, and furthermore, it is possible to easily deal with specification changes and there is a trade-off However, since a reliable judgment can be made, the efficiency in LSI design is remarkably improved, and the design reliability is greatly improved by verification in each process.

[0042]

As described above, according to the present invention, the specification, R
Since the T-level design and its verification are configured to be performed continuously, it is effective in shortening the LSI design period, and can easily deal with changes in the specification level.
Furthermore, when several RT-level circuits are created and the optimal circuit is selected by trial and error in terms of performance, area, etc., this can be executed quickly, and in a consistent process, Since the results can be left in the form of a database or a diagram of the results of circuit division, there are various effects that the concept of the design process can be easily understood.

[Brief description of the drawings]

FIG. 1 is a process flow chart for explaining an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of a case where a certain specification is divided.

FIG. 3 is an explanatory diagram showing in detail a routine for data flow analysis and hardware estimation.

FIG. 4 is an explanatory diagram of a processing method when a specification change occurs during processing.

FIG. 5 is an explanatory diagram of division of functional blocks when making a trade-off determination.

Claims (8)

[Claims] 1. A first method for inputting an algorithm-level specification.
A second step of analyzing a data flow based on the specification; a third step of listing division candidates based on an analysis result in the second step; and a second step of listing in the third step A fourth step of performing a function verification based on the candidates obtained, a fifth step of estimating hardware based on the candidates enumerated in the third step, and based on the results of the function verification and the hardware estimation. A sixth step of determining whether it is necessary to divide the specification into functional blocks; and, if the determination in the fourth step is to divide, a seventh step of dividing and passing to the second step. An LSI design verification method, comprising: 2. The LSI design verification method according to claim 1, wherein a sparse portion of the data flow is searched and output in the second step. 3. The LSI design verification method according to claim 1, wherein in the fifth step, the circuit performance of the divided functional blocks is estimated and output. 4. The method according to claim 1, wherein in the fifth step, a constraint condition at the time of logic synthesis is output.
SI design verification method. 5. The LSI design verification method according to claim 1, wherein a result of said data flow analysis or a result of said hardware estimation is output by drawing display and data display. 6. The LSI design verification method according to claim 1, wherein the specification is input using a graphic. 7. A means for designing a register transfer level circuit while inputting and verifying an algorithm level specification, and a means for hierarchically dividing the algorithm level specification into a register transfer level. A means for displaying, in each figure of the division process, parts that can be divided in a graphic and providing information as a criterion for determining whether to divide, and a means for verifying the function of the division result of each layer. An LSI design verification device, comprising: 8. The LSI design verification device according to claim 7, wherein the input of the specification is performed using a graphic.