JPH11145295A - Automatic disposing and wiring method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a disposition and a wiring in which results of delay simulations before and after the automatic disposition and wiring conform to each other by a method wherein a delay of a critical path in a net list is set and also a type of block using at a time of the automatic disposition and wiring is determined based on values of a delay designated file. SOLUTION: Counting from AAA of a start point 20 designated in a delay designation file, an inverter 21 of a first stage is disposed, and continuously a NAND group 28 of a second stage is disposed. In the NAND group 28, there are a NAND 22 for a critical path block symbol and a plurality of NANDs 24. The first stage is connected to the second stage via a wiring 29. A wiring load is calculated from the wiring 29, and by the sum of input capacity at the next stage, a block selection table is retrieved and a block type satisfying values of the delay designation file is determined. The delay designation file is optimized for a designated set value. Thereby, delay values before and after an automatic disposition and wiring can conform to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to automatic placement and routing of integrated circuits, and more particularly, to an automatic placement and routing method in which a delay value in automatic placement and routing is adjusted.

[0002]

2. Description of the Related Art FIG. 5 is a flowchart showing an example of a conventional circuit design to automatic placement and routing. Traditionally,
From the net list 6 of the circuit designed in the circuit design and pattern design (step 1), a tentative wiring length is calculated as a predicted value of a wiring to be laid by automatic placement and routing (step 2). In the delay simulation (step 4),
A delay simulation is performed using the wiring delay obtained from the provisional wiring length and the delay library 18 and netlist 6 of each block. Next, the delay simulation is verified (Step 5). If there is a problem with the delay simulation result in Step 4, Step 1 is performed.
The circuit design is performed again, and if there is no problem, the process proceeds to the next step of automatic placement and routing.

A delay simulation is performed using the wiring delay obtained from the actual wiring data 10 obtained after the automatic placement and routing (step 9) and the delay library of each block (step 15). Next, the result of the delay simulation is verified (step 16). If the result is different from the verification result of step 5, it is determined whether or not the layout and wiring can be corrected (step 17). The process returns to the automatic placement and routing (step 9) as a modification of the layout after the wiring, or if not possible, returns to the circuit design and pattern design (step 1) to perform the circuit correction. In this way, the design value was satisfied.

[0004]

In the above-mentioned conventional example,
In the design of the integrated circuit, the automatic placement and routing is not performed so as to be the same as the temporary wiring length used in the delay simulation before the automatic placement and routing. Therefore, there is a problem that the delay simulation results before and after the automatic placement and routing are different.

Further, when the ratio of the number of used elements in the chip is large, it is difficult to change the arrangement position of the block which has been arranged once. There is no surrounding space and it cannot be replaced simply, so the arrangement of the surrounding blocks must be changed. Further, when it is difficult to change the arrangement and wiring, it is necessary to execute the automatic arrangement and wiring again to cope with it. Therefore, in order to satisfy the design values, it is necessary to correct the placement and wiring after automatic placement and routing, and part or all of the wiring. A return flow such as re-execution of wiring is indispensable, which leads to an increase in design and development time.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an automatic placement and routing method capable of performing placement and routing without any difference in delay simulation results before and after automatic placement and routing.

It is another object of the present invention to provide an automatic placement and routing method which does not require placement and routing correction and circuit correction after automatic placement and routing.

[0008]

To achieve the above object, an automatic placement and routing method according to the present invention comprises the steps of: reading a netlist to calculate a temporary wiring length; and performing a delay simulation using the temporary wiring length. In the automatic placement and routing method including the steps of reading a netlist and performing an automatic placement front, a delay specification file is created, a critical path delay in the netlist is set, and a value of the delay specification file is used. It is characterized in that the type of block used at the time of automatic placement and routing is determined.

Further, when determining the type of a block used at the time of automatic placement and routing, a block selection table is used to determine
It is preferable to determine which block to use.

Further, it is preferable that the block selection table generates in advance a plurality of blocks having different capacities for one functional block, and stores an output load allowed for each block.

Further, in the automatic placement and routing method according to the present invention, a step of reading a netlist and calculating a provisional wiring length; a step of performing a delay simulation using the provisional wiring length; and a step of reading the netlist and performing automatic placement and routing. In the automatic placement and routing method including (1) and (2), a delay specification file is created, the delay of the critical path in the netlist is set, and based on the value of the delay specification file,
It is characterized in that the position where each block is arranged is determined at the time of automatic placement and routing.

Further, in the step of performing the delay simulation, it is preferable to perform the delay simulation by adding the delay value of the delay designation file as the delay value of the block symbol for the critical path.

Furthermore, the block symbol for the critical path is replaced with a real block satisfying the delay value specified in the delay specification file, and the block arrangement position is adjusted to satisfy the delay value specified in the delay specification file. It is preferable to carry out the placement and routing.

In the delay specification file, the required delay value from the start point to the end point of the critical path, which needs to keep the delay value within a certain value in the design circuit, or each block existing on this critical path Preferably, a required delay value is specified.

The automatic placement and routing method according to the present invention particularly has a delay designation file and a critical path block symbol which can be designated by a designer, and the delay value of the delay designation file is used as the delay value of the critical path block symbol. And performing a delay simulation. In addition, by replacing the block symbol for the critical path with a real block that satisfies the delay value specified in the delay specification file, and by adjusting the block layout position, an arrangement that satisfies the delay value specified in the delay specification file is performed. Wiring is performed.

The delay specification file contains a required delay value from the start point to the end point of the critical path that requires the delay value to be within a certain value in the design circuit, or a required delay value for each block existing on the critical path. Specify a value. In the automatic placement and routing, the wiring length is adjusted by optimizing the block type or adjusting the block placement position to satisfy the required delay value specified in the delay specification file.

[0017]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart showing an embodiment of the automatic placement and routing method of the present invention. This method is divided into delay verification before automatic placement and routing and automatic placement and routing. In the delay verification before automatic placement and routing, first, in circuit design and pattern design (step 1), the designer uses the critical path block symbol 7 only for blocks on the critical path specified in the delay specification file 8. The information included in the critical path block symbol 7 is only logical information, and the delay value required in the delay simulation (step 4) is given the value of the delay specification file 8 to give the delay to the critical path (step 4). 3). After the delay simulation (step 4), the delay value is verified (step 5). If there is no problem, the delay verification before the automatic placement and routing is completed, and the next automatic placement and routing 9 (step 9).
Proceed to.

In the automatic placement and routing (step 9), the delay specification file 8, net list 6, and block selection table 11 are input information. First, in the automatic placement and routing (step 9), first, an n-th block is arranged from the critical path start point (step 9-1), and a block of the next (n + 1) -th stage is arranged (step 9-).
2). Next, routes between the blocks in the nth to (n + 1) th stages are assigned routes (step 9-3). Thereafter, the capacity of the net to which the route is assigned is calculated (determination of the output load of the n-th block) (step 9-4), the input capacity of the next-stage and the block type (capacity) of the first to n-th blocks are delayed.
Is determined (step 9-5). The placement and routing is started from the critical path in the delay specification file 8.

FIG. 2 is a diagram showing the automatic placement and routing of FIG. As shown in this figure, the first-stage impeller (BLK1) 21 is arranged, counting from the AAA of the start point 20 specified in the delay specification file 8, and then the second-stage NA
The ND group 28 is arranged. The NAND group 28 includes a critical path block symbol NAND 22 and a plurality of Ns.
There is AND24. Then, the wiring 29 between the first stage and the second stage is wired. The wiring load is calculated from the wiring 29 actually drawn in this manner, and the block selection table 11 shown in FIG. 4 is searched by the sum of the wiring load and the next stage input capacitance to determine a block type satisfying the value of the delay designation file. For the third row, the NOR of the block symbol for the critical path
23, there are a plurality of NORs 25, and a wiring 30 connects between the second stage and the third stage. Similarly, the fourth
The stage includes an inverter 21 and an inverter 26 of a critical path block symbol, and the third stage and the fourth stage are connected by a wiring 31. From the fourth stage onward, the critical path end point (QQQ) 27 and the inverter 26 continue.

FIG. 3 is a diagram showing an example of the delay designation file of FIG. In this delay specification file, a delay specification file that can be specified by a designer is used. There are a path specification 36 that specifies the start point and the end point of the critical path and specifies only the delay between them, and a block specification 37 that specifies each block existing on the critical path.
The path designation 36 and the block designation 37 can be used together. In each case, the starting point, the ending point, and the specified delay value for specifying the delay can be specified. That is, as in FIG. 2, the start point AAA, the end point QQQ27, the inverter (BLK1) 21, the NAND
(BLK2) 22, NOR (BLK3) 23, and inverter (BLK4) 24, and the designated value 33 in the delay designation file 8 is 3NS to 5NS.

FIG. 4 is a diagram showing an example of the block selection table of FIG. According to this figure, if the sum of the input capacitance of the second-stage NAND group 28 connected to the output of the inverter 21 and the wiring capacitance of the wiring 29 is 3 as shown in FIG. 4 of 32), delay specification file 8
Is 3 (33 in FIG. 3 and 33 in FIG. 4), the block type 34 of the inverter is determined to be INV3.
If the output load is 2, the block satisfying the specified value 3 in the delay specification file 8 is INV2.
There are two types of INV3 (35 in FIG. 4). In this case, the smaller block size is selected. Therefore IN
V2 is selected. The same processing is repeated for the second and subsequent stages, and the placement and routing is performed up to the end point of the critical path. After judging the termination of the placement and routing of the critical path portion in Step 13, automatic placement and routing other than the critical path are performed in Step 14 by the same method as the conventional one.

Next, in the delay simulation, verification before placement and routing is performed using the delay value of the delay specification file, and in the automatic placement and routing, the same delay specification file is used, and a block type that can satisfy the specified value is used. Make a decision.

Next, a second embodiment of the present invention will be described. In the second embodiment, the wiring length is adjusted by adjusting the arrangement position of the block specified in the delay specification file, and the value specified in the delay specification file is satisfied.

Further, both the first embodiment and the second embodiment can be used together to satisfy the specified value of the delay specification file.

In this embodiment, as shown in FIGS. 2 and 3, a case where a method of giving a required value for each block is described by taking as an example a case where a critical path is extremely short, passing through four blocks. However, the present invention is not limited to this, and it is also possible to specify only the delay value from the start point to the end point of the critical path and perform optimization by a combination of selection of a block type and movement of a block arrangement position.

[0027]

According to the present invention, the block type used for the critical path and the block placement position are determined while performing automatic placement and routing, and optimization is performed on the design value designated in the delay designation file. Therefore, the delay value before and after the automatic placement and routing coincides in the critical path that requires an accurate delay value on the circuit, so that the verification result before the automatic placement and routing can be reflected in the automatic placement and routing. .

Further, since the delay values before and after the automatic placement and routing coincide, the design is completed upon completion of the automatic placement and routing, so that the design does not return. Therefore, the integrated circuit design T
AT can be shortened.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of the automatic placement and routing in FIG. 1;

FIG. 3 is a diagram showing an example of a delay designation file of FIG. 1;

FIG. 4 is a diagram illustrating an example of a block selection table in FIG. 1;

FIG. 5 is a flowchart showing a conventional example.

[Explanation of symbols]

1 Circuit design and pattern design step 2 Temporary wiring length calculation step 3 Critical path delay addition step 4 Delay simulation step 5 Delay value verification step 6 Netlist 7 Critical path block symbol 8 Delay designation file 9 Automatic Steps of placement and routing 10 Actual routing data 11 Block selection table 12 Netlist after placement and routing 13 Step of judging completion of all stages of critical path 14 Step of automatic placement and routing other than critical path 15 Delay simulation (after placement and routing) step 16 Delay Step of value verification (after placement and routing) 17 Step of determining whether to modify placement and routing or circuit correction 18 Delay library 20 Starting point of critical path 21 Inverter of block symbol for critical path 22 Critical NAND for block symbol for pass 23 NOR for block symbol for critical path 24 NAND 25 NOR 26 Inverter 27 End point of critical path 28 NAND group 29 Wiring between first and second stages 30 Second and third stages Wiring between the third stage 31 Wiring between the third and fourth stages 32 Output load 33 Value specified in delay specification file 8 34 Inverter block type 35 Delay specification when output load is 2 Value specified in file 8 36 When specifying the path of the delay specification file 37 When specifying the block of the delay specification file

Claims (7)

[Claims] An automatic placement and routing method comprising the steps of: reading a netlist to calculate a temporary wiring length; performing a delay simulation using the temporary wiring length; and reading the netlist and performing an automatic placement front. In the method, a delay specification file is created, a delay of a critical path in the netlist is set, and a type of a block used at the time of automatic placement and routing is determined based on a value of the delay specification file. Automatic placement and routing method. 2. The method according to claim 1, wherein when determining the type of the block used in the automatic placement and routing, the block to be used is determined using a block selection table.
Automatic placement and routing method described in 1. 3. The block selection table according to claim 2, wherein the block selection table generates in advance a plurality of blocks having different capacities for one functional block, and stores an output load allowed for each block. Automatic placement and routing method. 4. An automatic placement and routing method comprising: reading a netlist to calculate a temporary wiring length; performing a delay simulation using the temporary wiring length; and reading the netlist and performing automatic placement and routing. In the method, a delay specification file is created, a delay of a critical path in the netlist is set, and a position for arranging individual blocks during automatic placement and routing is determined based on the value of the delay specification file. An automatic placement and routing method characterized by the following. 5. The automatic delay simulation according to claim 5, wherein in the step of performing the delay simulation, a delay value of the delay designation file is added as a delay value of a block symbol for a critical path. Place and route method. 6. A delay value specified in the delay specification file by replacing the block symbol for the critical path with a real block satisfying a delay value specified in the delay specification file and adjusting a block arrangement position. 6. The automatic placement and routing method according to claim 5, wherein the placement and routing satisfying the following is performed. 7. The delay specification file may include a required delay value from a start point to an end point of a critical path in which a delay value needs to be within a certain value in a design circuit, or each block existing on the critical path. 7. The automatic placement and routing method according to claim 1, wherein a request delay value is specified.