JPH05174093A - Delay calculating device for logic circuit - Google Patents

Abstract

PURPOSE:To decrease a retrogression caused by a delay time error by estimating in advance a device delay and a wiring delay between flip-flops in an initial state of a logical design. CONSTITUTION:The device is constituted of a means 1 for providing a logical notation of a high abstraction degree from a logic circuit diagram, a means 2 for drawing a rough layout chart, a means for allowing each element of the logical notation and a position of the rough layout to correspond to each other, a means 4 for calculating a rough device delay from the logical notation, a means 5 for calculating a rough wiring delay time from the rough layout chart, a rough device delay time 6 between all flip-flops, and a means 11 for adding up the rough wiring delay time, and outputting a delay design error, when the delay time is larger than one clock cycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay calculation device for a logic circuit, and more particularly to a logical structure representation expressed by a logic notation having a higher abstraction than a detailed circuit diagram using logic parts and a floor plan level arrangement. The present invention relates to a delay calculation device for a logic circuit that roughly calculates a delay.

[0002]

2. Description of the Related Art Conventionally, this type of delay calculation method extracts a path between all flip-flops from a circuit diagram after a detailed circuit diagram is created or after the layout of logic components of a logic circuit is determined. Then, detailed delay calculation of all paths is performed based on detailed device delay information, wiring length, wiring branch data, and the like to calculate whether the delay between flip-flops is within the clock cycle time. Alternatively, a logic simulation was performed in consideration of these detailed delay data, and it was checked whether the state value held by the flip-flop reached the next fan-out destination flip-flop within the clock cycle time. ..

[0003]

The logic design of a logic circuit breaks down from a logic schematic diagram to a detailed logic circuit diagram. In any design process, the signal delay time between flip-flops is taken into consideration. There must be. This is because if the signal delay time between flip-flops is longer than the clock cycle time, the logic must be changed.

The delay time of a logic circuit includes a device delay and a wiring delay, and the device delay can be calculated at the time when the logic circuit diagram is created. However, the wiring delay is a mounting design performed after the logic design. Calculation is not possible without the placement / wiring information of the obtained logic parts. Therefore, in the design of a high-speed computer in which the delay time must be taken into consideration, it is necessary to perform rough mounting design at the time of logic design and obtain the layout / wiring information of logic components in advance.

In the prior art, the delay calculation by the device delay was possible at the time of creating the detailed logic circuit diagram, but at the time of creating the logic schematic diagram, the logic component was not specified, and it was mounted. Since the information was not finalized, no delay calculation was performed, and it was due to the intuition and experience of the logic circuit designer. As a result, if a delay time error between flip-flops is detected at the time when the detailed logic circuit diagram is created and when the placement and wiring of the logic components are confirmed, it is necessary to change the design by changing the logic. There was a design loss of redesigning.

[0006]

It is an object of the present invention to improve the disadvantages of the conventional example, and in particular, the delay time for the flip-flop can be surely grasped at the initial stage of the logic design, whereby the return after the design and the like can be performed. It is possible to provide a delay calculation device capable of effectively avoiding the above.

[0007]

According to the present invention, the logical configuration of a logic circuit is represented by a logical component represented by a representation having a higher abstraction than a detailed circuit diagram using logical components and between the logical components. A logical structure expressing means expressed by a logical notation consisting of connections, a layout expressing means expressing a schematic layout diagram showing a layout position when a logical constituent element is realized by an actual logic circuit, and a logical structure expressing means. For a logical component, a position indicating means for indicating a position on the schematic layout diagram where the logical component is arranged on an LSI or a board that realizes the logical circuit is provided, and a device delay required by the logical component is provided. Device delay calculation means that is roughly obtained from the logical representation of the logical constituent elements, and each logical constituent element that obtains the wiring length between two connected logical constituent elements by the position indicating means. A wiring delay calculating means for roughly calculating the position and for calculating a rough wiring delay between two logical components in consideration of the number of branches of the wiring is provided, and a logical component including all flip-flops and its logic. The device delay calculation means and the wiring delay calculation means are used to calculate the sum of the device delay time and the wiring delay time with respect to the logic constituent elements including other flip-flops, which the logical values of the constituent elements can influence. The configuration is such that the delay is calculated and the delay calculation between all flip-flops is provided. This aims to achieve the above-mentioned object.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A functional block diagram of an embodiment within the scope of claim 1 of the present invention is shown, FIG. 2 is a functional block diagram of an embodiment within the scope of claim 2 of the present invention, and FIG. The functional block diagram of the Example of the range of 3 is shown. Further, FIG. 4 is an example of the logical notation expressed by the logical structure expressing means 1. FIG. 6 is a layout diagram of the LSI represented by the layout representation means 2. FIG. 7 is an example in which the logical notation and the layout diagram are associated by the position indicating means 3. FIG. 8 is a logical representation of each logical component in logical notation and the corresponding schematic circuit diagram. FIG. 8 is an example of expressing logical connections between logical components in the layout diagram.

In FIG. 1, a logical structure expressing means 1 expresses the structure of a logical circuit by a representation having a higher abstraction than a detailed circuit diagram using logical parts, and between the logical components and the logical components. Represents a logical notation consisting of connections. Figure 4
This is an example of logical notation with a high degree of abstraction. In FIG. 4, FF
-A indicates a register representing a set of 32-bit flip-flops, for example. Selector-f consists of logic-d and FF
Each 32-bit output of -b is a control signal IN-g
It is a selector that selects according to the value of. In a detailed circuit diagram using conventional logic components, for example, FF-a is represented by a shape in which 32 libraries of LSI having 1-bit flip-flops are used and wiring is made for each pin of the library. ..

On the other hand, the layout expressing means 2 expresses a schematic layout diagram which can show an approximate arrangement position when the logical constituent elements are realized by an actual logic circuit.
FIG. 5 shows the schematic layout diagram in the case of an LSI. In the layout diagram, BO to BF represent relocatable blocks, and each logical component is a block BO.
To BF.

Next, the position instructing means 3 includes the logical constituent elements (FF-a or selector) expressed by the logical structure expressing means 1.
(f etc.), the position on the schematic layout diagram where the logical constituent elements are arranged on the LSI or the board that realizes the logical circuit is designated. FIG. 5 is a diagram showing the logical notation of FIG. 4 and the floor plan in which the logical components of the LSI are arranged.
It is instructed to allocate the FF-a to the block at the upper left corner of the LSI by using the position designating means, and to allocate the selector-f to the block B8 of the LSI.

On the other hand, the device delay calculation means 4 roughly finds the device delay required by the logical component from the logical representation of the logical component. For example, the logical expression of the selector-f is "f = IF g.EQ.O" as shown in FIG.
The expression "THEN d ELSE b" is "f = g.d + g.b" in the Boolean expression, and when this is simply mapped to the gated library by a method such as logic synthesis, FIG. The detailed circuit diagram of the selector-f of FIG. The device delay of the inverter gate f1 is 1 [ns], the device delay of the AND gates f2 and f3 is 2 [ns], and the device delay of the OR gate f3 is 3 [ns].
[Ns], the device delay between g and f is 5 [n
s] 6 [ns] for comb, 5 [ns] for d-f, b-
The device delay can be roughly estimated with respect to the selector-f between f as well as 5 [ns].

Similarly, for logic-d, a-d
The approximate device delay between them is 1 [ns], and regarding the logic-e, 5 [ns] or 6 [ns] between i and e, f
It can be roughly estimated that the distance between −e and h−e is 7 [ns] or 8 [ns]. Further, in another embodiment of the device delay calculating means, if the selector is 5 [ns],
If the depth of the logic pool operation is one step, 2 [ns], 2
If it is a stage, a rough delay is set in advance to 4 [ns], and the device delay can be calculated for each logical component.

The wiring delay calculating means 5 roughly determines the wiring length between two connected logical constituent elements from the position of each logical constituent element obtained by the position indicating means 3, and determines the number of branches of the wiring. Taking into account, the approximate wiring delay between the two logic components is determined. In FIG. 4, it can be seen that the logic-d and the selector-f have a connection relationship. In FIG. 6, the logic-d is block B by the position indicating means 2.
1 and the selector-f is instructed to be located in the block B8.

The wiring delay calculating means 5, like the wiring 1 in FIG. 8, obtains the wiring length between these blocks by the Mahattan length or the like, and calculates the wiring delay between the blocks. If the wiring delay time to the adjacent block on the LSI is 1 [ns], then F
The wiring delay from Fa to logic-d is 1 [ns],
The wiring delay from the logic -d to the selector -f is 3 [n
s]. When each wiring has a plurality of branching signal propagation paths, these wiring delays are corrected in proportion to the number of branches.

The delay calculation means 6 between all flip-flops is
The device delay time and the wiring delay time of the logical path between the logic component including all flip-flops and the logic component including other flip-flops to which the logical value of the logic component can influence The total is obtained by using the device delay calculation means 4 and the wiring delay calculation means 5. In the example shown in FIG. 4, there are logical paths between FF-a and FF-c and between FF-b and FF-c. Explaining the path from FF-a to FF-c, the device delay is 13 [ns] or 14 [ns] in total of logic-d, selector-f, and logic-e, and the wiring delay is shown in FIG. By way of example, the total delay value due to the wirings l, m, n, and k is 7 [ns]. Therefore, FF-
The delay time from a to FF-c is 20 [ns] or 21
[Ns] is required. Similarly, the delay time from FF-b to FF-c is also obtained.

Next, in the scope of claim 2, the flip-flop designating means 7 designates a logical constituent element including any two flip-flops in logical notation. In FIG. 4, it is assumed that FF-a and FF-c are designated. The inter-FF connection identifying means 7 identifies the connection between the logical components including the designated two flip-flops. In FIG. 4, FF
The logical connection between -a and FF-c is FF-a-logic-d-selector-f-logic-e-FF-c. The specific inter-flip-flop delay calculating means 9 limits the device delay calculating means 4 and the wiring delay calculating means 5 to only the logical components existing between the logical components including the two flip-flops and the logical connection between them. Is used to determine the approximate delay between the logical components, including the two flip-flops. Delay time from FF-a to FF-c of FIG. 4 As shown in the embodiment of FIG.
It is calculated as [ns] or 21 [ns].

Further, in the scope of claim 3, the cycle time setting means sets the clock cycle time of the logic circuit. For example, the clock cycle of the designed logic circuit is 18
It is set to be [ns]. Delay error detection means 10
Is the delay time between the two logical components including the flip-flops, which is calculated by the delay calculation means 6 between all flip-flops or the delay calculation means 9 between specific flip-flops,
The clock cycle time set by the cycle time setting means is compared, and a design error is displayed when the delay time between the logic components is larger than the clock cycle time. In the example of FIG. 5, since the delay time from FF-a to FF-c is calculated as 20 [ns] or 21 [ns], a delay error is apparently generated for the clock cycle setting of 18 [ns]. It is determined to occur.

[0019]

As described above, according to the present invention,
Approximate device delays and wire delays between all flip-flops or specific flip-flops can be roughly estimated at the initial stage of logic design before creating a detailed schematic or determining the layout of the logic circuit. It is possible to know the delay time between the flip-flops, and also to know whether the obtained delay time between the flip-flops is larger than one clock cycle of the logic circuit.
As a result, an unprecedented excellent delay calculation device for a logic circuit, which can significantly reduce the backtracking of the design caused by the detection of a delay error after the detailed circuit diagram is created or the layout of the logic circuit is determined Can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram showing an example of another range of the present invention.

FIG. 4 is an explanatory diagram showing an example of a logical expression used by the logical structure expression means in FIGS. 1 and 2;

FIG. 5 is a schematic layout diagram of an LSI.

FIG. 6 is an explanatory diagram showing that the correspondence between the logical expression of FIG. 4 and the schematic layout diagram of the LSI is shown by the position indicating means.

FIG. 7 is a schematic diagram of logic notation of elements excluding elements including a flip-flop and elements showing an input signal among logic constituent elements shown in FIG. 4, and set when executing device delay calculation means generated from this logic notation; It is explanatory drawing showing a circuit diagram.

FIG. 8 is a diagram showing a schematic wiring path between the logical components indicated by the position indicating means in the schematic layout of the LSI of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Logical structure expressing means 2 Position indicating means 3 Layout expressing means 4 Device delay calculating means 5 Wiring delay calculating means 6 All flip-flop delay calculating means 7 Flip-flop specifying means 8 Flip-flop connection specifying means 9 Specific flip-flop delay calculating means Means 10 Cycle time setting means 11 Delay error detecting means

Claims (3)

[Claims] 1. A logical structure of a logical circuit is expressed by a logical notation consisting of logical components represented by a representation having a higher degree of abstraction than a detailed circuit diagram using logical components and connections between the logical components. A logical structure expressing means, a layout expressing means for expressing a schematic layout diagram showing an arrangement position when the logical constituent elements are realized by an actual logic circuit; and a logical constituent element expressed by the logical structure expressing means, An LSI for realizing a logic circuit or a position designating means for designating a position where a logical component is arranged on a board on a schematic layout diagram is provided, and a device delay required by the logical component is represented by a logical representation of the logical component. From the position of each logic component obtained by the position designating means, and the device delay calculation means that is roughly obtained from And a wiring delay calculating means for calculating a rough wiring delay between two logical components in consideration of the number of branches of the wiring, and a logical component including all flip-flops and a logic of the logical component. A total of a device delay time and a wiring delay time with respect to a logical component including another flip-flop, which value can influence, is obtained by using the device delay calculating means and the wiring delay calculating means. A delay calculation device for a logic circuit, comprising delay calculation means between flip-flops. 2. A logical structure of a logical circuit is expressed by a logical notation consisting of logical constituent elements represented by a representation having a higher degree of abstraction than detailed circuit diagrams using logical parts and connections between the logical constituent elements. A logical structure expression means, a layout expression means for expressing a schematic layout diagram showing a layout position when a logical constituent element is realized by an actual logic circuit; and a logical constituent element expressed by the logical structure expression means, A position designating means for designating a position on the schematic layout diagram where a logical constituent element is arranged on an LSI or a board for realizing a logical circuit is provided, and a logical constituent element including any two flip-flops is designated by the logical notation. And a flip-flop connection specifying means for specifying the connection between the logical components including the specified two flip-flops. A logical component including two flip-flops is limited to only the logical components existing between the logical components including the flip-flops and the logical connection between them, and using the device delay calculation means and the wiring delay calculation means. A delay calculating device for a logic circuit, comprising: delay calculating means between specific flip-flops for obtaining a rough delay between them. 3. In addition to the first claim or the second claim, a cycle time setting means for setting a clock cycle time of a logic circuit, a delay calculation means between all the flip-flops or a specific flip-flop is provided. The delay time between the two logic components including the flip-flop obtained by the delay calculation means is compared with the clock cycle time set by the cycle time setting means, and the delay time between the logic components is calculated from the clock cycle time. 3. The delay calculation device for a logic circuit according to claim 1, further comprising a delay error detection means for displaying a design error when it is larger than the delay calculation means between the flip-flops.