CN113887166A - Orbit allocation method based on integer linear programming and two-stage division strategy - Google Patents

Abstract

The invention relates to an orbit allocation method based on integer linear programming and a two-stage division strategy. First, an efficient integer linear programming model for solving the orbit allocation problem is proposed to minimize the overlap between iroutes and thereby significantly improve routability. Secondly, a parallel mechanism based on a panel level and a supbpanel level is provided, and the mechanism can greatly improve the solving speed of the SPTA algorithm on the premise of not sacrificing the quality of the track distribution solution. Then, an efficient two-phase partitioning strategy is designed to further optimize the runtime of the algorithm.

Description

Orbit allocation method based on integer linear programming and two-stage division strategy

Technical Field

The invention belongs to the technical field of integrated circuit computer aided design, and particularly relates to a track distribution method with good expandability and parallelism and based on integer linear programming and a two-stage division strategy.

Background

Physical design is one of the most important and time-consuming links in Very Large Scale Integration (VLSI) design, and the design results directly affect the performance, reliability, and manufacturing yield of the chip. In VLSI physical design, routing is a very critical step. To reduce the complexity of the routing process, it is usually divided into two steps: general wiring and detailed wiring. With the increasing complexity of the detailed wiring problem and the increasing density of nets, the overall wiring result is more and more difficult to match the requirements of the detailed wiring. Therefore, in order to reduce the difficulty of the detailed wiring work while increasing the utilization of the overall wiring result, scholars introduced a step of track allocation to better match the overall wiring and the detailed wiring.

Today, a series of orbital assignment related assignment methods have been proposed, including WBM-TA, GTA, TROY, etc. The conventional track allocation algorithms described above maximize the number of allocated wires without allowing conflicts, and do not consider that the unallocated wires may have a large amount of overlap with the already allocated wires in the detailed wiring stage, thereby causing a very serious short circuit problem, which does not provide effective wiring guidance for detailed wiring in actual industrial production.

To solve the above problems and improve routability in a detailed routing stage, a novel track allocation technique allocates all wires to tracks in consideration of minimizing a wire length cost, an overlapping cost, and a barrier cost. The NTA, TA-HDPSO, RDTA, etc. aim to distribute all the conductors onto the tracks in the track distribution phase, which is more helpful to solve the short-circuit problem in the detailed wiring, and more easily balances the mismatch between the overall wiring and the detailed wiring. Here, we refer to the problem model corresponding to the above-described novel Track allocation technique as a Routability-Driven Track Assignment (RDTA) problem.

The track allocation problem has proven to be an NP-hard problem. An Integer Linear Programming (ILP) method is one of the optimized mathematical Programming methods of a decision-making system, and has a good application prospect in solving NP-difficulty problems and multivariate optimal decision-making problems. Currently, the ILP method has been applied to a number of problems in VLSI wiring processes, such as global wiring, rail allocation, and detailed wiring. The series of wiring work based on the ILP obtains excellent results in the aspect of solution quality, and the feasibility of the ILP applied to the wiring field is reflected.

The existing track distribution technology driven by routability is based on a heuristic method, and has the problem of easy falling into local optimization, so that an accurate and globally optimal track distribution scheme cannot be obtained. In order to provide a more reliable track allocation scheme and a more accurate routability estimation for detailed routing, we propose an SPTA algorithm, a track allocation method based on integer linear programming and a two-stage partitioning strategy with good scalability and parallelism. According to our investigation, the invention is the research work for solving RDTA by adopting an ILP method for the first time.

Disclosure of Invention

The invention aims to provide a track allocation method based on integer linear programming and a two-stage division strategy.

In order to achieve the purpose, the technical scheme of the invention is as follows: a track distribution method based on integer linear programming and two-stage division strategies comprises the following steps:

step S1, a parallel mechanism based on a panel level and a supbpanel level is provided, and a two-stage division strategy is provided based on the mechanism;

step S2, an integer linear programming model is proposed to solve the routability-driven orbit assignment problem to minimize the overlap between iroutes to significantly improve routability.

In an embodiment of the present invention, in step S1, the two-stage partitioning policy includes two sub-processes, which are a first-stage partitioning policy and a second-stage partitioning policy in sequence, where the first-stage partitioning policy refines a panel into a plurality of independent smaller-scale supbpanels, and the divided supbpanels are completely independent, and the second-stage partitioning policy divides the panel into units of finer granularity based on the first-stage partitioning policy by taking the supbpanels as units, and divides the solving scale of the current model into units of finer granularity.

In one embodiment of the present invention, in step S2, the track allocation problem of the routability driver is described as: giving a group of net sets N to be subjected to rail distribution, wherein the N comprises global nets and local nets, each net N comprises a plurality of pins and extracted wires iroutes, and P represents a group of panel sets, each panel P comprises one row or one column of wiring units, the panels consisting of one row or one column of wiring units are horizontally or vertically oriented panels, and each panel comprises a rail set T to be distributed_pSet of all obstacles B_TAnd a set of iroutes I to be allocated_p(ii) a For each panel to be wired, set I_pAll iroutes in (1) are assigned to the set T_pThe goal is to minimize the total stacking cost, total barrier cost and total line length cost of track distribution solutions; thus, an integer linear programming model to solve the routability-driven trajectory assignment problem is as follows:

1) decision variables

There are only two allocation scenarios for iroute on the track: allocated and unallocated, define iroute i as a simple binary variable x in the track t allocation case_itAs shown in equation (1):

wherein the decision variable x is determined when iroute i is assigned to a track t_itHas a value of 1; otherwise, the variable x is decided_itIs 0;

2) constraint conditions

The exclusive constraint is in one allocation, and the exclusive constraint ensures that one iroute can be allocated to only one track in the panel, as shown in formula (2):

wherein for set I_pHas | T at any iroute i_pL x corresponding to it_itIf and only if | T_pL x_itWhen the sum of (1) is equal to 1, the equation holds; otherwise, an exclusivity constraint is violated;

3) overlap amount legitimacy constraints

The final overlapping cost is obtained by calculating the overlapping quantity of the panel sections, the whole panel is divided into a plurality of sections with unequal lengths, and after the section is finished, the formula (3) can be used for S_tThe number of overlaps per segment is determined for all segment elements in the track, and particularly, if no conductor is assigned to the k-th segment of the track t, the onum is obtained from equation (3)_tkThe value of (2) is-1, the overlapping quantity is a nonnegative natural number according to the meaning of the overlapping quantity, and the formula (4) sets a lower bound for the overlapping quantity to ensure the legality of the overlapping quantity;

wherein, the gum_tkIs an integer variable representing the number of overlaps of track t on the k-th segment, c_ikIs I_pWhether or not middle iroute i exists on the k-th segment, c_ikIs a known binary constant;

4) objective function

Since the goal of the track allocation problem is to minimize the costs incurred during routing, the optimized objective function can be represented by equations (5) - (8):

minimizeα×blkcost+β×overlapcost+γ×wlcost (5)

wherein blkcost, overlapcost and wlcost are barrier cost, overlap cost and line length cost generated in panel, respectively; olen (I, b) represents I_pIroute i and B in the set_TThe length of overlap between obstacles b in the set; slen_tkA segment length representing the kth segment of track t; distance (x)_ijPin, j) represents the shortest distance between the position where iroute i is placed and other components in the net where i is located, i, j, pin are the same as the net n where i is located_i(ii) a Alpha, beta and gamma are self-defined parameters; since wire collision with obstacles during track allocation is the most priority, α is set to a very large value to ensure that the cost of the obstacles is as low as possible.

In an embodiment of the present invention, in consideration of the running time, in the model optimization process, the process of calculating the wire length cost is as follows: the method comprises the steps of extracting iroutes from local nets, distributing the iroutes to a track with the shortest Manhattan distance to the iroutes, respectively calculating the Manhattan distances between the iroutes and components in the same-line nets, and then distributing the obtained iroutes to the track with the shortest Manhattan distance, wherein when the Manhattan distances between the current iroute and other components are calculated in the global nets, only the distances between the current iroute and pins in the nets and the iroute of the determined tracks are considered, and the iroutes with undetermined positions are ignored in the process, and the distances calculated in the mode are used as the basis of the cost of optimizing the lines in the model optimization process.

Compared with the prior art, the invention has the following beneficial effects: the invention discloses solving RDTA by adopting an ILP method for the first time.

Drawings

FIG. 1 is a general router flow diagram.

FIG. 2(a) a multi-layer global routing model.

Fig. 2(b) shows a corresponding multi-layer track assignment model.

Fig. 3(a) overall wiring results.

Fig. 3(b) a schematic diagram of a wire pattern.

FIG. 4 is a schematic diagram of barrier cost and overlap cost calculation.

FIG. 5(a) is a top view of a wire mesh.

Figure 5(b) manhattan distance between net assemblies.

FIG. 5(c) is a weighted complete graph of net assemblies.

Fig. 5(D) shows a 3D view of the intra-net connectivity build-up.

Fig. 6 is a schematic diagram of a segmentation method and an overlap amount calculation method.

FIG. 7 is a schematic diagram of a first stage partitioning strategy.

Fig. 8 is a diagram of a second stage partitioning strategy.

FIG. 9 is a diagram of a parallel implementation model.

Detailed Description

The technical scheme of the invention is specifically explained below with reference to the accompanying drawings.

As shown in fig. 1, a track allocation method based on integer linear programming and two-phase partition strategy includes the following steps:

step S1, a parallel mechanism based on a panel level and a supbpanel level is provided, and a two-stage division strategy is provided based on the mechanism;

step S2, an integer linear programming model is proposed to solve the routability-driven orbit assignment problem to minimize the overlap between iroutes to significantly improve routability.

The invention discloses a track allocation method with good expandability and parallelism based on integer linear programming and a two-stage division strategy.

The method specifically comprises the following design processes:

1. a wiring overall flow is designed. The input data of the process is a track set T of each panel_pIroute group I_pAnd a net set N, wherein the output data is a track allocation scheme. The process comprises two sub-processes which are a two-stage division strategy and an orbit allocation process in sequence.

2. A novel two-phase partitioning strategy is proposed. The two-stage partition strategy comprises two sub-processes, namely a first-stage partition strategy and a second-stage partition strategy. The process can reduce the time cost of solving for the track distribution process.

3. The first stage partitioning strategy refines the panel into a plurality of independent smaller-scale supbpanels, and the divided supbpanels are completely independent.

4. Under the condition of meeting further division conditions, the second-stage division strategy divides the current model solution scale into finer-grained units by taking the supbpanel as a unit on the basis of the division of the first stage.

5. The effective ILP model for solving the RDTA is provided, the model considers the wiring information of the local net and the global net at the same time, and has more accurate routability estimation compared with the traditional problem model, and the practicability of solving the RDTA by applying the ILP method is embodied. Under the condition that overlapping conflict is allowed to occur, the ILP model solving phase provided by the invention can obtain the optimal solution scheme of the RDTA.

6. An efficient parallel strategy based on the panel level and the supbpanel level is proposed. Compared with various existing modern track allocation algorithms, the SPTA realizes a good acceleration ratio on a multi-core machine and shows excellent expandability.

The following is a specific implementation process of the present invention.

1. Consider the wire pattern of a local wire mesh:

the global routing phase determines the routing scheme for all nets that minimizes interconnect costs on the basis of ensuring routability of an Integrated Circuit (IC) design. The track assignment stage assigns each wire in the routing scheme provided by the overall router to the appropriate track and minimizes the wire-to-wire overlap cost, the wire-to-obstacle overlap cost, and the wire length cost within each wire net. Since conventional track allocation is a solution that maximizes the number of allocated wires to minimize the cost, there may be some wires that are not allocated, and most track allocation does not take into account wires in local nets, which may result in inaccurate calculations of the costs incurred during the routing process. Therefore, the problem model of the invention not only extracts the wires from the global wire network, but also considers the wire extraction in the local wire network, and fully utilizes the information of the overall wiring, so that the track distribution result is closer to the detailed wiring.

In the multilayer wiring problem, the wiring direction is uniform (horizontal or vertical direction) within the same layer, and the wiring direction between adjacent layers is crossed. Fig. 2(a) and (b) are schematic diagrams of a multi-layer track allocation model. In fig. 2(a), there are wiring layers 1,2, and 3, and the wiring layers 1 and 3 are wirings in the vertical direction and 2 is in the horizontal direction. Each circle represents an abstracted unit of wiring, which we call a G-cell. The rectangle in FIG. 2(b) is one of the routing channels for each routing layer, which we call a panel. The dashed lines in the panels represent tracks, and each panel contains a number of tracks for the placement of wires.

Fig. 3(a) and (b) are schematic diagrams of the wire pattern extracted by the algorithm. The round points are pins, the smallest rectangular area is called a wiring unit, the nets with all pins existing in the same wiring unit are called local nets, and the nets crossing multiple wiring units are called global nets. FIG. 3(a) is the overall wiring result for two nets, n₁For local nets with two pins, n₂A global net with two pins. Fig. 3(b) shows a specific case of the SPTA extraction wire. The present invention herein refers to a line segment passing through one or more wiring units as a wire. w is a₁And w₂Is from a global net n₂Extracted wire, w₃Is from a local net n₁The extracted wire is called iroute by the invention.

2. Cost calculation method

2.1 cost of obstacle

According to the described wire model, the invention extracts iroutes to be distributed from the global nets and the local nets. When iroute is assigned to a certain track, if overlap occurs with part or all of one or more obstacles on the track, it is said that iroute collides with the obstacle. The length of overlap resulting from such collisions is referred to as barrier cost.

2.2 overlap cost

When iroute is assigned to a track, if it overlaps with one or more iroutes already assigned to the track, it is said that a conflict occurs between iroute and iroute. The length of overlap resulting from such collisions is called the overlap cost.

Fig. 4 is a schematic diagram of a calculation manner of barrier cost and overlap cost. The panel shown in the figure contains three tracks, the shaded rectangle being an obstacle spanning tracks 2 and 3. The cost per track is calculated as follows:

track 1: barrier cost 0; the overlapping cost is 1 × 1+3 × 2+2 × 1 ═ 9;

track 2 barrier cost 0; the overlapping cost is 0;

track 3 barrier cost 2; the overlapping cost is 1 multiplied by 1 to 1;

2.3 line length cost

Both pins and iroutes are components within nets, and a net contains several pins and iroutes. In the track assignment phase, one track is selected for each iroute and placed on the track. In the subsequent detailed routing stage, these placed iroutes will be connected to other components of the net they are on. The cost of connecting all components together inside a net is the wire length cost.

Fig. 5(a) - (d) are schematic diagrams of the way the line length cost of a net is calculated. FIG. 5(a) is a top view of a net containing 6 components (3 pins and 3 iroutes). P₂And ir₂Distributed over the horizontally oriented panel, and the remaining four modules distributed over the vertically oriented panel of the next level. FIG. 5(b) showsThe manhattan distance between every two components in the wire mesh. Using the information in the table to generate a weighted complete graph, as shown in fig. 5(c), the 6 components are connected together by the minimum spanning tree algorithm, and the resulting tree length is the line length cost of the net (the sum of the solid path lengths shown in fig. 5 (c)). Figure 5(D) is a 3D view of the assembly of nets 6 connected together.

3. Problem model

Based on the discussion of the wire model and the three costs, the routability-driven orbit allocation problem solved by the present invention can be described in detail as follows:

given a set of net sets N (including global nets and local nets) to be track-assigned, each net N contains several pins and iroutes. Let P denote a set of panel collections, where each panel consists of a row or column of wiring units. The panel composed of a row (column) of wiring units is a horizontally (vertically) oriented panel, each panel comprising a set of tracks T to be allocated_pSet of all obstacles B_TAnd a set of iroutes I to be allocated_p. For each panel to be wired, the invention will assemble I_pAll iroutes in (1) are assigned to the set T_pThe goal is to minimize the total stacking cost, total barrier cost and total line length cost of track distribution solutions.

4. ILP model of the invention

The traditional ILP model cannot be used for solving the RDTA, and therefore, an orbit allocation algorithm based on an integer linear programming model and a two-stage partition strategy is provided.

1) Decision variables

There are only two allocation scenarios for iroute on a track, allocated and unallocated. We can define iroute i as a simple binary variable x in the case of track t allocation_itAs shown in equation (1):

wherein the decision variable x is determined when iroute i is assigned to a track t_itHas a value of1; otherwise, the variable x is decided_itThe value of (d) is 0.

2) Constraint conditions

Definition 1 an exclusive constraint is in one allocation, and the exclusive constraint ensures that one iroute can be allocated to only one track in the panel, as shown in formula (2):

wherein for set I_pHas | T at any iroute i_pL x corresponding to it_itIf and only if | T_pL x_itWhen the sum of (1) is equal to 1, the equation holds; otherwise, the exclusivity constraint is violated.

Defining 2iroute number constraints in order to enable the track allocation scheme to better guide the detailed wiring work, the wiring resources need to be considered more fully, so that the invention allocates all iroutes extracted from one panel to the appropriate tracks.

Wherein for each iroute set I_pAll have I_p|×|T_pL x_itIf and only if I_p|×|T_pL x_itIs the sum of | I_pThe equation holds true when |; otherwise, the iroute number constraint is violated.

For the ILP model to solve the RDTA problem, two sets of constraints of definition 1 and definition 2 need to be satisfied simultaneously.

Theorem 1: in the ILP model of the present invention for solving the RDTA problem, the exclusivity constraint p₁Is really contained in iroute quantity constraint q₁Of i.e.

And (3) proving that: if it proves

Only p needs to be proved₁Is q₁Is not a requirement. Let p be₁Represents the formula (2), q₁Equation (3) is expressed.

The full conditions are as follows: let | T_P|＝N,|I_PAnd M. P is to be₁The following M sub-formulae (formula (44)) can be obtained by expanding q₁The (M + 1) th sub-formula (5)) can be obtained by expansion. The equation (5) can be obtained by adding the left and right sides of the equation (4) with the same sign. Let p be₁Is X, then

Satisfy q₁. Can be obtained, p₁→q₁。

x₁₁+x₁₂+...+x_1N+...+x_MN＝|I_p| (5)

② unnecessary conditions: let Y be q₁One solution of, i.e. x₁₁＝x₁₂＝...＝x_1N＝1,x₂₁＝x₂₂＝...＝x_MN＝0。

At this time, Y does not satisfy p₁. Namely, it is

Thus, p₁Is q₁Is a sufficient condition that is not necessary for the purpose,

in summary, the ILP model for solving the RDTA problem of the present invention satisfies the exclusive constraint and the iroute number constraint, and the ILP model of the present invention only needs to add the constraint shown in formula (2).

3) Overlap amount legitimacy constraints

In the ILP model provided by the invention, the final overlapping cost is obtained by adopting a mode of calculating the overlapping quantity of panel sections. The description will be given by taking a panel in fig. 6 as an example, in which a solid rectangle is a panel, a broken line is a rail on which iroute can be placed, a shaded rectangle placed on the rail is an obstacle, and a solid rectangle placed horizontally in the figure is iroute. Before the iroute distribution is carried out, the invention marks the panel according to the coordinates of the starting point and the end point of all the iroutes in the panel, and the marking result is shown as a vertical dashed line in the figure. We refer to the area between the two vertical dashed lines as a segment. Thus, the whole panel is divided into several segments with different lengths, the beginning segment is indicated by first in the figure, and the ending segment is indicated by last.

After segmentation is complete, equation (6) can be applied to S_tThe number of overlaps per segment is found for all segment elements in the sequence. In particular, if no conductor is allocated to the kth segment of track t, then the onum derived from equation (6)_tkHas a value of-1. According to the meaning of the overlap quantity, the overlap quantity is a non-negative natural number, and the formula (7) sets a lower bound for the overlap quantity to ensure the legality of the overlap quantity.

Wherein, the gum_tkIs an integer variable representing the number of overlaps of track t on the k-th segment, c_ikIs I_pWhether or not middle iroute i exists on the k-th segment, c_ikIs a known binary constant.

To ensure that the required overlap cost is accurate and effective, the overlap quantity value should satisfy the legitimacy constraint. FIG. 6 shows a solution for the allocation of the tracks of the panel, the panel shown at the bottom being the overlap of the tracks on the segments. 3 iroutes have been placed on 3 rd section of track 1, 0 iroute has been placed on 3 rd section of track 2, 1 iroute has been placed on 3 rd section of track 3, and then the track 1,2,3 overlap quantity in 3 rd section respectively is: 2,0,0.

4) Objective function

Since the objective of the track allocation problem is to reduce the costs generated during the wiring process as much as possible, the optimized objective function can be expressed by equations (8) to (11).

minimizeα×blkcost+β×overlapcost+γ×wlcost(8)

Wherein blkcost, overlapcost and wlcost are barrier cost, overlap cost and line length cost generated in panel p, respectively; olen (I, b) represents I_pIroute i and B in the set_TThe length of overlap between obstacles b in the set; slen_tkIndicating the segment length of the kth segment of track t. distance (x)_ijPin, j) represents the shortest distance between the position where iroute i is placed and other components in the net where i is located, i, j, pin are the same as the net n where i is located_i. α, β and γ are custom parameters. Since it is the most priority to have the wire collide with the obstacle during the track allocation process, α is set to a very large value in the present invention to ensure that the obstacle cost is as small as possible. In the experimental part, the invention provides the adjustment process of alpha, beta and gamma, and minimizes the overlapping cost and the line length cost on the premise of ensuring the barrier cost to reach the optimal value.

In consideration of the running time, in the optimization process of the model, the process of calculating the wire length cost is as follows: iroutes extracted from local nets are assigned to the track with the shortest manhattan distance from them. For iroutes extracted from the global net, the manhattan distances between each component placed on different tracks and in the same net are calculated respectively, and then the component is distributed to the track with the shortest manhattan distance. It is noted that in calculating the Manhattan distance of the current iroute from other components in the global net, we only consider the distance between the current iroute and the pins in the net and the iroute of the determined track, and the iroute of the undetermined position is ignored in this process. The distance calculated in the mode is used as the basis of the optimized line length cost in the model optimization process. On the premise that the quality of the solution is slightly reduced, the method for calculating the line length cost by adopting the approximation method can save more time cost than the method for generating the minimum spanning tree.

Due to the excessive solution time, the conventional ILP is usually manually stopped within a certain time or a certain number of iterations to meet the time requirement of the wiring design. The SPTA does not interrupt the solving process of the ILP and set iteration times, but automatically stops after finding the optimal solution. Therefore, the ILP model of the present invention can obtain an optimal solution under the orbit allocation problem model of the present invention.

5. Two-stage partitioning strategy

Since ILP is NP-complete, the computational cost of SPTA is high. Therefore, in this section, the present invention provides a partitioning technique of the ILP model, which is called a two-stage partitioning strategy to reduce the size of the solution space and achieve the purpose of saving time and cost. Before partitioning, the original problem is solved by establishing an ILP model by taking panel as a unit. Now, the initial track allocation problem is divided into a plurality of sub-problems, i.e. the panel is divided into a plurality of subsets according to a certain rule, and the invention refers to the smaller unit formed after the division as the subpanel. And then, an ILP method is applied to model and solve the track distribution problem of the supbpanel.

(1) First phase partitioning strategy

The first stage partitioning strategy is to refine the panel to several independent smaller-scale supbpanels. FIG. 7 is a schematic diagram of the first stage partitioning strategy. The upper half of FIG. 7 is a complete panel before division, and the bottom of the figure is two supbpanels formed after division. In the above subsection, we have completed the segmentation of the panel. And selecting a segment without any iroute as a basis for dividing the subbeep, namely a blank segment indicated by a dotted circle in the figure. As shown in fig. 7, the first segment line is used as the start coordinate of the supbpanel a, and the start coordinate of the blank segment is used as the end coordinate of the supbpanel a; and taking the ending coordinate of the blank segment as the starting coordinate of the supbpanel B, and taking the last segment line as the ending coordinate of the supbpanel B. Thus, the panel is divided into two supbpanels.

The first stage divides and reduces the solution space, and the divided supbpanel is completely independent, so the track distribution results before and after the first stage division are kept consistent, and the time cost is greatly reduced.

(2) Second stage partitioning strategy

The first stage partitioning strategy only considers partitioning a panel into irrelevant ones according to the blank segments, but there are still large-scale ones, and the existence of such ones makes the time cost of solving the ILP model too large. Therefore, a second stage partitioning strategy is proposed.

Since the first-stage partition strategy has found all the partition cases that do not involve the position of the conducting wire, we can consider selecting a suitable position in the supbpanel to achieve the purpose of partitioning the large-scale supbpanel. The invention sets two cuttable conditions: the wire count condition and the cut count condition further divide the supbpanel if and only if both cut conditions are met.

A 3-wire number condition is defined that a constant i _ num is introduced, which represents the maximum amount of iroute that can be tolerated in a subpanel. A supbpanel to be cut needs to satisfy | I_subpI _ num can become a partitioned candidate for the subpanel. In order to obtain the supbpanel with uniform iroute number after division, the invention selects the cutting position in the 1/3-2/3 interval of the supbpanel segmentation mark.

And 4, defining a cutting number condition, namely only considering the distribution condition of iroute after cutting, and possibly causing a bad influence on the final track distribution result by not considering the number of the iroute obtained by cutting. Thus, the invention introduces an i _ cut parameter that represents the number of cuts iroute that can be tolerated in a cut. The subbank to be cut can become a candidate subbank to be divided by meeting the requirement that irotectout < i _ cut. Wherein iroutect is the minimum number of cutting wires in all cutting positions of the suppanel. The current supbpanel will be divided if and only if the conditions a, b are all satisfied.

FIG. 8 shows two results of the first-stage partition strategy, i.e., supbpanela and B, at the top, and two solid rectangles at the bottom left₁And A₂The lower left dotted rectangle represents the removed iroute set. Assuming that two parameters i _ num and i _ cut are set to 4 and 3, respectively, the subblanb does not satisfy the wire count condition and cannot be divided. As can be seen from FIG. 8, there are 6 segments in the sequence of supbpanel A, and 7 segments are marked (including the left and right edges of supbpanel). We will label the segments within the (1/3,2/3) interval as candidate cutting positions, i.e. the three dotted lines that are hooked in the figure. Wherein, two broken lines cut off the wire 3, a broken line cut off the wire 2. One of the dotted lines satisfies the cut number condition, and finally, we cut the supbpanela along the position of the dotted line. The two iroutes at the position of the dotted line frame in the figure are cut open and removed to another container for storage. Wait for supbpanela₁And A₂After the allocation is finished, the removed iroutes are allocated to the proper track in a greedy way, namely, the track with the minimum cost is selected.

6. Partition method validity proof

The proposed first stage partitioning strategy partitions in panel units, analyzes a single panel: the number of the leads in the panel is I, the number of the tracks is T, and the number of the leads of the two divided subpanel is I₁，I₂And I ═ I₁+I₂。

Theorem 2: according to the ILP model, the number of decision variables of a panel is I multiplied by T, and the decision variables of the model are binary variables. Then the decision variable x can only take a value of 0 or 1. From this, the size of the panel search space before the non-division is 2^T×IThe size of the divided supbpanel search space is respectively

And

then, must have

Proof (counter-proof) hypothesis

Let a be 2^TSince T.gtoreq.1, a.gtoreq.2. Is reduced to a^I1+a^I2＞a^IEqual division on two sides of the inequality a^IThen 1/a is obtained^I1+1/a^I2Is greater than 1. Since a is ≧ 2, a^I2Not less than 2, then 1/a^I21/2 or less, and 1/a can be obtained by the same method^I1Less than or equal to 1/2. Thus 1/a^I1+1/a^I2Less than or equal to 1. Not in accordance with the original formula, inequality 2^T×I1+2^T×I2＜2^T×IIt is not true.

The proposed second-stage division strategy is divided on the basis of the first-stage division by taking the subpanel as a unit, and the solving scale of the current model is divided into units with finer granularity. The second stage division strategy is similar to the first stage in the principle of running time reduction, and the proving process is shown as a stage division proving and is not described in detail herein.

In conclusion, the proposed two-stage division strategy can effectively solve the problem of long solving time of the ILP model. And, the same quality of track allocation results as before division can still be obtained after the first stage division. By adjusting the wire number condition and the cutting number condition, the solving speed is improved on the premise that the second stage division can ensure that the solution quality is high enough.

Parallel strategy for SPTA Algorithm

Fig. 9 shows a parallel strategy implementation method adopted by the SPTA algorithm. All threads share a panel set that contains all wiring resources and a net set that includes both global and local. The SPTA algorithm performs parallel processing in two parts in the wiring process, one is to divide the panel into a plurality of small-scale subpanels,the other is to establish an ILP model for each independent supbpanel, i.e., the panel line and the supbpanel line in fig. 9. The invention combines the parallel mechanism of the panel level and the supbpanel level to obtain the parallel strategy based on the panel level and the supbpanel level. First, the SPTA performs a first stage division operation and a second stage division operation on the current panel. And obtaining a supbpanel set after the two-stage division strategy is completed. Next, the SPTA solves the current suppanel for ILP modeling and a removed iroutes reassignment operation after the solution. In particular, the parallel strategy of the present invention enables the two-phase partitioning operation and the ILP modeling solution to be performed simultaneously. I.e. the presence of p in FIG. 9₁To p_mA plurality of panels simultaneously carry out two-stage division operation, and a plurality of suppanel simultaneously carry out ILP modeling solving operation.

The SPTA parallel solving unit without adding the two-stage partitioning strategy is a panel, and because the wiring resources between the panel and the panel are mutually independent, namely the tracks, iroutes and obstacles, the panel-level parallel strategy is feasible and the optimal solution of the track distribution solved by the ILP method is not damaged. The SPTA parallel solving unit added with the first-stage division strategy is supbpanel, and the positions of iroutes and the distribution sequence of fixed iroutes are not changed during division, so that the track distribution result obtained by adding the SPTA algorithm of the first-stage division strategy is still the optimal solution. And adding the SPTA parallel solving unit of the second-stage division strategy into the finer granularity of the supbpanel. However, the second stage division strategy fixes the allocation sequence of the removed iroutes, that is, the allocation can be performed after the allocation of other iroutes in the subpanels which are not divided and belong to the removed iroutes is completed. Therefore, the final track allocation result obtained by adding the SPTA of the two-stage division strategy is an approximately optimal solution. Finally, experimental results demonstrate that parallel strategies based on the panel and the supbpanel levels are effective.

The above are preferred embodiments of the present invention, and all changes made according to the technical scheme of the present invention that produce functional effects do not exceed the scope of the technical scheme of the present invention belong to the protection scope of the present invention.

Claims (4)

1. A track distribution method based on integer linear programming and two-stage division strategies is characterized by comprising the following steps:

step S1, a parallel mechanism based on a panel level and a supbpanel level is provided, and a two-stage division strategy is provided based on the mechanism;

step S2, an integer linear programming model is proposed to solve the routability-driven orbit assignment problem to minimize the overlap between iroutes to significantly improve routability.

2. The track distribution method based on integer linear programming and two-stage partition strategy as claimed in claim 1, wherein in step S1, the two-stage partition strategy includes two sub-processes, which are a first-stage partition strategy and a second-stage partition strategy in sequence, wherein the first-stage partition strategy refines the panel into a plurality of independent and smaller-scale sub-panels, and the sub-panels after partitioning are completely independent, the second-stage partition strategy partitions the panel based on the first-stage partition strategy by using sub-panels as units, and partitions the current model solving scale into finer-grained units.

3. The method for track allocation based on integer linear programming and two-phase partition strategy according to claim 1, wherein in step S2, the routability-driven track allocation problem is described as: giving a group of net sets N to be subjected to track distribution, wherein the N comprises global nets and local nets, each net N comprises a plurality of pins and extracted wires iroutes, and P represents a group of panel sets, each panel consists of one row or one column of wiring units, the panels consisting of one row or one column of wiring units are horizontally or vertically oriented panels, and each panel respectively comprises a track set T to be distributed_pSet of all obstacles B_TAnd a set of iroutes I to be allocated_p(ii) a For each panel to be wired, set I_pAll iroutes in (1) are assigned to the set T_pThe goal is to minimize the total stacking cost, total barrier cost and total line length cost of track distribution solutions; thus, solving for routability drivesAn integer linear programming model of the moving trajectory assignment problem is as follows:

1) decision variables

There are only two allocation scenarios for iroute on the track: allocated and unallocated, define iroute i as a simple binary variable x in the track t allocation case_itAs shown in equation (1):

wherein the decision variable x is determined when iroute i is assigned to a track t_itHas a value of 1; otherwise, the variable x is decided_itIs 0;

2) constraint conditions

The exclusive constraint is in one allocation, and the exclusive constraint ensures that one iroute can be allocated to only one track in the panel, as shown in formula (2):

wherein for set I_pHas | T at any iroute i_pIf and only if | T is xit corresponding to | T_pThe equation holds when the sum of | xit equals 1; otherwise, an exclusivity constraint is violated;

3) overlap amount legitimacy constraints

The final overlapping cost is obtained by calculating the overlapping quantity of the panel sections, the whole panel is divided into a plurality of sections with unequal lengths, and after the section is finished, the formula (3) can be used for S_tThe number of overlaps per segment is determined for all segment elements in the track, and particularly, if no conductor is assigned to the k-th segment of the track t, the onum is obtained from equation (3)_tkThe value of (2) is-1, the overlapping quantity is a nonnegative natural number according to the meaning of the overlapping quantity, and the formula (4) sets a lower bound for the overlapping quantity to ensure the legality of the overlapping quantity;

wherein, the gum_tkIs an integer variable representing the number of overlaps of track t on the k-th segment, c_ikIs I_pWhether or not middle iroute i exists on the k-th segment, c_ikIs a known binary constant;

4) objective function

Since the goal of the track allocation problem is to minimize the costs incurred during routing, the optimized objective function can be represented by equations (5) - (8):

minimize α×blkcost+β×overlapcost+γ×wlcost (5)

wherein blkcost, overlapcost and wlcost are barrier cost, overlap cost and line length cost generated in panel, respectively; olen (I, b) represents I_pIroute i and B in the set_TThe length of overlap between obstacles b in the set; slen_tkA segment length representing the kth segment of track t; distance (x)_ijPin, j) represents the shortest distance between the position where iroute i is placed and other components in the net where i is located, i, j, pin are the same as the net n where i is located_i(ii) a Alpha, beta and gamma are self-defined parameters; due to the distribution process of the trackThe collision of the middle conductor with the obstacle is the most priority, so a is set to a very large value to ensure that the cost of the obstacle is as small as possible.

4. The orbit allocation method based on integer linear programming and two-phase partition strategy according to claim 3, wherein the process of calculating the wire length cost in the model optimization process for considering the running time is as follows: the method comprises the steps of extracting iroutes from local nets, distributing the iroutes to a track with the shortest Manhattan distance to the iroutes, respectively calculating the Manhattan distances between the iroutes and components in the same-line nets, and then distributing the obtained iroutes to the track with the shortest Manhattan distance, wherein when the Manhattan distances between the current iroute and other components are calculated in the global nets, only the distances between the current iroute and pins in the nets and the iroute of the determined tracks are considered, and the iroutes with undetermined positions are ignored in the process, and the distances calculated in the mode are used as the basis of the cost of optimizing the lines in the model optimization process.

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