JP2652968B2 - Automatic wiring method - Google Patents

Description

The present invention relates to an automatic wiring system for an integrated circuit or a printed circuit board.

[Conventional technology]

In the conventional automatic wiring method, the wiring area is treated as a grid, all the grids are secured in the storage area, and each grid is labeled based on the wavefront propagation from the grid corresponding to the terminal to be wired, and the wavefront is When you reach the target terminal, reverse the label and complete the route `` maze method ''
It is well known that a wiring area is shared between processors constituting a parallel computer to perform wavefront propagation in parallel.

This conventional technology is described in detail in "Prototype Research on Parallel Routing Processor" in the IPSJ Transactions on 1986.

Although not a parallel process, a conventional sequential automatic wiring method generates search lines from both terminals S and D for wiring, and searches for a search line from terminal S and a search line from terminal D. If does not intersect, the operation of generating a line orthogonal to those search lines as a new search line is repeated. When the search line derived from terminal S and the search line derived from terminal D intersect, a route is found. The "line segment search method" is well known (DWHightower,
'A Solution to Line−Routing Problem on the Conti
nuous Plane, 'Proc. 6th Design Automation Workshop, p
p.1-24,1969).

In addition, "Improved line search method" which improved "Line search method"
Is also well known. This generates a corner point at a distance from the corner of the obstacle that satisfies the design rule of the integrated circuit, and generates an escape line passing through the corner point. When generating an escape line, its length is determined so that the escape line satisfies the design rules. In other words, the escape line is extended from the corner point, and when the escape line reaches an allowable range close to the obstacle, the extension is stopped there. In this way, a search line is generated from both the terminals S and D for wiring. Then, an operation of enumerating escape lines intersecting with the search line generated from the terminal S and setting it as a new search line is repeated until the search line derived from the terminal S reaches the search line derived from the terminal D, When the route is reached, the search line is traced in the opposite direction to complete the wiring route. This is described in detail in the 1988 IEICE Technical Report, "Improved Line Segment Search Method Using Heap Search Tree".

In addition, there is a "parallel line search method" that improves the wiring speed by adapting the "improved line search method" to multi-layer wiring and further enabling parallel processing. Patent application filed on March 13 (3)｝.

This means that if the number of computers to be processed in parallel is n,
The wiring area is divided into n equal parts according to the wiring direction for each wiring layer,
Each computer has obstacles included in its assigned wiring area, and obstacles themselves exist in the adjacent area,
The attribute and the position of the obstacle where the area given by the obstacle extends to the own area according to the rule are stored. And
Each computer generates a corner point and an escape line associated with those obstacles in parallel.

Next, a computer in charge of an area including terminals to be connected (terminal S and terminal D) generates a search line from those terminals,
The position and length of the search line generated from the terminal S are sent to all other computers. The search line generated from the terminal D is added to a set of escape lines of the computer that generated the search line. Each computer checks whether or not an escape line intersecting with the search line exists in the area in which the computer is in charge based on the information about the search line sent thereto, and enumerates them. The process of sending those positions and lengths to all other computers is repeated.

If the listed escape lie line is included, it means that the wiring route has been found. Then, the intersecting escape line is traced in the opposite direction from the terminal D side to the terminal S side (called a back trace), thereby completing the path. This back tracing is performed by a computer that handles each escape line.

[Problems to be solved by the invention]

The method in which the above-mentioned "maze method" is parallelized requires a large amount of storage area to secure all the grids of the wiring area in the storage area, and can cope with an increase in the scale of the integrated circuit to be wired. Have difficulty. It is also difficult to respond to detailed design rules.

One method, the "line segment search method", has no problem with respect to storage space consumption and design rules, but there is no example of parallel processing by a parallel computer. It takes a lot of wiring time.

In addition, the "improved line segment search method" has no problem with respect to the consumption of the storage area, but the correspondence of the multilayer wiring is insufficient.
Similar to the “line segment search method”, there is no example of parallel processing by a parallel computer, and enormous wiring time is required for wiring a large-scale integrated circuit. Also, it is OK for the wiring to pass through like the through-hole prohibited area, but the area where the through-hole cannot be provided is outside the framework of the algorithm, so the wiring must adhere to the design rule of the through-hole prohibited area. Is difficult to do.

In addition, the "improved line segment search method" is made compatible with multilayer wiring,
In the "parallel line segment search method" that enabled parallel processing,
Regarding the handling of the through-hole forbidden area, the same problem as the “improved line segment search method” remains.

[Means for solving the problem]

According to the automatic wiring method of the first invention, in the automatic wiring processing of an integrated circuit having a multi-layer structure or a printed circuit board, a corner is located at a position away from a corner of an obstacle by a distance satisfying a design rule and at the same position on an adjacent layer. To generate a point, generate an escape line for avoiding obstacles according to the wiring direction of the layer to which the corner point belongs based on the corner point, and connect terminals between the escape lines. In the automatic wiring method characterized by searching for the route of the through-hole, a corner point is generated around the through-hole prohibited area in the same way as an obstacle, and an escape line is generated from the corner point. Line generation is performed taking into account only obstacles. It is constructed by eliminating the path going through the intersection of the Cape line.

Further, according to the automatic wiring method of the second invention, when parallel processing of automatic wiring processing of an integrated circuit or a printed circuit board is performed by computers connected to each other by an interconnection network, a wiring area is divided and received by each computer. Each computer has an obstacle or through-hole prohibited area included in its own wiring area, and an obstacle or through-hole prohibited area itself exists in the adjacent area. Memorizes the attributes and positions of obstacles and through-hole forbidden areas where the influence of the area and the through-hole forbidden area may affect your own area, and the distance that satisfies the design rule from the corners of those obstacles and through-hole forbidden areas An escape lane that generates a corner point only at a distance and avoids obstacles and through-hole prohibited areas based on the corner point The escape line is generated, but only the obstacles are taken into account when creating the escape line, and a route for connecting the terminals is searched from the escape line that intersects the area other than the through-hole prohibited area. The processing is performed by each computer in parallel.

[Action]

In the present invention, assuming that the number of computers to be processed in parallel is m, the wiring area is divided into n equal parts in accordance with the wiring direction for each wiring layer, and each computer has an obstacle included in its own wiring area. Or through-hole prohibited area, and obstacles and through-hole prohibited area itself exist in the adjacent area, but obstacles and other areas where the influence of the obstacle or through-hole prohibited area on your area by design rules may affect The attribute and position of the through-hole prohibited area are stored.

When generating a corner point at a distance that satisfies the design rules from the corners of these obstacles and through-hole prohibited areas, and generating an escape line based on the corner point, Each computer performs a series of processes in which only the obstacle is taken into consideration, in parallel.

Next, a computer in charge of an area including terminals to be connected (terminal S and terminal D) generates a search line from those terminals,
The position and length of the search line generated from the terminal S are sent to all other computers. The search line generated from the terminal D is added to a set of escape lines of the computer that generated the search line.

Each computer checks whether or not an escape line intersecting the search line exists in an area in which the computer is responsible based on the information about the search line sent thereto. Only the escape lines not included in the area are enumerated, and the processing is repeated by sending them as new search lines and transmitting their positions and lengths to all other computers.

Then, in the enumerated escape lines, the terminal D
If the search line generated from is included, it means that the wiring route has been found. And the crossing escapes
The path is completed by tracing the line in the opposite direction from the terminal D side to the terminal S side (referred to as back trace). This back tracing is performed by a computer that handles each escape line. Then, since the generated route becomes a new obstacle, each computer updates corner points and escape lines around them.

In the present invention, when generating a corner point,
A through-hole prohibited area is treated in the same way as an obstacle. When generating an escape line from a corner point, it is not treated as an obstacle. First, when searching for an escape line, a through-hole prohibited area is used. By not recognizing the route that passes through the intersection of the escape lines that intersect as a candidate for the wiring route, the framework of the “parallel line segment search method” can be extended to handle the design rule of the through-hole prohibited area , More suitable for practical use.

Further, in the present invention, processing for handling a through-hole prohibited area (generation of a corner point, generation of an escape line, search for an escape line) and the like can be performed in parallel, so that high-speed processing is possible. .

〔Example〕

FIG. 1 is a diagram showing the state of sharing of wiring areas by a plurality of computers according to an embodiment of the present invention. The wiring area in FIG. 1 is composed of two layers, the first layer is for wiring in the X-axis direction, and the second layer is a layer for wiring in the Y-axis direction. Then, there are n computers PE that perform parallel processing, and PE0, PE1,.
Each of _n-1 shares a part of the wiring region of both layers.

FIG. 2 is a diagram showing a state of preprocessing in the present embodiment. First, the main computer PE0 performs an input process of information regarding the wiring area, and as shown in FIG. 2, the obstacles 1-1, 1-2,
,.., And through terminals S, D,..., Which are a kind of obstacle, are transferred to the respective PEs in charge. Next, each of the PEs includes the obstacles 1-1, 1-2,...
-2, ..., terminal S, D, based on the information ... about tolerance only point corner in away P ₁₁ design rules from their _{corners, P 21, P 31, P} 41, P 12, P ₂₂ , P ₃₂ , P ₄₂ ,.

In this case, the obstacle 1-1, 1-2,..., The through-hole forbidden area 2-1, 2-2,..., The layer where the terminals S, D,. A corner point is also generated at a point of the same coordinate on the layer of the second layer. Then, each PE checks whether or not the generated corner point is at a position away from an obstacle or the like by more than the allowable range of the design rule, and removes the corner point that does not adhere to it.

Next, each PE corner points _{P 11, P 21, P 31} , P 41, P
₁₂ , P ₂₂ , P ₃₂ , P ₄₂ , ... escape lines L ₁₁ , L ₂₁ ,
L ₁₂ , L ₂₂ , ... are generated. The escape line is
When a line is extended from the corner point along the wiring direction of the layer, the line is extended to a position away from the first obstacle to be allowed by a design rule allowable range.

Since the processing of generating these corner points and the generation of the escape line can be performed using only information on the area in which each PE is in charge, communication between PEs is completely unnecessary, and all PEs are not required. After processing is completed, PE
Synchronize between

FIG. 3 is a view showing a state in which corner points and escape lines caused by terminals to be wired in the present embodiment are removed. Then, as shown in FIG. 3, the corner points and the escape lines resulting from the terminals S and D to be wired from now on are removed by the PE in charge of the terminals.

FIG. 4 is a diagram showing a state in which a search line is generated from terminals to be wired in this embodiment. As shown in FIG. 4, subsequently, search lines T ₁₁ , T ₁₂ , T ₂₁ , and T ₂₂ are generated from the terminal S and the terminal D. In other words, from the same coordinate point of the layer where the terminals S and D exist and the layer next to it (upper and lower), to a point separated from the obstacle etc. along the wiring direction of that layer by the allowable range of the design rule The lines are extended to search lines T ₁₁ , T ₁₂ , T ₂₁ , and T ₂₂ . This process is also performed by the PE in charge of the wiring area, the search lines T ₁₁ and T ₁₂ generated from the terminal S are sent to PE 0, and the search lines T ₂₁ and T ₂₂ generated from the terminal D are Is added to the set of escape lines for the PE responsible for

Then, information about the position and length of the search line T _11, T ₁₂ generated from the terminal S PE0 is forwarded to all other PE, therewith causing the escape line intersecting searched in each PE. each
PE is an escape
Searches for a line and sends information about the position and length of the escape line to PE0. PE0 is included in a set of escape lines (set A) sent from each PE.
Check if there is any generated from terminal D, and if not, transfer set A again to each PE, and leave each PE to search for an escape line that intersects them outside the through hole prohibited area Is repeated until the search lines T ₂₁ and T ₂₂ generated from the terminal D are reached.

FIG. 5 is a diagram showing a state where the wiring route is completed in the present embodiment. As shown in FIG. 5, PE0 is completed terminal if you find the search line T _21, T ₂₂ generated from D, the route K and then by following the escape line intersecting therewith in the opposite direction in the set A I do. At the time of the above-mentioned search, a pointer is set for the case of following the backward direction.

Therefore, since the newly generated route K becomes a new obstacle, it is necessary to update the escape lines and corner points around them.

FIG. 6 is a diagram showing a state in which corner points and escape lines around wirings constituting a path newly generated in this embodiment are updated. As shown in FIG. 6, PE0 sends information on the newly generated route K to the PE in charge of the area in which they exist, and the PE that has received such information places the information in the wiring prohibited area around the route K. Removes the included corner points and the escape lines generated from the corner points, and removes the routing-prohibited areas (Escape lines are included in areas that are not a distance that meets the design rules. If the corner point itself is outside the wiring prohibited area, an escape line is regenerated from the corner point, and a corner point and an escape line are also generated around the route K. Processing is
At maximum, the degree of parallelism is equal to the number of bends in the route.

When the update of the escape line and the corner point in the wiring area is completed, the next wiring is repeated.

〔The invention's effect〕

As described above, the automatic wiring method of the present invention treats a through-hole prohibited area in the same way as an obstacle when generating a corner point, and generates an escape line from a corner point, It is not treated as an obstacle, and when searching for an escape line, the escape line that crosses in the through-hole prohibited area is not recognized as a candidate for the wiring route. Can be handled, and the design rule for the through-hole prohibited area can be handled, which has the effect of being more suitable for practical use.

Further, the automatic wiring method of the present invention can perform processing for handling a through-hole prohibited area (corner point generation, escape line generation, escape line search) and the like in parallel, so that high-speed processing can be performed. This has the effect of being possible.

[Brief description of the drawings]

FIG. 1 is a diagram showing the state of sharing of wiring areas by a plurality of computers according to one embodiment of the present invention, FIG. 2 is a diagram showing a state of preprocessing in this embodiment, and FIG. FIG. 4 is a view showing a state in which a corner point and an escape line caused by a terminal to be removed are removed, FIG. 4 is a view showing a state in which a search line is generated from a terminal to be wired in this embodiment, and FIG. FIG. 6 is a view showing a state in which a wiring route is completed, and FIG. 6 is a diagram showing corner points and escape points around wires constituting a route newly generated in this embodiment.
It is a figure showing signs that a line was updated. 1-1, 1-2, ~ ...... obstacle, 2-1 and 2-2, ~ ...... through holes forbidden region, D, S, ~ ...... terminals, K ...... path, L _11, L _21,
L ₁₂ , L ₂₂ , ... Escape line, P ₁₁ , P ₂₁ , P ₃₁ , P ₄₁ ,
P ₁₂ , P ₂₂ , P ₃₂ , P ₄₂ , ……… Corner point, PE0, PE1,
~PE _n-1 ...... _{calculator, T 11, T 12, T} 21, T 22, ~ ...... search line.

Claims (2)

(57) [Claims] In automatic wiring processing of an integrated circuit or a printed circuit board having a multilayer structure, a corner point is generated at a position away from a corner of an obstacle by a distance satisfying a design rule and at the same position on an adjacent layer. Generates an escape line for avoiding obstacles according to the wiring direction of the layer to which the corner point belongs based on the corner point, and searches for a route for connecting the terminals from among the escape lines In the automatic wiring method, a corner point is generated around a through-hole prohibited area as well as an obstacle, and an escape line is generated from the corner point. Escape line that intersects inside the through-hole prohibited area when searching for routes, considering only obstacles Automatic wiring scheme, characterized in that to eliminate a path through the intersection. 2. When parallel processing of automatic wiring processing of an integrated circuit or a printed circuit board is performed by computers connected to each other by an interconnection network, each computer is divided and assigned a wiring area. Obstacles and through-hole prohibited areas included in the wiring area in which they are in charge, and obstacles and through-hole prohibited areas themselves exist in the adjacent area,
Memorize the attributes and positions of obstacles and through-hole prohibited areas where the effects of those obstacles and through-hole prohibited areas affect your area by rules, and from the corners of those obstacles and through-hole prohibited areas A corner point is generated at a distance that satisfies the design rule, and an escape line is generated based on the corner point to avoid obstacles and through-hole prohibited areas. Each computer performs in parallel the process of searching for a route to connect terminals from among the escape lines that intersect in areas other than the through-hole prohibited area, taking into account only obstacles Automatic wiring method characterized by the following.