JPH09319788A - Parallel processing system by network - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a parallel processing system by a network accelerating conversion processing to mask producing data of design data. SOLUTION: In the parallel processing system working design data to convert- process to mask producing data by parallel processing by plural processors connected with a main processor through the network, the host computer 1 divides a design data area into plural blocks, sets a margin of a prescribed width outside by setting the boundary line of each block to be reference and provides graphic data in the overlapping area of this margin for all the blocks sharing the area by setting the graphic data as a processing object. Then by considering the difference performance between the respective processors 9 and 10 of respective computers 4 and 5 and a data quantity within each block stored in memories 7 and 8, data in each block is divided to the processors 9 and 10 of the respective computers 4 and 5 to execute parallel processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network parallel processing system for converting design data of an LSI or the like into exposure mask manufacturing data by parallel processing by a plurality of processing devices connected to a main processing device via a network. Regarding

[0002]

2. Description of the Related Art Conventionally, for example, data for LSI design is converted into mask manufacturing data for drawing (exposure), and a circuit for a reticle, a mask, a wafer, etc. is circuited by an electron beam drawing apparatus based on the mask manufacturing data. A method of drawing a design pattern to manufacture an LSI is used. Further, with the recent increase in the scale of LSIs (the appearance of VLSI and ULSI) and the increase in density, there is an increasing demand for shortening the processing time for creating drawing data (exposure data) for LSI manufacturing. Therefore, the data area of the chip is divided into a large number of data processing target areas for each layer, and each processing target area is assigned to a plurality of processors to perform parallel processing, for example, Japanese Patent Laid-Open No. 2-232772. Techniques have been proposed. In this technique, the data area of the LSI chip is divided into small areas having substantially the same data amount, and the load of the parallel processors is made uniform to perform parallel processing.

[0003]

However, the above-mentioned prior art has the following problems. That is, in the LSI pattern data processing device disclosed in Japanese Patent Laid-Open No. 2-232772, when the parallel processor performs the sizing process of the graphic data, the graphic data may be cut, or the overlapping of the graphic data cannot be confirmed. There is a defect. Further, the setting of the boundary line for dividing the pattern data area into the small areas having substantially the same data amount according to the layout of the LSI chip is complicated, and it cannot be said that the parallel processing is efficient. Further, for graphic data processing, it is necessary to equip a parallel processor having the same performance, which increases the design cost.

An object of the present invention is to solve the above-mentioned problems of the prior art, to speed up the conversion process of design data into mask manufacturing data, and to effectively utilize the existing equipment to reduce the design cost. It is to provide a parallel processing system by a network.

[0005]

In order to solve the above problems, the present invention has the following constitution. That is, in a parallel processing system by a network that processes design data and converts it into mask manufacturing data by parallel processing by a plurality of processing devices connected to the main processing device via a network, the main processing device and a network connected to the main processing device. Each processing device includes a processor for converting the design data into an internal data for processing, a plurality of design patterns, a processing program, a parallel processing target processing device under the network, and data related to each processor of these. The main processing unit divides the design data area into a plurality of blocks, sets a margin of a predetermined width on the outer side of the boundary line of each block, and stores the margin. The graphic data in the overlapping area is applied to all blocks that share the area. Graphic data is provided as a processing target, and the data of each block is distributed to the processor of each processing device in consideration of the performance difference of each processor of each processing device stored in the data storage unit and the amount of data in each block. It is characterized in that parallel processing is performed.

Further, the main processing unit sets the width of the margin provided outside the boundary line of the block to a value larger than the absolute value of the displacement amount for thickening or thinning the graphic in the block. Is preferred.

According to the above configuration, the main processing unit divides the design data area into a plurality of blocks for each layer, decomposes the polygonal design data in each block into a set of trapezoidal data, and divides the boundary line of each block. Based on the above, a margin of a predetermined width is set, and the graphic data in the area where the margin overlaps is stored in the data storage unit by making the graphic data to be processed in all blocks sharing the area. Further, the graphic data of each block is distributed to the processors of the respective processing devices for parallel processing in consideration of the performance difference between the respective processors of the respective processing devices and the amount of data in each block.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of a parallel processing system using a network according to the present invention will be described with reference to the drawings. 1 is an explanatory diagram showing a parallel processing system configuration example by a network, FIG. 2 is a flowchart showing a processing flow of the entire parallel processing system, FIG. 3 is an explanatory diagram showing an example of block division of an LSI chip area, and FIG. 4 is FIG. 7 is an explanatory diagram showing each block extracted from FIG. 5, FIG. 5 is an explanatory diagram showing an example of decomposing polygonal graphic data into trapezoidal data, FIG. 6 is an explanatory diagram showing a library reference example of graphic data in a block, and FIG.
10 to 10 are comparative explanatory views showing the results of the sizing processing of graphic data by a block having no margin and a block having a margin.

First, an example of the configuration of a parallel processing system using a network will be described with reference to FIG. In this embodiment, a loosely coupled system having a cluster configuration will be described. FIG.
In FIG. 1, reference numeral 1 denotes a host computer as a main processing unit, which files a plurality of design patterns as a library, a memory 2 as a data storage unit in which a processing program is stored, and a format conversion of design data into internal data for processing. It is equipped with a plurality of processors 3 as processing units for performing the above and starting application software.

Numerals 4 and 5 are computers connected to the host computer 1 through the data communication line 6, and the computers 4,5
Are equipped with memories 7 and 8 as data storage units and processors 9 and 10 for performing processing instructed by the host computer 1, respectively. These computers 4 and 5 can use existing workstations, personal computers, etc. connected by a network as processing devices. The computers 4 and 5 may have different memory capacities or different numbers of processors and different processing performance. These characteristics are stored in the memory 2 of the host computer 1 in advance.

The application of this system is
The configuration of the system for realizing parallel processing is not particularly limited. That is, as in the present embodiment, either or both of a single processor machine and a multiprocessor machine may be used as the processing device, or a tightly coupled system by one multiprocessor machine, a massively parallel machine, etc. It may be configured. Further, the number of CPUs equipped in the system may be any other than that provided by the server or hardware, and the system can be constructed by the existing device configuration.

Next, the flow of the operation for converting the mask manufacturing data from the design data by the above system will be described with reference to the flowchart shown in FIG. The LSI design pattern data (GDS) is once converted into internal format data unique to the system in layer units. As will be described later, this internal format data is constructed so that the LSI design area is divided into several small areas for each layer, and the figure data is distributed and held in each of the divided small areas. This small area is referred to as a block, and a plurality of layers that compose one design data are all divided into common blocks, which are allocated by the host computer 1 to each processor such as each computer 4, 5 in each block. The data in the above block is transferred from the host computer 1 to each computer 4, 5
Only blocks required for the above are transferred or copied, and parallel processing is performed by each processor in units of blocks (see FIG. 1). At this time, when there is a performance difference between the host computer 1 and each of the computers 4 and 5 connected to the network or between the processors of the computers 4 and 5, the host computer 1 and the graphics of the block Considering the number of data (density), the load is large (the number of data is large)
Blocks are automatically assigned to high-performance processors, and blocks with low load are automatically assigned to relatively low-performance processors. When the number of blocks is larger than the number of processors, the process of the next block is distributed to the processor which has finished the process of one block, and the above work is repeated until all blocks are converted. As a result, the parallel processing can be speeded up. Then, the plurality of layers in the internal format are subjected to OR processing, and the mask layers in the internal format are also combined. Also in this case, the processing is distributed to a plurality of processors in block units.

The host computer 1 and each computer 4, 5
In the above, the format-converted internal format data (mask unit) is input, the logical processing between figures and the sizing of figures are performed on the figure data in the block, and the processing results are individually output to the internal format. To do. The design rules are also verified for the internal format data. Here, the logical processing between figures includes the processing of performing AND, OR, NOT, etc. on the figure data, and the sizing of the figure includes the process of thickening or narrowing the figure by a certain width. The verification of the design rule is included in response to individual commands such as “check the part where the distance between figures is XX μm or less” with respect to the figure data that has been subjected to sizing, It is verified whether the graphic data is cut, no intersection (overlapping) occurs, no acute-angled pattern occurs, and a warning is given to notify.

In the present system, in the host computer 1 and the computers 4 and 5, when performing some processing on the internal format data in mask units, for example, logical processing between figures, sizing of figures, verification of design rules, etc. Since the internal graphic data is processed, information such as the processing status of blocks and processing results of other computers is not required at all. In this way, since the data divided into blocks are independent from each other, efficient parallel processing is possible in each computer.

Next, when the host computer 1, the computers 4, 5, etc. have finished the logical processing for the internal format data in mask units, the internal format data in mask units processed by the respective processors are transferred between figures between blocks. Are processed (specifically, a graphic overlapping in a margin area described later) is subjected to a logical process (OR process) to obtain mask manufacturing data. Also in this case, the processing is performed in block units on the host computer 1 and the computer 4,
It is performed by allocating to each processor such as 5. This mask manufacturing data is obtained by sequentially arranging unit mask data in one file (for example, MEBES, JE
OL, etc.), or may be composed of a plurality of files.

Next, a block division method of the chip area for causing the computers 4, 5 and the like connected by the network from the host computer 1 to perform parallel processing will be described. In FIG. 3, reference numeral 11 denotes a chip area of the LSI, and a block boundary line 12 is an area including polygon graphic data showing a circuit pattern designed in the chip area.
Divide into arbitrary blocks by. FIG. 5 shows a method of decomposing the polygonal figure data existing in each block into some trapezoidal data. FIG. 5 shows a case where trapezoidal decomposition is performed by drawing a horizontal line from the corners p and q of the polygon, which are concaves. Further, in the internal format, in addition to the graphic data that each block directly has, the library has graphic patterns that can be repeatedly referred to. The library can globally refer to the library reference data from each block with respect to the mask of one layer. FIG. 6 shows an example of referring to a library of graphic data in this block.

Further, each block divided by the block boundary line 12 is provided with a margin boundary line 13 having a constant width outside the block boundary line 12 with other blocks, so that the adjacent block blocks are adjacent to each other. Overlap regions 14 are formed inside and outside of 12. At this time, the width of the margin formed in each block is set to a value larger than the absolute value of the sizing amount of the figure.

FIG. 4 shows a state in which blocks with margins divided by the block boundary line 12 shown in FIG. 3 are individually extracted. At the time of block division, a trapezoidal group decomposed from one polygon may be divided over a plurality of blocks beyond the overlap area 14 due to a margin like a polygon e. The trapezoidal data in the overlap area is processed by having it as graphic data in all blocks sharing the area.

Here, in the block division of the chip area, the effect of providing a margin to the divided blocks will be specifically verified. As an example, when the sizing process is performed on the graphic data in the block, the result of the block having no margin and the result of the block having the margin will be compared and described.

In FIG. 7, when the graphic data A and B divided into two blocks with no margin by the block boundary line 12 as shown in FIG. 7A are minus-sized (thinned to a certain width), (b) As described above, the figure data A and B, which are originally one, are disconnected. In order to avoid this, it is necessary to be aware of the data of all adjacent blocks when processing a block, and it becomes difficult to handle the blocks independently.

On the other hand, as shown in FIG. 8A, in the case where a margin boundary line 13 is formed outside each block divided into two upper and lower blocks by the block boundary line 12, As mentioned above, the trapezoidal data in the overlap area between the margins is
All blocks that share the area are processed as graphics data. Therefore, the upper and lower blocks with margins are processed with the similar graphic data A and B, respectively. Next, after performing minus sizing as shown in (b), if the upper and lower blocks are joined by the block boundary line 12 as shown in (c), the entire graphic data is cut without cutting the graphic data A and B. Minus sizing is done. The graphic data A, B
As a result, the number of trapezoidal data is reduced from the initial two to three. Therefore, if the block with margin is used, it is possible to perform graphic processing without trouble even if the block is treated independently.

Next, in FIG. 9, as shown in FIG. 9A, the graphic data C and D divided into two blocks on the left and right with no margin by the block boundary 12 are plus-sized (thickened by a certain width). When the graphic data C and D originally separated from each other intersect (overlap) as in the case of b), a warning that "the graphic intersects" is issued at the time of verification. However, when the blocks are treated independently, it is not possible to confirm the intersection between the graphic data held by each of the plurality of blocks. Therefore, in order to verify a certain block, it is necessary to refer to the data of all the adjacent blocks, which makes the process complicated and time consuming.

On the other hand, as shown in FIG. 10A, when the margin boundary line 13 is formed outside each block divided into two blocks on the left and right by the block boundary line 12, As described above, the trapezoidal data in the overlapping area of the margins is processed by having it as graphic data in all blocks sharing the area. Therefore, processing is performed by giving the same graphic data C and D to each of the two blocks with margins on the left and right.

Next, if plus sizing is performed as shown in (b), it can be confirmed that the graphic data C and D intersect in each block. Therefore, in each computer that performs parallel processing, it is possible to verify the design rule and perform appropriate graphic processing, and thus it is possible to contribute to the speedup of parallel processing.

As described above, when the figure data in the chip area is divided into blocks, the figure data is divided into blocks with margins and the figure data is processed in parallel, thereby improving the efficiency of processing and increasing the speed of parallel processing. It becomes possible to contribute.

Although various preferred embodiments of the present invention have been described above, the present invention is not limited to the above-mentioned embodiments, and many modifications can be made without departing from the spirit of the invention. Of course.

[0027]

As described above, according to the present invention, the main processing unit divides the design data area into a plurality of blocks, and at the same time, the performance difference between the processors of the respective processing units stored in the data storage unit and the inside of each block. In consideration of the data amount, the data of each block is distributed to the processors of the respective processing devices to perform parallel processing. Therefore, it is possible to provide a parallel processing system using a network, in which the conversion processing of design data into mask manufacturing data is speeded up and the existing equipment is effectively used to reduce the design cost.

Further, when the graphic data in the chip area is divided into blocks, the graphic data is divided into blocks with margins and the graphic data are processed in parallel to improve the efficiency of the processing.
It is possible to contribute to the speedup of parallel processing.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a configuration example of a parallel processing system by a network.

FIG. 2 is a flowchart showing the flow of processing of the entire parallel processing system.

FIG. 3 is an explanatory diagram showing an example of block division of an LSI chip area.

FIG. 4 is an explanatory diagram in which each block is extracted from the chip area of FIG.

FIG. 5 is an explanatory diagram showing an example of decomposition of polygonal figure data into trapezoidal data.

FIG. 6 is an explanatory diagram showing an example of referring to a library of graphic data in a block.

FIG. 7 is an explanatory diagram showing a result of minus sizing of graphic data of a block having no margin.

FIG. 8 is an explanatory diagram showing a result of minus sizing of graphic data of a block with a margin.

FIG. 9 is an explanatory diagram showing a result of plus-sizing of graphic data of a block having no margin.

FIG. 10 is an explanatory diagram showing a result of plus sizing of graphic data of a block with a margin.

[Explanation of symbols]

 1 Host computer 2, 7, 8 Memory 3, 9, 10 Processor 4, 5 Computer 6 Data communication line 11 LSI chip area 12 Block boundary line 13 Margin boundary line 14 Overlap area

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number in the agency FI Technical indication location H01L 21/30 541M 21/82 C (72) Inventor Kiyotaka Mochizuki Nagano City Nagano Prefecture 711 Shinko Electric Industry Co., Ltd. (72) Inventor Satoshi Akutagawa 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu Limited (72) Inventor Yasufumi Ishihara 3--9-15 Kaigan, Minato-ku, Tokyo Issue within Japan NUS Co., Ltd.

Claims (2)

[Claims] 1. A parallel processing system by a network for processing design data and converting it into mask manufacturing data by parallel processing by a plurality of processing devices connected to the main processing device via a network, wherein the main processing device and Each processing device connected by a network relates to a processor that performs a process by converting the design data into an internal data format, a plurality of design patterns, a processing program, a parallel processing target processing device under the network, and each processor of these. The main processing unit divides the design data area into a plurality of blocks, and sets a margin of a predetermined width outside on the basis of the boundary line of each block. , All blocks sharing the graphic data in the area where the margin overlaps The data of each block is given to the processor of each processing device in consideration of the performance difference of each processor of each processing device stored in the data storage unit and the amount of data in each block stored in the data storage unit. A parallel processing system using a network, which distributes and performs parallel processing. 2. The width of a margin provided outside the boundary line of the block is set to a value larger than an absolute value of a displacement amount for thickening or thinning a graphic in the block. A parallel processing system based on the network according to Item 1.