JPS62108594A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS62108594A
JPS62108594A JP24703985A JP24703985A JPS62108594A JP S62108594 A JPS62108594 A JP S62108594A JP 24703985 A JP24703985 A JP 24703985A JP 24703985 A JP24703985 A JP 24703985A JP S62108594 A JPS62108594 A JP S62108594A
Authority
JP
Japan
Prior art keywords
hole
hybrid integrated
integrated circuit
metal member
melting point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24703985A
Other languages
Japanese (ja)
Inventor
新居崎 信也
隆 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP24703985A priority Critical patent/JPS62108594A/en
Publication of JPS62108594A publication Critical patent/JPS62108594A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は混成集積回路、特に高速、高周波回路に好適な
混成集積回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a hybrid integrated circuit, particularly a hybrid integrated circuit suitable for high-speed, high-frequency circuits.

〔発明の背景〕[Background of the invention]

混成集積回路は小形1機能ブロック化、高信頼性および
電気特性の向上等の利点があり、種々の回路に多用され
ている。該混成集積回路の製造方式は、大別すると厚膜
および薄膜に分類されるが、該両者は構成材料とプロセ
スを異にするのみで、回路基板の基本構成は同一である
Hybrid integrated circuits have advantages such as small size, single functional block, high reliability, and improved electrical characteristics, and are widely used in various circuits. The manufacturing methods for hybrid integrated circuits can be broadly classified into thick film and thin film, but both differ only in the constituent materials and processes, and the basic structure of the circuit board is the same.

すなわち、抵抗と配線がセラミック基板上に設けられ、
該基板上に能動素子、コンデンサ等の部品が搭載される
That is, the resistor and wiring are provided on the ceramic substrate,
Components such as active elements and capacitors are mounted on the substrate.

一方、日本マイクロエレクトロニクス協会編” I C
化実装技術” (昭和55年1月、工業調査会発行)の
第10頁に記載されているように、基板両面に配線系を
構成し、スルーホールで接続する技術がある。
On the other hand, edited by Japan Microelectronics Association” I C
As described on page 10 of ``Integrated Mounting Technology'' (January 1980, published by Kogyo Kenkyukai), there is a technology in which a wiring system is configured on both sides of a board and connected through through holes.

ところが、高周波回路および高速回路では、高周波のア
ース系を十分にとることが要望されている。すなわち配
線系とアースとの間を十分に短かい距離で接続すること
が要望されるが、平面構成では、小型化になるに伴って
十分なアース系、すなわちアース原点より十分に広く、
かつ短かいパターンでアース配線系を形成することが因
業である。
However, in high-frequency circuits and high-speed circuits, it is desired to provide a sufficient high-frequency grounding system. In other words, it is required to connect the wiring system and the ground at a sufficiently short distance, but with a planar configuration, as miniaturization progresses, it is necessary to connect the wiring system to the ground at a sufficiently short distance.
The key is to form a ground wiring system with a short pattern.

このため、従来技術は第2図(断面模式図)に示すよう
に、セラミック基板1の裏面2全体。
Therefore, as shown in FIG. 2 (schematic cross-sectional view), the conventional technology is based on the entire back surface 2 of the ceramic substrate 1.

をアースとし、該裏面2のアースと表面3の配線系、す
なわちランド部3Aに低融点はんだ7を介して結合した
搭載部品8の電極9とをスルーホール4により接続する
構造からなる。
is grounded, and the through hole 4 connects the ground on the back surface 2 to the wiring system on the front surface 3, that is, the electrode 9 of the mounted component 8 bonded to the land portion 3A via a low melting point solder 7.

このような構成からなる従来技術では、配線系(例えば
電極9)からスルーホール4までの距離が大であり、か
つスルーホール4部の導体厚さが薄いため、直流的およ
び交流的に無視できない抵抗が存在する。前者の抵抗は
ばらつきが大きく、いちがいに言うこと−はできないが
100mΩのオーダになることもある。後者の抵抗値は
前記文献P、198の式(下記(1)式)を用いて推定
すれば3〜5nHとなる。また高周波的にはスルーホー
ル4部のスキンデプスも影響してくる。
In the conventional technology with such a configuration, the distance from the wiring system (for example, the electrode 9) to the through hole 4 is large, and the thickness of the conductor in the through hole 4 portion is thin, so that it cannot be ignored in terms of DC and AC. Resistance exists. The resistance of the former has a large variation, and although it is impossible to say with certainty, it may be on the order of 100 mΩ. The latter resistance value is estimated to be 3 to 5 nH using the equation (formula (1) below) in the above-mentioned document P, 198. In addition, the skin depth of the 4th through hole also affects the high frequency.

ただし、Lsニストリップ導体の自己インダクタンス、
W:該導体の幅、L:該導体の長さ、μ、二真空の透磁
率。
However, the self-inductance of the Ls strip conductor,
W: Width of the conductor, L: Length of the conductor, μ, magnetic permeability in two vacuums.

〔発明の目的〕[Purpose of the invention]

本発明は上記にかんがみ、直流的および高周波的なイン
ダクタンスの低減および小形化をはかることができる混
成集積回路を提供することを目的とするものである。
In view of the above, it is an object of the present invention to provide a hybrid integrated circuit that can reduce DC and high frequency inductance and downsize.

〔発明の概要〕[Summary of the invention]

本発明は上記目的を達成するために、搭載部品の電極を
接続する電極部にスルーホールを形成し、該スルーホー
ルの内部に金属部材を充填することを特徴とする。
In order to achieve the above object, the present invention is characterized in that a through hole is formed in an electrode portion that connects the electrodes of a mounted component, and the inside of the through hole is filled with a metal member.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を図面にって説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図は本実施例である混成集積回路の断面模式図であ
る。同図の符号のうち第2図に示す符号と同一のものは
同一または該当する部分を示すものとする。
FIG. 1 is a schematic cross-sectional view of a hybrid integrated circuit according to this embodiment. The same reference numerals as those shown in FIG. 2 indicate the same or corresponding parts.

高周波、高速回路では、グランド(アース)に接続すべ
き対象配線系は、直接には能動素、子の端子であるが、
電位的に直接に接続できないものは、コンデンサを介し
て接続する。そこで。
In high-frequency, high-speed circuits, the target wiring system that should be connected to the ground (earth) is directly the active element or child terminal, but
Anything that cannot be connected directly in terms of potential is connected via a capacitor. Therefore.

本実施例では、基板1上の搭載部品の接続ランド5と基
板1の裏面アース2とを直接にスルーホール4により接
続し、該スルーホール4の内部に金属部材1例えばPb
50〜95%の高融点はんだ6を棒状またはペースト状
に充填してリフローを行う。したがって、スルーホール
4の内部には、高融点はんだからなる金属部材6が充填
される。
In this embodiment, the connection land 5 of the mounted component on the board 1 and the back ground 2 of the board 1 are directly connected through the through hole 4, and a metal member 1, for example, Pb is inserted into the through hole 4.
Reflow is performed by filling 50 to 95% high melting point solder 6 in the form of a rod or paste. Therefore, the inside of the through hole 4 is filled with a metal member 6 made of high melting point solder.

次に上記金属部材6上に、これよりリフロ一温度が低い
はんだ(通常−Ag人共品はんだ)ペーストを印刷した
後、コンデンサ等の部品8を搭載してリフローを行い、
低融点はんだ7により前記接続ランド5とスルーホール
4部とを接続する。このようにすれば、アースをとるべ
き部品8の電極9の直下に、金属部材6で充填されたス
ルーホール4を形成することができるので、該スルーホ
ール4を介して基板裏面2のパターンと接続できる。
Next, after printing a solder paste with a lower reflow temperature than this on the metal member 6 (usually - Ag solder), components 8 such as capacitors are mounted and reflowed,
The connection land 5 and the through hole 4 are connected by a low melting point solder 7. In this way, the through hole 4 filled with the metal member 6 can be formed directly under the electrode 9 of the component 8 to be grounded, so that the pattern on the back surface 2 of the substrate can be connected to the pattern on the back surface 2 of the substrate through the through hole 4. Can be connected.

本実施例によれば、スルーホール4に充填された金属部
材6により、平坦性がほぼ確保されているため1部品8
の搭載工程では従来技術を適用することが可能である。
According to this embodiment, flatness is almost ensured by the metal member 6 filled in the through hole 4, so one part 8
Conventional technology can be applied to the mounting process.

〔発明の効果〕〔Effect of the invention〕

以上説明したように1本発明によれば、アースをとるべ
き対象物とアースとを金属部材により直接に接続できる
ので、直流抵抗は約1mΩ程度の小さな値となり、また
交流的にはインダクタンスは0.5〜InHの小さな値
となり。
As explained above, according to the present invention, the object to be grounded and the ground can be directly connected by a metal member, so the DC resistance becomes a small value of about 1 mΩ, and the inductance is 0 in terms of AC. It becomes a small value of .5 to InH.

さらに数Glkの高周波回路およびサブn5ecの高速
回路に適用することが可能である。
Furthermore, it is possible to apply to several Glk high-frequency circuits and sub-N5EC high-speed circuits.

なお2本発明によれば、スルーホール部と電極ランドと
を同一場所に形成できるため、小形化をはかることが可
能である利点がある。
In addition, according to the present invention, the through-hole portion and the electrode land can be formed at the same location, so there is an advantage that it is possible to achieve miniaturization.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係わる混成集積回路の一実施例の断面
模式図、第2図は従来の混成集積回路の断面模式図であ
る。 1・・・基板、2・・・裏面、4・・・スルーホール。 5・・・ランド部、6・・・金属部材、7・・・低融点
はんだ、8・・・搭載部品、9・・・電極。 第 1図 ど 第20
FIG. 1 is a schematic cross-sectional view of an embodiment of a hybrid integrated circuit according to the present invention, and FIG. 2 is a schematic cross-sectional view of a conventional hybrid integrated circuit. 1... Board, 2... Back side, 4... Through hole. 5... Land portion, 6... Metal member, 7... Low melting point solder, 8... Mounting component, 9... Electrode. Figure 1, Figure 20

Claims (1)

【特許請求の範囲】 1、搭載部品の電極を接続する電極部にスルーホールを
形成し、該スルーホールの内部に金属部材を充填するこ
とを特徴とする混成集積回路。 2、上記スルーホール内に充填される金属部材として高
融点はんだを用いると共に、搭載部品の接続用はんだと
して低融点はんだを用いることを特徴とする特許請求の
範囲第1項記載の混成集積回路。
[Scope of Claims] 1. A hybrid integrated circuit characterized in that a through hole is formed in an electrode portion for connecting an electrode of a mounted component, and the inside of the through hole is filled with a metal member. 2. The hybrid integrated circuit according to claim 1, wherein a high melting point solder is used as the metal member filled in the through hole, and a low melting point solder is used as the solder for connecting the mounted components.
JP24703985A 1985-11-06 1985-11-06 Hybrid integrated circuit Pending JPS62108594A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24703985A JPS62108594A (en) 1985-11-06 1985-11-06 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24703985A JPS62108594A (en) 1985-11-06 1985-11-06 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS62108594A true JPS62108594A (en) 1987-05-19

Family

ID=17157503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24703985A Pending JPS62108594A (en) 1985-11-06 1985-11-06 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS62108594A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01139367U (en) * 1988-03-17 1989-09-22
JPH02125364U (en) * 1989-03-27 1990-10-16
US5051869A (en) * 1990-05-10 1991-09-24 Rockwell International Corporation Advanced co-fired multichip/hybrid package
JPH0521412U (en) * 1991-08-29 1993-03-19 太陽誘電株式会社 Inductor
US5243142A (en) * 1990-08-03 1993-09-07 Hitachi Aic Inc. Printed wiring board and process for producing the same
JP2006303725A (en) * 2005-04-18 2006-11-02 Audio Technica Corp Capacitor microphone

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01139367U (en) * 1988-03-17 1989-09-22
JPH02125364U (en) * 1989-03-27 1990-10-16
US5051869A (en) * 1990-05-10 1991-09-24 Rockwell International Corporation Advanced co-fired multichip/hybrid package
US5243142A (en) * 1990-08-03 1993-09-07 Hitachi Aic Inc. Printed wiring board and process for producing the same
DE4125879C2 (en) * 1990-08-03 2000-07-27 Hitachi Aic Inc Printed circuit boards and processes for their manufacture
JPH0521412U (en) * 1991-08-29 1993-03-19 太陽誘電株式会社 Inductor
JP2006303725A (en) * 2005-04-18 2006-11-02 Audio Technica Corp Capacitor microphone

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