JPH01173779A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH01173779A JPH01173779A JP33282387A JP33282387A JPH01173779A JP H01173779 A JPH01173779 A JP H01173779A JP 33282387 A JP33282387 A JP 33282387A JP 33282387 A JP33282387 A JP 33282387A JP H01173779 A JPH01173779 A JP H01173779A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- substrate
- solder
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910000679 solder Inorganic materials 0.000 abstract description 11
- 238000000034 method Methods 0.000 abstract 1
- 238000005476 soldering Methods 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/184—Components including terminals inserted in holes through the printed circuit board and connected to printed contacts on the walls of the holes or at the edges thereof or protruding over or into the holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は高周波アンプ、ミキサなどの混成集積回路に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to hybrid integrated circuits such as high frequency amplifiers and mixers.
第２図は従来の混成集積回路の構成の一例を示す図であ
り、（ａ）は上面、（ｂ）は正面、（Ｃ）は下面をそれ
ぞれ示している。第２図において、基板１の表面には信
号ラインパターン２とその近くにアース用のランド６が
被着しており３両者間にはチップ部品であるチップコン
デンサ３が跨って装着されている。ランド６はスルーホ
ール４を介して裏面のアースパターン７に接続している
。FIG. 2 is a diagram showing an example of the configuration of a conventional hybrid integrated circuit, in which (a) shows the top surface, (b) shows the front surface, and (C) shows the bottom surface. In FIG. 2, a signal line pattern 2 and a grounding land 6 are attached to the surface of a substrate 1, and a chip capacitor 3, which is a chip component, is mounted astride between the two. The land 6 is connected to the ground pattern 7 on the back side via the through hole 4.
従来の混成集積回路は上記のような構成を有しているの
で、チップコンデンサ３を装着するためには基板１の表
面にアース用のランド６を設ける必要があり、形状が大
きくなってしまうという欠点があっｆｃ。また裏面のア
ースにスルーホール４で接続していたために、アースに
電位差が生じてしまい特性を悪くしてしまうという欠点
があった。Since the conventional hybrid integrated circuit has the above-mentioned configuration, it is necessary to provide a grounding land 6 on the surface of the substrate 1 in order to mount the chip capacitor 3, which increases the size of the circuit. There are flaws. Furthermore, since the through hole 4 was connected to the ground on the back side, there was a drawback that a potential difference was generated between the grounds and the characteristics were deteriorated.
したがって本発明の課題はアースランドを基板表面に設
ける必要のない混成集積回路を提供することにある。SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a hybrid integrated circuit which does not require an earth land on the surface of the substrate.
本発明は高周波アンプ、ミキサ等の混成集積回路におい
て、基板に穴を開け、コンデンサあるいは抵抗等のチッ
プ部品をその穴の中に挿入し基板の表面、裏面の導電体
にそれぞれで接続して構成された混成集積回路である。The present invention is a hybrid integrated circuit such as a high-frequency amplifier or mixer, which is constructed by making a hole in a substrate, inserting a chip component such as a capacitor or a resistor into the hole, and connecting it to a conductor on the front and back sides of the substrate. It is a hybrid integrated circuit.
第１図は本発明の一実施例の構成の全般を示した図であ
る。第１図において、セラミックあるいはガラスファイ
バ入りエポキシ樹脂等の基板１の上に信号ラインパター
ン２が印刷されており、その信号ラインパターン２とア
ースパターン７をチップ部品で接続する部分のパターン
に穴を開け、そこにチップコンデンサ３を挿入し、基板
表面の信号ラインパターン２と裏面の全面アースのパタ
ーン７を半田５等で接続する。FIG. 1 is a diagram showing the overall configuration of an embodiment of the present invention. In Fig. 1, a signal line pattern 2 is printed on a substrate 1 made of ceramic or glass fiber-containing epoxy resin, and a hole is formed in the pattern where the signal line pattern 2 and the ground pattern 7 are connected by a chip component. Open it, insert the chip capacitor 3 there, and connect the signal line pattern 2 on the front surface of the board and the entire surface ground pattern 7 on the back surface with solder 5 or the like.
第１図（ｂ）の右方には一部を引出して拡大した図を示
しである。チップコンデンサ３の上部電極８は上部に施
した半田９を介して信号ラインパターン２に接続され、
下部電極１ｏは下部に施した半田１１を介してアースパ
ターン７に接続しである。従ってアース用のランド６（
第３図）を設ける必要がなくなる。The right side of FIG. 1(b) shows a partially enlarged view. The upper electrode 8 of the chip capacitor 3 is connected to the signal line pattern 2 via solder 9 applied to the upper part.
The lower electrode 1o is connected to the ground pattern 7 via solder 11 applied to the lower part. Therefore, land 6 for grounding (
3) is no longer necessary.
なおチップコンデンサを挿入する孔は側壁には導電膜が
付着しないようにしておく。又、チップコンデンサ３と
スルーホールの透き間には半田が流れ込まないような処
理をしておく必要がある。Note that the hole into which the chip capacitor is inserted is made so that no conductive film adheres to the side wall. Further, it is necessary to take measures to prevent solder from flowing into the gap between the chip capacitor 3 and the through hole.
上の説明から分るように１本発明の混成集積回路におい
ては、基板１の表面の信号ラインパターン２と裏面の全
面アースのパターン７を半田５等で接続することにより
９表面にアースランド６を設ける必要がなく素子の面積
が縮減でき、又、直接裏面のアースパターン７に接続す
るため９部品装着部のアース電位差を小さくすることが
できて特性の改善ができ、更に、チップ部品の大部分が
挿入孔の中に入ってしまうので、厚さが大幅に減少する
。As can be seen from the above description, in the hybrid integrated circuit of the present invention, the signal line pattern 2 on the front surface of the substrate 1 and the entire ground pattern 7 on the back surface are connected with solder 5 or the like, thereby forming a ground land 6 on the surface 9. The area of the element can be reduced as there is no need to provide a The thickness is significantly reduced because the portion is inserted into the insertion hole.
すなわち本発明によれば、基板上の部品実装の効率が上
がり、形状が小型化できると同時に特性も向上する。That is, according to the present invention, the efficiency of mounting components on the board is increased, the size can be reduced, and the characteristics are also improved.
ｖｌｌ下口vll lower mouth
第１図は本発明の一実施例である混成集積回路の全体を
示した図、第２図は従来の混成集積回路の構成を示す図
である。
記号の説明：１は基板、２は信号ラインノくターン、３
はチップコンデンサ、４はスルーホール、５は半田、６
はアースランド、７はアースパターン、８は上部電極、
９は半田、１０は下部電極、１１は半田をそれぞれあら
れしている。
第１図
（ａ）FIG. 1 is a diagram showing the entirety of a hybrid integrated circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing the configuration of a conventional hybrid integrated circuit. Explanation of symbols: 1 is the board, 2 is the signal line turn, 3
is a chip capacitor, 4 is a through hole, 5 is solder, 6
is the earth land, 7 is the earth pattern, 8 is the upper electrode,
9 is solder, 10 is a lower electrode, and 11 is solder. Figure 1(a)
Claims (1)
，該チップ部品の両端電極を該基板の表面，裏面の導電
体パターンにそれぞれで接続して成ることを特徴とする
混成集積回路。1. 1. A hybrid integrated circuit characterized in that a hole is made in a substrate, a chip component is inserted into the hole, and electrodes at both ends of the chip component are connected to conductive patterns on the front and back surfaces of the substrate, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33282387A JPH01173779A (en) | 1987-12-28 | 1987-12-28 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33282387A JPH01173779A (en) | 1987-12-28 | 1987-12-28 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01173779A true JPH01173779A (en) | 1989-07-10 |
Family
ID=18259200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33282387A Pending JPH01173779A (en) | 1987-12-28 | 1987-12-28 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01173779A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006302851A (en) * | 2005-03-23 | 2006-11-02 | Kyocera Corp | Ceramic container, and battery using this, or electric double layer capacitor, and electric circuit board |
-
1987
- 1987-12-28 JP JP33282387A patent/JPH01173779A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006302851A (en) * | 2005-03-23 | 2006-11-02 | Kyocera Corp | Ceramic container, and battery using this, or electric double layer capacitor, and electric circuit board |
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