JPH11330662A - Printed board device - Google Patents

Printed board device

Info

Publication number
JPH11330662A
JPH11330662A JP13641798A JP13641798A JPH11330662A JP H11330662 A JPH11330662 A JP H11330662A JP 13641798 A JP13641798 A JP 13641798A JP 13641798 A JP13641798 A JP 13641798A JP H11330662 A JPH11330662 A JP H11330662A
Authority
JP
Japan
Prior art keywords
hole
chip component
chip
electrodes
buried
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13641798A
Other languages
Japanese (ja)
Other versions
JP3959841B2 (en
Inventor
Junichi Kimura
潤一 木村
Toao Ishida
東亜男 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP13641798A priority Critical patent/JP3959841B2/en
Publication of JPH11330662A publication Critical patent/JPH11330662A/en
Application granted granted Critical
Publication of JP3959841B2 publication Critical patent/JP3959841B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a printed board device in which size reduction is realized by increasing the mounting density of electronic part on a board. SOLUTION: In a printed board 33 comprising chip parts 17, 19, 20 each having electrodes at the opposite ends and a hole 16 to be buried with the first chip part 17, the hole 16 comprises through holes 11, 12 made at such distances as the opposite electrodes of the chip part 17 is included and a non- through hole 15 communicating the through holes 11, 12. The through holes 11, 12 are connected with the electrodes of the chip part 17 and the chip part 19 or 20 is mounted while sharing one electrode 21 in the hole 16 where the chip part 17 is buried thus realizing a printed board device having reduced size.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、高周波モジュール
等に使用するプリント基板装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board used for a high-frequency module or the like.

【0002】[0002]

【従来の技術】従来のプリント基板装置は図4,5に示
す構成であった。以下、図面に従って、従来のプリント
基板装置について説明する。1は高周波モジュールに使
用される高周波回路が表面に形成されたプリント基板で
あり、その表面には高周波回路を構成する電気部品5,
6,7を実装するためのランド2,3,4が形成されて
いる。このプリント基板1への電気部品の接合は、まず
図5(a)に示すように、ランド2,3,4にクリーム
半田8をスクリーンを用いて印刷し、次に図5(b)に
示すように電気部品5,6,7を両端の電極9,10,
11が前記クリーム半田上に載る様に実装し、リフロー
炉で前記クリーム半田を溶融し、プリント基板1のラン
ド2,3,4と電気部品5,6,7の電極9,10,1
1を半田接合する。プリント基板1の高周波回路および
ランド2,3,4の設計にあたっては、前記電気部品
5,6,7をランド2,3,4に半田接合する際にリフ
ロー時クリーム半田の流れにより、ランド2,3,4が
半田で接続しないように、図4に示すようにある一定の
間隔A,Bをあけてランド2,3,4を形成する。
2. Description of the Related Art A conventional printed circuit board device has the structure shown in FIGS. Hereinafter, a conventional printed circuit board device will be described with reference to the drawings. Reference numeral 1 denotes a printed circuit board on which a high-frequency circuit used in a high-frequency module is formed.
The lands 2, 3, and 4 for mounting 6, 7 are formed. 5A, cream lands 8 are printed on the lands 2, 3, and 4 using a screen, and then, as shown in FIG. 5B. Electrical parts 5, 6, 7 as shown in FIG.
11 is mounted on the cream solder, the cream solder is melted in a reflow furnace, and the lands 2, 3, 4 of the printed circuit board 1 and the electrodes 9, 10, 1 of the electric components 5, 6, 7 are mounted.
1 is soldered. In designing the high-frequency circuit of the printed circuit board 1 and the lands 2, 3, and 4, when the electric components 5, 6, and 7 are solder-bonded to the lands 2, 3, and 4, the lands 2 and 3, As shown in FIG. 4, the lands 2, 3, and 4 are formed at predetermined intervals A and B so that the lands 3 and 4 are not connected by solder.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、この様
な従来の構成では、高周波モジュールの大きさに大きく
影響する基板の大きさは電気部品の底面積、ランド間の
間隔、高周波回路パターンによって決定されるためにモ
ジュールの小型化には限界があるという問題があった。
However, in such a conventional configuration, the size of the substrate, which greatly affects the size of the high-frequency module, is determined by the bottom area of the electric components, the interval between lands, and the high-frequency circuit pattern. For this reason, there is a problem that there is a limit to downsizing the module.

【0004】本発明は、このような問題点を解決するも
ので高周波モジュール等の小型化を実現するプリント基
板装置を提供することを目的としたものである。
An object of the present invention is to solve such a problem and to provide a printed circuit board device which realizes miniaturization of a high-frequency module or the like.

【0005】[0005]

【課題を解決するための手段】この目的を達成するため
に本発明のプリント基板装置は、両端に電極を有するチ
ップ部品と、このチップ部品のうち第1のチップ部品が
埋設される埋設孔を有するプリント基板において、前記
埋設孔は前記第1のチップ部品の両電極が内包される距
離にそれぞれ設けられたスルーホールと、このスルーホ
ール間を連絡するように穿孔された非スルーホールとで
形成されるとともに前記スルーホールと前記第1のチッ
プ部品の電極とをクリーム半田で接続し、この第1のチ
ップ部品の電極を共用して第2のチップ部品を載置する
ものである。
In order to achieve this object, a printed circuit board device according to the present invention comprises a chip component having electrodes at both ends and a buried hole in which a first chip component of the chip component is buried. In the printed circuit board, the buried hole is formed by a through hole provided at a distance in which both electrodes of the first chip component are included, and a non-through hole formed so as to communicate between the through holes. At the same time, the through hole and the electrode of the first chip component are connected by cream solder, and the second chip component is mounted using the electrode of the first chip component in common.

【0006】これにより、高周波モジュール等の小型化
が達成できる。
[0006] Thus, downsizing of the high-frequency module and the like can be achieved.

【0007】[0007]

【発明の実施の形態】本発明の請求項1に記載の発明
は、両端に電極を有するチップ部品と、このチップ部品
のうち第1のチップ部品が埋設される埋設孔を有するプ
リント基板において、前記埋設孔は前記第1のチップ部
品の両電極が内包される距離にそれぞれ設けられたスル
ーホールと、このスルーホール間を連絡するように穿孔
された非スルーホールとで形成されるとともに前記スル
ーホールと前記第1のチップの電極とはクリーム半田で
接続し、この第1のチップ部品の電極部を共用して第2
のチップ部品を載置したプリント基板であり、第1のチ
ップ部品と第2のチップ部品の電極を共用するので、プ
リント基板の小型化が図れ、結果としてモジュール等の
小型化が図れる。また、第1のチップ部品の上に第2の
チップ部品を載置しているので、チップ部品の実装密度
を高めることができる。更に、チップ部品間の距離が短
くなるので、高周波性能が向上する。
DETAILED DESCRIPTION OF THE INVENTION The invention according to claim 1 of the present invention is directed to a printed circuit board having a chip component having electrodes at both ends and a buried hole in which a first chip component of the chip component is buried. The buried hole is formed by a through hole provided at a distance in which both electrodes of the first chip component are included, and a non-through hole formed so as to communicate between the through holes. The hole and the electrode of the first chip are connected by cream solder, and the electrode of the first chip component is shared with the second chip.
Since the electrodes of the first chip component and the second chip component are shared, the size of the printed board can be reduced, and as a result, the size of the module and the like can be reduced. In addition, since the second chip component is mounted on the first chip component, the mounting density of the chip components can be increased. Further, since the distance between the chip components is shortened, the high frequency performance is improved.

【0008】以下、本発明の実施の形態について、図面
を用いて説明する。図1(a)は本発明の実施の形態に
よるプリント基板装置の要部平面図である。11,12
は基板面にランド13,14を有するスルーホールで、
スルーホール11,12の間に非スルーホール15を穿
孔してチップ部品を埋設する埋設孔16を形成する。図
中の破線はチップ部品17,19,20であり、スルー
ホール11,12の間隔はチップ部品17を内包される
距離にそれぞれ設ける。18はチップ部品19,20の
一方の電極を装着するためのランドである。チップ部品
19,20はランド18とスルーホール11,12の間
にそれぞれ装着される。図1(b)は埋設孔16の寸法
図で、本実施の形態では1005サイズのチップ部品用
の埋設孔16としてスルーホール径30を0.6mm、非
スルーホール径31を0.8mm、スルーホールの間隔3
2を0.8mmとした。
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1A is a plan view of a main part of a printed circuit board device according to an embodiment of the present invention. 11,12
Is a through hole having lands 13 and 14 on the substrate surface,
A non-through hole 15 is formed between the through holes 11 and 12 to form a buried hole 16 for burying a chip component. The broken lines in the figure are the chip components 17, 19, and 20, and the distance between the through holes 11, 12 is set to the distance in which the chip component 17 is included. Reference numeral 18 denotes a land on which one of the electrodes of the chip components 19 and 20 is mounted. Chip components 19 and 20 are mounted between lands 18 and through holes 11 and 12, respectively. FIG. 1B is a dimensional view of the buried hole 16. In this embodiment, the buried hole 16 for a 1005 size chip component has a through hole diameter 30 of 0.6 mm, a non-through hole diameter 31 of 0.8 mm, and a through hole. Hole spacing 3
2 was set to 0.8 mm.

【0009】図2は本発明の実施の形態の斜視図で、図
2(a)に示すように、チップ部品17を埋設孔16に
埋設し、図2(b)に示すように、クリーム半田22を
チップ部品17の電極21とスルーホール11,12の
ランド13,14と、ランド18に印刷し、チップ部品
19,20を実装する。このように実装された基板をリ
フロー炉に通して半田付けを行う。これにより、チップ
部品17の電極21とスルーホール11,12の内面と
チップ部品19と20の電極23,24、及び、電極2
3,24とランド18が半田接合される。また、非スル
ーホール15によりスルーホール11,12間は電気的
に絶縁されておりショートすることはない。なお、33
はチップ部品17が埋設される基板である。
FIG. 2 is a perspective view of an embodiment of the present invention. As shown in FIG. 2A, a chip component 17 is buried in a burying hole 16, and as shown in FIG. 22 is printed on the electrodes 21 of the chip component 17, the lands 13, 14 of the through holes 11, 12 and the land 18, and the chip components 19, 20 are mounted. The board thus mounted is passed through a reflow furnace to perform soldering. Thus, the electrodes 21 of the chip component 17, the inner surfaces of the through holes 11, 12 and the electrodes 23, 24 of the chip components 19 and 20, and the electrode 2
The lands 18 and the lands 18 are soldered. Further, the through holes 11 and 12 are electrically insulated from each other by the non-through holes 15, so that no short circuit occurs. Note that 33
Is a substrate in which the chip component 17 is embedded.

【0010】図3は本発明の実施の形態の埋設孔16を
用いた電気部品の配置を示した透視図である。図3
(a)は埋設孔16の上に3端子トランジスタ25を装
着したものであり、図3(b)はチップ部品26と埋設
孔16の配置を示す。
FIG. 3 is a perspective view showing an arrangement of electric components using the buried hole 16 according to the embodiment of the present invention. FIG.
3A shows a three-terminal transistor 25 mounted on the buried hole 16, and FIG. 3B shows the arrangement of the chip component 26 and the buried hole 16.

【0011】[0011]

【発明の効果】以上のように本発明によれば、隣接する
チップ部品のランドの共用化を図ることで実装間隔をな
くすチップ部品配置が可能になり、部品の実装密度を高
めることでプリント基板装置を小型化することができ
る。
As described above, according to the present invention, it is possible to dispose the chip components by eliminating the mounting intervals by sharing the land of the adjacent chip components, and to increase the component mounting density by increasing the component mounting density. The device can be downsized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)は本発明の実施の形態によるプリント基
板装置の要部平面図 (b)は同埋設孔の実施寸法を示す平面図
FIG. 1A is a plan view of a main part of a printed circuit board device according to an embodiment of the present invention, and FIG. 1B is a plan view showing practical dimensions of the buried hole.

【図2】(a)は同プリント基板装置の第1の組立工程
の要部斜視図 (b)は同第2の組立工程の要部斜視図
FIG. 2A is a perspective view of a main part of a first assembly process of the printed circuit board device. FIG. 2B is a perspective view of a main part of a second assembly process of the same.

【図3】(a)は同トランジスタの部品配置の透視図 (b)は同チップ部品配置の透視図FIG. 3A is a perspective view of the component arrangement of the same transistor, and FIG.

【図4】従来のプリント基板装置の要部斜視図FIG. 4 is a perspective view of a main part of a conventional printed circuit board device.

【図5】(a)は同クリーム半田印刷後の斜視図 (b)は同チップ部品実装後の要部斜視図5A is a perspective view after the cream solder printing, and FIG. 5B is a perspective view of a main part after the chip component is mounted.

【符号の説明】[Explanation of symbols]

11 スルーホール 12 スルーホール 15 非スルーホール 16 埋設孔 17 チップ部品 19 チップ部品 20 チップ部品 Reference Signs List 11 through hole 12 through hole 15 non-through hole 16 buried hole 17 chip component 19 chip component 20 chip component

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 両端に電極を有するチップ部品と、この
チップ部品のうち第1のチップ部品が埋設される埋設孔
を有するプリント基板において、前記埋設孔は前記第1
のチップ部品の両電極が内包される距離にそれぞれ設け
られたスルーホールと、このスルーホール間を連絡する
ように穿孔された非スルーホールとで形成されるととも
に前記スルーホールと前記第1のチップの電極とはクリ
ーム半田で接続し、この第1のチップ部品の電極部を共
用して第2のチップ部品を載置したプリント基板装置。
1. A printed circuit board having a chip component having electrodes at both ends and a buried hole in which a first chip component of the chip component is buried, wherein the buried hole is the first component.
The first chip is formed by a through-hole provided at a distance in which both electrodes of the chip component are included, and a non-through-hole formed so as to communicate between the through-holes. The printed circuit board device is connected to the electrode by cream solder, and the second chip component is mounted by sharing the electrode portion of the first chip component.
JP13641798A 1998-05-19 1998-05-19 Method for manufacturing printed circuit board device Expired - Fee Related JP3959841B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13641798A JP3959841B2 (en) 1998-05-19 1998-05-19 Method for manufacturing printed circuit board device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13641798A JP3959841B2 (en) 1998-05-19 1998-05-19 Method for manufacturing printed circuit board device

Publications (2)

Publication Number Publication Date
JPH11330662A true JPH11330662A (en) 1999-11-30
JP3959841B2 JP3959841B2 (en) 2007-08-15

Family

ID=15174679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13641798A Expired - Fee Related JP3959841B2 (en) 1998-05-19 1998-05-19 Method for manufacturing printed circuit board device

Country Status (1)

Country Link
JP (1) JP3959841B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012248805A (en) * 2011-05-31 2012-12-13 Elna Co Ltd Manufacturing method of print circuit board mounted with components
JP2018506860A (en) * 2015-02-15 2018-03-08 華為技術有限公司Huawei Technologies Co.,Ltd. Power pipe connection structure for power amplifier and power amplifier

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012248805A (en) * 2011-05-31 2012-12-13 Elna Co Ltd Manufacturing method of print circuit board mounted with components
JP2018506860A (en) * 2015-02-15 2018-03-08 華為技術有限公司Huawei Technologies Co.,Ltd. Power pipe connection structure for power amplifier and power amplifier
US10426036B2 (en) 2015-02-15 2019-09-24 Huawei Technologies Co., Ltd. Power tube connection structure of power amplifier and power amplifier

Also Published As

Publication number Publication date
JP3959841B2 (en) 2007-08-15

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