JPS62105525A - Semiconductor integrator circuit device - Google Patents

Abstract

PURPOSE:To prevent the gate insulating film of a MOS transistor TR from being polarized and to stabilize the operation of a semiconductor integrated circuit device by providing a diode which clamps the gate input voltage of the CMOS TR of the input circuit of a digital circuit part to the current voltage side on the side of the digital circuit part. CONSTITUTION:An analog/digital mixed type semiconductor integrated circuit device is provided with the digital circuit 1 as the 1st circuit part and an input circuit part 1a composed of a CMOS TR, and the 1st circuit part is operated at a specific voltage of 5V as an operating source voltage Vdd-Vss. Further, a linear circuit part 2 as the 2nd circuit part and an output circuit part 2a on the side of the circuit 2 are provided and this 2nd circuit part is operated at a specific voltage of 12V as an operating voltage Vcc higher than the voltage Vdd-Vcc. The diode D1 for gate input voltage clamping is connected between the connection point between the output circuit part 2a of the 2nd circuit part and the input circuit part 1a of the 1st circuit part and the voltage Vdd. Then input voltages to TRs M1 and M2 of the input circuit part 1a are clamped to prevent the gate insulating film from being polarized.

Description

[Detailed Description of the Invention] [Technical Field] The present invention is particularly effective when applied to semiconductor integrated circuit device technology and to a semiconductor integrated circuit device in which two types of circuits that operate at different power supply voltages are formed together. technology, such as CMOs that operate with relatively low supply voltages.
The present invention relates to a technique that is effective for use in an analog/digital mixed semiconductor integrated circuit device in which a 5-logic circuit and a linear circuit that operates at a relatively high power supply voltage are formed together.

[Background technology]

For example, a bipolar 276MO8 coexisting semiconductor integrated circuit device, as introduced in Nikkei McGraw-Hill, October 12, 1981 issue, page 52754111, published by Nikkei McGraw-Hill, is a so-called analog/digital mixed semiconductor integrated circuit device. Both analog and digital signals? Can be handled within one semiconductor integrated circuit device.

FIG. 3 shows an outline of a mixed analog/digital semiconductor integrated circuit device previously studied by the present inventors. In the semiconductor integrated circuit device shown in the figure, a digital circuit section 1 made up of a CMOS logic circuit and a linear circuit section 2 made up of bipolar transistors are formed together. At the same time, part of the output of the linear circuit section 2 is input to the digital section 1.

In this case, the digital circuit section 1 is constituted by a CMOS logic circuit, and has a predetermined power supply voltage Vdd-Vss (approximately 5V).
It can be operated by. Further, the linear circuit section 2 is constituted by a bipolar transistor, and is operated by a power supply voltage VCC (approximately 12 V), which is higher than the power supply voltage Vdd-V'sS (approximately 5 V).

Here, the output of the linear circuit section 2 is 0 MO
3) By being input to the input circuit g1b by the transistors M1 and M2, the signal is passed to the digital section 1 by the CMQS logic circuit. Note that the two circuit sections 1a and 2b are provided as an input interface for the digital section 10.

However, in the analog/digital mixed type semiconductor integrated circuit device described above, the digital circuit section 1 and the linear circuit s2
The inventors have found that the following problems are likely to occur due to large differences between the respective operating power supply voltages Vdd and VCC.

That is, the power supply voltage VCC on the linear circuit section 2 side, which is higher than the power supply voltage Vdd (approximately 5 V) of the digital circuit section 11Q, is applied to the gate inputs of the transistors M1 and M2 (0MO8) forming the input circuit section lb on the digital circuit section 1 side. (approximately 12v) may be applied. Then, as shown in FIG. 4, a large reverse bias voltage (Vcc-Vdd=
Approximately 7V) is applied. This reverse bias voltage (VCC-
When Vdd) is applied, residual ion polarization occurs in the thickness direction of the gate insulating film 19. When this ion polarization occurs, the threshold of the MOS transistor M1 changes,
It becomes difficult to turn it on. In other words, CMOS
The inventors have revealed that the input circuit section 2a including the transistors M1 and M2 does not operate normally.

In FIG. 4, reference numeral 11 denotes an n-type epitaxial layer, which serves as a pack gate of the p-channel MOS transistor M1. 12 is a p-type drain diffusion layer, 13 is a p-type source diffusion layer, and 14 is an n-type diffusion layer for taking out the back gate electrode. Further, 27 indicates an electrode made of aluminum or the like.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device technology in which the input operation of a CMOS circuit receiving an output from a circuit with a high power source is always performed normally.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief description of typical inventions disclosed in this application is as follows.

In an analog/digital mixed semiconductor integrated circuit device in which a linear circuit section that operates at a relatively high power supply voltage is formed together with a digital circuit section using transistors, the input circuit section of the digital circuit section is By providing a diode that clamps the gate input voltage of the constituent CMOS transistors to the power supply voltage side of the digital circuit section, the gate isolation of the CMOS transistors described above is achieved.
Preventing residual polarization from occurring in the film, thereby stabilizing the threshold characteristics of the MOS transistor,
This is intended to achieve the purpose of ensuring that the input operation of the digital circuit section is always performed normally.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows a circuit state of a main part of a semiconductor integrated circuit device to which the technology according to the present invention is applied.

The semiconductor integrated circuit device partially shown in the figure is a so-called analog/digital mixed type semiconductor integrated circuit device, in which two types of circuit sections, a first circuit section and a second circuit section, are formed together. ing. In this case, a digital circuit section 1 is formed as a first circuit section, and a linear circuit section 2 is formed as a second circuit section. Then, the linear circuit section 2
A part of the output is input to the digital section 1.

Furthermore, the digital circuit section 1 is mainly constituted by a CMOS logic circuit, and has a predetermined power supply voltage Vdd-Vss (approximately 5V
). The linear circuit section 2 is mainly composed of bipolar transistors, and the above power supply voltage Vdd-Vss (approximately sV), k
n+ can also be operated with a high voltage source W voltage Vcc (approximately 12V).

The output of the linear circuit section 2 is a bipolar transistor T
1 and a resistor R1 from an output circuit section 2a formed by CMOS transistors M1 and M2, the signal is passed to a digital section 1 formed from a CMOS logic circuit.

Here, in the semiconductor integrated circuit device according to the embodiment shown in FIG. A diode DI connected in the forward direction toward the Vdd side is provided. This diode D1 connects the gate input voltage Vg of the CMOS transistors Ml and M2 to the power supply voltage Vdd of the digital circuit section 1.
Clamp to the side. Specifically, the gate input voltage Vg of the CMOS transistors Ml and M2 is higher than the forward voltage Vf of the diode D1 (Vf valve 0.6 V) in accordance with the power supply voltage Vdd of the digital circuit section 1. It is designed to be clamped to prevent it from happening.

FIG. 2 shows an embodiment of the semiconductor structure near the input circuit section 1. In FIG.

In the embodiment shown in the figure, the diode D1 is composed of a pffl polycrystalline silicon layer 25 partially formed on a surface oxide film (field oxide film) 24 and an n-type polycrystalline 7937 layer 26. .

As a result, the thickness of the reverse bias voltage applied to the gate of the p-channel MO8) transistor M1 is determined by the difference between the power supply voltage (Vdd-Vss) on the digital circuit section 1 side and the power supply voltage VCC on the linear circuit section 2 side. Regardless of the roughness, the forward voltage Vf of the diode D1 (Vf 40.6
V) will be maintained below. This reliably prevents residual ion polarization from occurring in the gate insulating film under the gate electrode 18 of the p-channel transistor M1, thereby improving the stability of the operation of the input circuit section 1a. will be secured.

In FIG. 2, 9 is a p-type silicon semiconductor substrate, 10 is an n++ buried layer, 11 is an n-type epitaxial layer, and 23 is a p-type isolation expansion! ! The I layer, 25 is a phosphorus silicate glass film as a surface retention film, and 27 is an electrode made of vapor-deposited aluminum or the like.

Also, on the digital circuit section 1 side, p channel MO8)
The transistor M1 is formed by a p+ type drain 4 contact layer 12, a p type low melting layer 13, an n+ type multiple melting layer 14 for taking out the back gate electrode, and the like. The n-channel MOS transistor M2 is formed in the p-type well 15, and has an n+-type drain diffusion layer 16, an n+-type source diffusion layer 17, an n+-type scattering layer for taking out the pack gate electrode (not shown), and the like.

On the other hand, the bipolar transistor T on the linear circuit section 2 side
1 is formed on the n++-containing layer 10, and the p-type base diffusion layer 20.1 is formed on the n++-containing layer 10. It includes an n-type emitter diffusion layer 21, an n-type collector current collection widening layer 22, and the like.

〔effect〕

[11 For example, an IJ that operates at a relatively high power supply voltage together with a digital circuit section using CMOS transistors
In an analog/digital mixed semiconductor integrated circuit device in which a near circuit section is formed, a diode is provided that clamps the gate input voltage of a CMOS transistor constituting the input circuit section of the digital circuit section to the power supply voltage side of the digital circuit section. This prevents residual polarization from occurring in the gate insulating film of the CMOS transistor, thereby stabilizing the gate voltage characteristics of the MOS transistor, thereby stabilizing the input voltage of the digital circuit section. The effect is that the operation is always performed normally.

The invention made by the non-inventor has been specifically explained based on the examples above, but it goes without saying that this invention is not limited to the above examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the diode D1 may be a Schottky barrier diode or a p
Type Same diffusion layer as drain (nose) 13'kPMO8
A junction diode formed nearby and between the epitaxial layer and the epitaxial layer may be used.

[Application field]

Although the invention made by the present inventor is applied to the technology of analog/digital mixed semiconductor integrated circuit devices, which is the background field of application, the present invention is not limited to this, for example, pure MO3 The present invention can also be applied to technology for type semiconductor integrated circuit devices or digital-only semiconductor integrated circuit devices.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a circuit state of a main part of a semiconductor integrated circuit device to which the present invention is applied, FIG. 2 is a diagram showing an outline of a semiconductor structure in a part of the circuit shown in FIG. 1, and FIG. 4 is a diagram showing a circuit state of a part of a semiconductor integrated circuit device studied prior to the present invention, and FIG. 4 is an enlarged diagram showing a semiconductor structure of a part of the circuit shown in FIG. 3.

Claims (1)

[Claims] 1. A first circuit section configured by a CMOS circuit;
A second circuit section that is operated at a power supply voltage higher than the operating power supply voltage of the first circuit section is formed together with the first circuit section, and the output of the second circuit section is input to the first circuit section. A semiconductor integrated circuit device, characterized in that a diode is formed that clamps a gate input voltage of a CMOS circuit receiving an output from a second circuit section to a power supply potential side of the second circuit section. . 2. The semiconductor according to claim 1, wherein the first circuit section is composed of a digital circuit section using a CMOS logic circuit, and the second circuit section is composed of a linear circuit section using bipolar transistors. Integrated circuit device.