JPH0329325B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input protection circuit in an MIS (metal-insulator-semiconductor) logic circuit.

Conventionally, circuits as shown in FIGS. 1 and 2 are known as gate protection circuits in MIS logic input circuits.

These circuits are for protection resistor R and clamp
MISFET Q ₄ is used to prevent gate breakdown due to high voltage input.

In other words, for high voltage input,
The purpose is to clamp the high voltage input and prevent gate breakdown by the surface-eighth breakdown of MISFET Q ₄ or the breakdown operation of the junction diodes D and D' between the drain and the substrate.

However, it has been found that the conventional gate protection circuit has a problem in that the input circuit malfunctions due to negative undershoot of the input signal.

In other words, in the circuit shown in Figure 1, if the undershoot value is larger than the threshold voltage of the input transmission gate MISFET Q ₁ , the input transmission gate
Even if the gate of MISFET Q ₁ is held at ground potential, which is an off level, it will turn on and the input MISFET Q ₃ will be turned on.
The charge accumulated in the gate of the circuit leaks.

Also, as shown in Figure 2, even if the input is directly to the clocked inverter, as shown in Figure 3, if a negative undershoot is input, the drain of the clamp MISFET _Q4 D becomes a negative voltage, and the voltage between it and the substrate P is forward biased.
A parasitic lateral transistor with these as the emitter and base and the drain D of MISFET Q ₃ forming the clocked inverter as the collector,
The charge accumulated in the output of the clocked inverter will leak.

As shown in Figure 2, in devices that apply back bias to the substrate, the threshold voltage of the conventional clamping MISFET Q ₄ is larger in absolute value than the forward voltage V _F of the junction diode D. If an undershoot larger than |V _BB +V _F | is input, a current flows from the board to the input terminal P, which changes the board bias voltage and reduces the operating margin of the logic circuit. becomes.

In addition, as a MISFET protection device,
The one described in Japanese Patent No. 51-32511 is known.

The present invention was made to solve these problems, and to provide an MIS input protection circuit that also prevents malfunctions of logic circuits and input circuits due to negative undershoot of an input signal.

In one embodiment of the invention, for clamping
As the MISFET, one whose threshold voltage is smaller in absolute value than the threshold voltage of the MISFET constituting the logic circuit such as the input circuit and the threshold voltage of the parasitic lateral transistor is used.

Hereinafter, the present invention will be specifically explained with reference to Examples.

In a gate protection circuit as shown in FIG. 1 or 2, the threshold voltage of MISFET Q ₄ for clamping is set to the threshold voltage of MISFET Q 1 to MISFET Q ₁ that constitutes a normal logic circuit.
The absolute value is smaller than the threshold voltage of Q ₃ (about 0.8 to 1.2 V), for example, about 0.2 to 0.3 V. In general, the threshold voltage of a MISFET is determined by the surface impurity concentration of the channel, the quality and thickness of the gate insulating film, etc., but the channel It is desirable to control the surface impurity concentration. In other words, if the clamping diode _Q4 is an n-channel MISFET,
This can be achieved by selectively introducing n-type impurities into the surface of the channel region through the gate insulating film.

According to this embodiment, the gate breakdown prevention operation against a positive high voltage (in the case of an n-channel MISFET) is performed by the surface-eighth breakdown of the clamping MISFET _Q4 or by the pn junction diode D between the drain and the substrate, as in the conventional case. This is done by clamping at a predetermined voltage using breakdown.

Then, the negative (n channel) of the input signal
Regarding undershoot (in the case of MISFET), since the threshold voltage of clamping MISFET Q ₄ is small, it turns on at -0.2 to -0.3V and is clamped at this voltage. In the circuit shown in FIG. 1, since the transmission gate MISFET Q ₁ is not turned on, the information (charge) accumulated at the gate of the input MISFET Q ₃ can be prevented from being destroyed.

Also, in the circuit shown in Fig. 2, the base-emitter voltage of the parasitic lateral transistor is clamped at the above voltage (0.2 to 0.3V) and suppressed to below the threshold voltage of the lateral transistor (approximately 0.7V). MISFET Q ₃ configuring the collector
Destruction of information (charge) stored in the drain can be prevented.

As shown in the figure, even in the case where the substrate back bias voltage -V _BB is applied, even if the negative undershoot of the input signal becomes larger than |V _BB +V _F |, the MISFET Q ₄ is on and clamps the input voltage to −0.2 to −0.3V, so diode A′ is either reverse biased or forward biased above its threshold voltage V _F Therefore, the substrate back bias voltage does not fluctuate and the operating margin does not decrease.

The present invention can be applied to various input circuits in addition to the input circuits described above. That is,
In addition to the transmission gate MISFET or the clocked inverter circuit, any other method may be used. Further, the MISFETs constituting each circuit can be similarly applied even if they are p-channel type MISFETs.

[Brief explanation of drawings]

1 and 2 are circuit diagrams each showing an example of an MIS input protection circuit, and FIG. 3 is a structural sectional view of a part of the circuit of FIG. 2.

Claims (1)

[Claims] 1. An input terminal, a protective resistor, and a second semiconductor region formed in the first semiconductor region of the first conductivity type.
conductivity type second and third semiconductor regions and the second and third conductivity type semiconductor regions;
A clamping MISFET having a first gate electrode formed on the first semiconductor region between the semiconductor regions with a gate insulating film interposed therebetween; 5 semiconductor region and a second gate electrode formed on the first semiconductor region between the fourth and fifth semiconductor regions via a gate insulating film.
MISFET, the second semiconductor region is coupled to the input terminal via the protection resistor, the first gate electrode and the third semiconductor region are coupled to a reference potential point of the circuit, and the second semiconductor region is coupled to the input terminal via the protection resistor; The gate electrode is coupled to the second semiconductor region, and the absolute value of the threshold voltage of the clamping MISFET is the absolute value of the forward voltage of the pn junction formed by the second semiconductor region and the first semiconductor region. A semiconductor integrated circuit device, wherein the protection resistor is configured without forming a pn junction with the first semiconductor region.