JPH0639455Y2 - MOS device protection circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a protection circuit in a MOS device, especially in a complementary MOS device.

[Conventional technology]

The input terminal of a complementary MOS device is usually connected to the gate of a MOS transistor. A protection circuit is inserted in the input terminal to prevent damage to the MOS transistor from high voltage caused by external noise or static electricity. FIG. 4 shows an example of a conventional input protection circuit. In the figure, a diode 4 is inserted between the input terminal 1 and the power supply (+) terminal 9, and a diode 6 is inserted between the input terminal 1 and the power supply (-) terminal 10.
When high voltage noise or surge is applied to the input terminals from the outside, the diodes 4 and 6 are forward biased,
Breaking down in the opposite direction, MOS transistor 7
And limits the voltage on the gates of 8 and 8 to protect the MOS transistor.

In the protection element shown in FIG. 4, an input voltage larger than the power supply voltage supplied to the power supply terminals 9 and 10 cannot be applied to the protected MOS transistor. Therefore, in order to increase the input voltage range, the protection element shown in FIG. So that the MOS transistor 7
It has also been proposed in Japanese Patent Laid-Open No. 53-76677 to connect two diodes 3 and 4, 5 and 6 in series in the opposite directions between the gates of 8 and 8 and the power supply terminals 9 and 10, respectively. .

[Problems to be solved by the invention]

The input protection diode as shown in FIG. 1 cannot be entirely formed in the semiconductor substrate, and one diode group is formed by forming polycrystalline silicon on an oxide film on the semiconductor substrate. To form a pair of diodes. The PN junction of a polycrystalline silicon diode is not stable, and it was desirable to form it in a semiconductor substrate in view of its characteristics. Therefore, an object of the present invention is to provide a structure in which an input protection circuit having a large input voltage range is formed in a semiconductor substrate.

[Means for solving problems]

A MOS element protection circuit device according to the present invention comprises a first region of opposite conductivity type formed in a semiconductor substrate of one conductivity type and the one conductivity type formed in the first region at a distance. Second and third regions, fourth and fifth regions of the opposite conductivity type formed apart from each other in the second region and forming a diode with the second region, respectively. Three
Of the opposite conductivity type, which are formed separately from each other in the second region and each of which constitutes a diode, and the fourth region and the fourth region in the second region. An eighth region of one conductivity type having a higher impurity concentration than the second region formed between the fifth region and the fifth region, and between the sixth region and the seventh region in the third region. A protection circuit device for a MOS element, which comprises a ninth region of one conductivity type having a higher impurity concentration than the formed third region, wherein the fifth and sixth regions are provided with an input of the MOS device. A terminal is connected, a first power supply terminal is connected to the fourth region, and a second power supply terminal is connected to the seventh region.

〔Example〕

Before explaining the embodiment of the present invention, the basic structure of this embodiment will be described first.

FIG. 1 is an equivalent circuit diagram of the input protection circuit of the present invention, and FIG. 2 is a sectional view of the input protection circuit according to a reference diagram for explaining the basic structure of the present embodiment. In the equivalent circuit, the first diode 3 and the second diode 4 are connected in opposite polarities and are inserted between the input terminal 1 and the power supply (+) terminal 9 via the protection resistor 2. In addition, the third diode 5
The fourth diode 6 and the fourth diode 6 are connected to each other in opposite polarities, and are inserted between the input terminal 1 and the power source (-) terminal 10 through the protective resistor 2.

Referring to FIG. 2 of the reference diagram of this embodiment realizing such an equivalent circuit, the low concentration N type diffusion region 14 (impurity concentration 10 ¹⁷
cm ⁻³ ). High concentration P type diffusion regions 12 and 13 (impurity concentration
10 ¹⁸ to 10 ²⁰ cm ⁻³ ) and the first diode 3 and the second diode 4 are formed by the respective PN junctions. Similarly, other third diode by the low concentration N-type diffusion region 15 (impurity concentration 10 ¹⁷ cm ^-3) high concentration P-type diffusion in regions 16 and 17 (impurity concentration 10 ¹⁸ ~10 ²⁰ cm ^-3) 5th and 4th
The diode 6 is formed. Here, the low-concentration N-type semiconductor substrate 20 (impurity concentration 10 ¹⁵ cm ⁻³ ) is formed in the low-concentration P-type diffusion region.
19 (impurity concentration 10 ¹⁶ cm ⁻³ ) is formed, and low concentration N-type diffusion regions 14 and 15 are formed therein. N-type semiconductor substrate 2
A positive power supply voltage is applied to 0, and a negative power supply voltage is applied to the p-type diffusion region 19.

Now, the potential of the power (+) terminal 9 is 5V, the power (-) terminal 10
To 0V as the logic level at the input terminal 1
Consider the case of applying a voltage of 20V. The reverse breakdown voltage of the diode is controlled to about 20 V by implanting 10 ¹⁷ cm ⁻³ ions of, for example, P atoms into the low concentration N type diffusion region 15. When OV is applied to the input terminal 1, the third diode 5 and the fourth diode 6 are
It is off. Further, about 15 V is applied to the first diode 3 and the second diode 4 which are connected in opposite polarities, but the breakdown voltage is not reached, so that they are in the off state. When a voltage higher than 25V is applied due to external noise or the like, the first diode 3 breaks down and the second diode 4 is forward biased, so only 20V is applied to the gate of the MOS transistor. . Since the withstand voltage of a normal MOS transistor is about 40V, it is protected without being destroyed. Even when a negative high voltage is applied, the same operation is performed and the MOS transistor is protected.

Positive / negative voltage as a logic level at the input terminal 1, for example, +10
When V and -10V are applied, the operation according to the above is performed. When a normal voltage, that is, ± 10 V is applied to the input terminal 1, the diode is in an off state, and when a high voltage is applied due to external noise or the like, the diode breaks down to protect the MOS transistor.

Here, the low concentration P-type diffusion region 19 is a p-type high concentration diffusion region.
The power source terminal 10 connected to 18 fixes the power source (-) to the power source (-), and the low concentration N type semiconductor substrate 20 is fixed to the power source (+) by the power source terminal 9 connected to the N type high concentration region 11.
No leakage current flows because the PN junction is always reverse biased.

In this embodiment, the protection circuit is formed on the N-type semiconductor substrate 20, but it can be realized on the P-type semiconductor substrate.

However, in the input protection circuit formed as shown in FIG.
There is a problem that an inversion layer is formed between the high-concentration P-type diffusion regions 12 and 13 and between the high concentration P-type diffusion regions 16 and 17, and channel leakage occurs.

FIG. 3 is a structural sectional view of an embodiment of the present invention. Compared with the reference diagram of FIG. 2, in order to prevent an inversion layer from being formed between the high-concentration P-type diffusion regions 12 and 13 and between the high-concentration P-type diffusion regions 16 and 17, these two layers are prevented. High concentration N between high concentration P type diffusion regions 12, 13 and 16, 17.
The mold diffusion regions 21 and 22 are provided as channel stoppers to prevent formation of the inversion layer.

[Effect of device]

As described above, the diodes of opposite polarities according to the present invention are further provided with one conductivity type region in another conductivity type region in one conductivity type semiconductor substrate, and two other conductivity type regions are formed therein. With this configuration, it can be formed in the semiconductor substrate and can normally receive an input voltage in a range wider than the power supply voltage, that is, a high voltage input from a level converter or the like.

Further, since the channel stopper is provided between the diodes connected to the opposite polarities, channel leak does not occur.

Also, the protection circuit according to the present invention can be used not only for the input terminal but also for the output terminal.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of an improved protection circuit, FIG. 2 is a reference diagram for explaining the basic structure of the present invention, and FIG. 3 is a sectional view of a protection circuit according to an embodiment of the present invention. FIG. 4 is an equivalent circuit diagram of a conventional protection circuit. 1 ... Input terminal, 2 ... Protection resistance, 3,4,5,6 ... Diode, 7 ... P-channel MOS transistor, 8 ... N-channel MOS transistor, 9 ... Power (+) terminal, 10 ...
… Power (–) terminal, 11 …… High-concentration N-type diffusion area, 12,13
…… High-concentration P-type diffusion region, 14,15 …… Low-concentration N-type diffusion region, 16,17,18 …… High-concentration P-type diffusion region, 19 …… Low-concentration P
Diffusion region, 20 …… Low-concentration N-type semiconductor substrate, 21,22 ……
High concentration N type diffusion region, 23 ... Insulating film.

Claims (1)

[Scope of utility model registration request] 1. A first region of opposite conductivity type formed in a semiconductor substrate of one conductivity type, and second and third regions of the same conductivity type formed in the first region so as to be spaced apart from each other. A region and a second region, which are formed to be separated from each other, and which respectively form a diode with the second region, and the fourth and fifth regions of the opposite conductivity type, which are separated from each other in the third region. Formed,
The sixth and seventh regions of the opposite conductivity type each forming a diode with the third region; and the fourth region and the fifth region formed in the second region. An eighth of one conductivity type having an impurity concentration higher than that of the second region
And a ninth region of one conductivity type having a higher impurity concentration than the third region formed between the sixth region and the seventh region in the third region. An element protection circuit device, wherein the input terminals of the MOS elements are connected to the fifth and sixth regions, the first power supply terminal is connected to the fourth region, and the seventh region is provided. A protection circuit device for a MOS element, to which a second power supply terminal is connected.