JPH02122497A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent a parasitic bipolar transistor (TR) by leading off a EPROM write power source from a second P channel TR source and a back gate. CONSTITUTION:At the time of writing the EPROM, a double use terminal 1 is made into a potential higher than that of a normal high potential side power source (VDD), first, a write voltage detecting circuit 2 executes a detecting operation at around VDD + 2.5V, and the inverse of P signal is set at an 'L' level. At such a time, since a first P channel enhancement TR 3 exists, a drain 13-3 of a second P channel enhancement TR 4 is not supplied with the voltage of the double use terminal until the TR 3 is turned on, and at such a time, since the TR 4 is turned on, the section of the emitter based o a parasitic PNP TR 21 is clamped at <= 0.1V, and charge is applied through a channel. Thus, the parasitic TR is not turned on, a TR 5 is turned off, and the over current can be prevented.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a complementary MIS integrated circuit that has a built-in EPROM and uses a write power supply terminal as another input or output terminal, and particularly, This relates to using the write power supply terminal as another input or output terminal.

[Conventional technology]

Conventionally, for this type of dual-use terminal, N
Power is supplied by switching the channel transistor 19 and turning it on during writing, or by using a diode 20 and a P-channel transistor 3 as shown in FIG. (For example, special public Sho 6l-1114
01) [Problems to be Solved by the Invention] Among the conventional terminal dual-purpose circuits described above, in the circuit shown in FIG. Therefore, a charge pump circuit was required to internally boost the gate voltage. In addition, since the circuit shown in FIG. 5 writes using the forward direction of the diode 20, a rise voltage of the diode and a voltage drop due to the series resistance occur, and in order to prevent a parasitic bipolar transistor, a diode is formed. has the disadvantage of requiring an additional step.

[Means to solve the problem]

In the terminal dual-purpose circuit of the present invention, an N-type well serving as a source and a back gate is connected to a first P-channel enhancement transistor connected to the dual-purpose terminal, and a drain is connected to the drain of the first P-channel transistor. A second P-channel enhancement transistor train is connected to an N-type well serving as the source and back gate of the second P-channel transistor, and the source is normally a high potential side power supply (hereinafter referred to as vol).
The first N-channel depletion transistor connected to the first N-channel depletion transistor and the dual-purpose terminal are input, detect the write voltage, and the first N-channel depletion transistor is connected to the first N-channel depletion transistor. It has a detection circuit that controls the gates of the second P-channel transistor and the first N-channel transistor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an embodiment of the present invention.
It is a structural sectional view of the part 3.4.5 in the figure. Dual-purpose terminal 1
is connected to the write voltage detection circuit 2 and the N-type well 11-1 which becomes the source 13-1 and back gate of the first P-channel enhancement transistor 3 via the N-type high concentration diffusion layer 12-1, and to the EPROM. The drain 13-2 of the transistor 3 is connected to the drain 13-3 of the second P-channel enhancement transistor 4, the source 13-4 of the transistor 4, and the input and output circuits. .

The N-type well 11-2 and the N-type high concentration diffusion layer 12-2, which serve as a gate, are connected to the drain 12-3 of the first N-channel depletion transistor 5.
Power is supplied to the block 8, the source of the transistor 5 is connected to VI)D, and the gates of the transistors 3 and 4.5 are set to "L" when the write voltage detection circuit 2 detects the voltage.
It is connected to the control signal F that becomes the level.

Next, the operation of this example will be explained.

During normal operation (not in EPROM writing state), the dual-purpose terminal is between the ground potential and V□, and in this case, the drain 13-2 of transistor 3 and the N-type well 1
1-1 and the diode formed by the drain 13-3 of the transistor 4 and the N-type well 11-2 are reverse biased, and there is no leakage current between the terminal 1 and vDn.

When writing to EPROM, dual-purpose terminal 1 is set to a higher potential than VDD, but first, the write voltage detection circuit
The detection operation is performed at about 2.5 V, and the signal becomes “L”.
" level. At this time, if transistor 3 is not present,
Drain 13-3 of transistor 4 and N-type well 11-
2, the shared terminal voltage is VDD ~ VDD + 2.5 V
becomes forward biased between the drain 13-3 and the emitter N
The parasitic PNP (PNP) transistor 21 having the type well 11-2 as the base and the P-type substrate 10 as the collector is turned on, and an excessive current is generated. In the present invention, since there is a transistor 3, the drain 13-3 of the transistor 4 is turned on only when the transistor 3 is turned on.
, the voltage of the dual-purpose terminal is supplied to the transistor 4.
Since both are on, the voltage between the emitter and base of the parasitic PNP transistor is clamped to 0.1 V or less, and the charge does not flow through the channel to turn on the parasitic transistor. Furthermore, the transistor 5 is also turned off, making it possible to prevent excessive current.

FIG. 3 is a circuit diagram of a second embodiment of the present invention, and FIG. 4 is a circuit diagram of a second embodiment of the present invention.
FIG. 3 is a cross-sectional view of the section 3.6.11 in FIG. 3;

The dual-purpose terminal 1 is used for the write voltage detection circuit 2. EPROM block9. It is connected to the anode 4 of the diode 3 and the N-type well 16 in which the diode 3 is formed. The cathode 5 of the diode 3 is connected to the N-type well 1 which becomes the back gate of the P-channel MIS type enhancement transistor 60.
7 and the source, and the gate 6 of the transistor 4 is connected to the
The control signal F from the write voltage detection circuit is a complementary type M configured by a P-channel enhancement transistor 19, an N-channel enhancement transistor 21, a P-channel enhancement transistor 20, and an N-channel enhancement transistor 22.
It is connected through two stages of IS logic inversion circuit, and the drain is
the drain of the N-channel depletion transistor 7;
And it is connected to the EPROM block. The drain of N-channel depletion transistor 8 is connected to the backgate of transistor 60.

The sources of the transistors 11 and 8 are connected to a normal high potential side power supply 7, and the gates are connected to a control signal F of a write voltage detection circuit.

The operation of this circuit will be explained.

When a write power supply voltage, for example 21V, is applied to the shared terminal l, this voltage is detected by the write voltage detection circuit, and the control signal becomes "L". In this state, transistor 11.8 is cut off and transistor 6 is turned on. At this time, the source and back gate of the transistor 6 are biased through the diode 3. At this time, the potential ■1° of the contact lO connected to the EPROM block changes v2 of the diode 3 to VF6,
Assuming that the series resistance of diode 3 is Rs, and the current is R6N, which is the on-resistance of the transistor, then V+o=21' (Vys+I o (Rx+Ro
Na)). Since R3 and RoNe can be determined by the area of the diode and the W/L ratio of the transistor 6,
It is easy to set ID=2 to 3mA and V+o=20V.

In a state other than the above, the control signal of the write voltage detection circuit becomes "H", the transistor 11.8 is turned on, and the transistor 6 is cut off.

At this time, the back gate of transistor 60 becomes the same potential as the normal high potential power supply through transistor 8,
The contact 10 also has the same potential as the normal high potential side power supply through the transistor 7. The cathode side of the diode 3 is at the same potential as the normal high-potential side power supply, so as long as the potential of the dual-purpose terminal l changes with the logic amplitude of the normal complementary logic circuit, the diode 3 It is reverse biased, and no current flows between the terminal 1 and the normal high potential power supply.

FIG. 5 is a circuit diagram of a third embodiment of the present invention. In contrast to the first embodiment described above, a delay circuit 17 is inserted between the gate signals of transistors 4.5 and 3.

In this embodiment, the delay circuit 17 causes the transistor 3 to
Since the turn-on timing of transistor 4 is delayed by several micrometers with respect to the turn-on timing of transistor 4, there is an advantage that the parasitic PNP transistor 21 shown in FIG. 2 is more difficult to turn on.

〔Effect of the invention〕

As explained above, the present invention prevents the parasitic bipolar transistor operation and extremely reduces the voltage drop in the supply voltage in order to supply the write voltage while the transistor 3.4 is on and the transistor 5 is off. Moreover, the process and area occupied can be reduced compared to the conventional example.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a structural sectional view of section 3.4.5 in FIG. 1, and FIG. 3 is a circuit diagram of a second embodiment of the present invention. Figure 4 is a partial cross-sectional view of the circuit in Figure 3;
FIG. 5 is a circuit diagram of a third embodiment of the present invention, and FIGS. 6 and 7 are circuit diagrams of conventional terminal dual-purpose circuits. l...Common terminal, 2...Write voltage detection circuit, 3.4...P channel enhancement transistor, 5...N channel depletion transistor, 7 ... Normal high potential side power supply (vt, n), 8 ... EPROM block,
10...P-type substrate, 11-1.11-2...
...N type well, 12-1.12-2.12-3.1
2-4...N-type high concentration diffusion layer, 13-1.13
-2.13-3.13-4...P-type high concentration diffusion layer, 14...Thermal oxide film, 15...Interlayer insulating film, 16... ...Metal electrode, 17...
Delay circuit, 18...Charge pump, 19...
...N-channel enhancement transistor,
20... Diode, 21... Parasitic P
NP) transistor, 22...polysilicon. Agent: Patent Attorney Shinmeiso Uchihara! Menkazuzu half-monkayaotsuzu diagram

Claims (2)

[Claims] (1) In a complementary MIS integrated circuit that incorporates an ultraviolet erasable EPROM and has a dual-purpose terminal that also serves as a write power supply terminal and another input or output terminal, the first
, has a second P-channel enhancement transistor, a first N-channel depletion transistor, and a write voltage detection circuit, and the N-type well serving as the source of the first P-channel enhancement transistor and its back gate is connected to a shared terminal. Connect and drain the
The N-type well is connected to the drain of the second P-channel enhancement transistor and serves as the source and back gate of the second P-channel enhancement transistor. The source of the channel depletion transistor is connected to a high-potential side power source other than the EPROM section of the integrated circuit, and the source of the channel depletion transistor is connected to the gates of the first and second P-channel enhancement transistors and the first N-channel enhancement transistor.
A complementary device characterized in that the gate of the channel depletion transistor is connected to a terminal of the write voltage detection circuit which becomes low level at the time of detection, and the power supply for writing to the EPROM is taken out from the source and back gate of the second P-channel transistor. Type MIS integrated circuit. (2) A delay circuit of several μsec is inserted between the gate of the first P-channel transistor and the gates of the second P-channel transistor and the first N-channel transistor, and A gate signal is applied to the second P-channel transistor and the first P-channel transistor.
The complementary MIS integrated circuit according to claim 1, wherein the signal is delayed from the gate signal of the P-channel transistor.