JPH01282858A - Semiconductor device - Google Patents

Abstract

PURPOSE:To equalize the temperature characteristic of the threshold voltage and reduce the changes of the current limitation value with temperature by using a transistor formed together with the base diffusion layer of a vertical MOS transistor in the same process and having a diffusion layer as a voltage limiting element between the gate and the source of the vertical MOS transistor. CONSTITUTION:A first transistor 1 includes a P type area 8 formed together with the P base diffusion layer 7 of a vertical MOS transistor in the same process and placed around a source 12. If the surface concentration of a P well diffusion layer 6 is made lower than that of the base diffusion layer 7 of the vertical MOS transistor, the threshold voltage of the first transistor 1 depends on the surface concentration of the area 8 formed together with the diffusion layer 7 in the same process to reduce the influence of the diffusion layer 6. This makes the threshold voltage of the first transistor 1 approximately the same as that of the vertical MOS transistor 3 and equalizes the temperature characteristics of the two with each other.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to the circuit configuration and element structure of a semiconductor integrated circuit, and particularly to the output of a semiconductor integrated circuit in which a vertical MOS transistor and a control circuit are formed on the same substrate. The present invention relates to a circuit configuration and an element structure of a current limiting circuit.

[Conventional technology]

In a semiconductor integrated circuit in which a vertical MOS transistor and a control circuit are formed on the same substrate, in order to limit the output current of the vertical MOS transistor, it is necessary to limit the gate-source voltage of the vertical MOS transistor. Conventional techniques include connecting a Zener diode 23 between the gate and source as shown in FIG. 7 and limiting the voltage between the gate and source using the Zener voltage, or as shown in FIG. There is a method in which several diodes are connected between the gate and the source, and the voltage between the gate and the source is limited by the forward voltage drop of the diode 25.
[Problems to be Solved by the Invention] In the conventional technology described above, the temperature characteristics of the threshold voltage of the vertical MOS transistor 3 and the temperature characteristics of the element that limits the gate-source voltage of the vertical MOS transistor 3 are Since the current limit value is different, there is a drawback that the current limit value varies greatly depending on the temperature. For example, in the circuit using the Zener diode 23 shown in FIG. 3, the temperature coefficient of the Zener voltage is small, the temperature coefficient of the threshold voltage of the vertical MOS transistor 3 is relatively large, and its polarity is negative, so the current The limiting value tends to increase with increasing temperature.

Furthermore, in the circuit using the forward voltage drop of the diode 25 shown in FIG. 4, the absolute value of the temperature coefficient of the diode 25 is larger than that of the vertical MOS transistor 3, and its polarity is negative, so the current limit value tends to decrease as temperature increases.

[Means for Solving the Problems] A semiconductor device of the present invention includes a vertical MOS transistor and a first transistor whose threshold voltage temperature characteristics are equal to those of the vertical MOS transistor.

The first transistor has a diffusion layer formed on its source side in the same process as the base diffusion layer forming process of the vertical MO8 in order to make the temperature characteristics of the threshold voltage equal to those of the vertical MOS transistor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. FIG. 2 is a sectional view of one embodiment of the present invention. first transistor 1
is a vertical MOS transistor P around the source 12.
It has a P-type head region 8 formed in the same process as the base diffusion layer 7. If the surface concentration of the P-well diffusion layer 6 is set lower than that of the P-base 7 diffusion layer of the vertical MOS transistor,
The threshold voltage of the first transistor is the P base diffusion layer 7
The influence of the P well diffusion layer 6 is determined by the thickness of the surface of the P group region 80 formed in the same process as that of the P well diffusion layer 6.

As a result, the threshold voltage of transistor 1 in tube 1 is vertical type M
It becomes almost equal to the threshold voltage of OS transistor 3,
Moreover, the temperature characteristics of both become equal.

Therefore, the temperature dependence of the current limit value, which has been a problem with the conventional technology, can be reduced.

Next, the operation of the current limiting circuit will be explained with reference to FIG.

In the semiconductor device of this embodiment, since the source terminal of the vertical MOS transistor 3 is used as an output terminal, a booster circuit 33 is used to raise the potential of the gate 34 of the vertical MOS transistor 3 above the potential of the VDD terminal 30. By doing this, the on-resistance of the vertical MOS transistor 30 becomes sufficiently low, and O
The potential of the UT terminal 35 rises to near the potential of the V terminal 30, and a sufficient current can be supplied to the load 36. At this time, the gate potential of the second transistor 2 is VD
Since the potential of the D terminal 30 is fixed and the second transistor is off, the potential of the gate 34 of the vertical MOS transistor 3 has increased to the maximum output voltage of the booster circuit 33.

When the OUT terminal is shorted to the ground (GND) 32, the second transistor 2 is turned on, and the charge accumulated in the gate 34 of the vertical MOS transistor 3 passes through the second transistor 2 and the first transistor 1 to the OUT terminal. 35, the potential of the gate 34 of the vertical MOS transistor 3 decreases, and the output current of the vertical MOS transistor 3 is limited.

The potential of the gate 34 of the vertical MOS transistor 3 is determined by the current from the booster circuit 33, the on-resistance of the second transistor 2, and the threshold voltage of the first transistor 1. Therefore, the first transistor 1 and the second transistor 2
By adjusting the dimensions of the vertical MoS transistor 3
The current limit value can be set.

Figure 4 shows the temperature characteristics of the current limit value. These are the results of simulations performed using a circuit simulator on the conventional circuit shown in FIG. 8 and the circuit of the present embodiment shown in FIG. 1. The dimensions of the vertical MOS transistor 30 are the same, 12V is supplied to the drain and gate terminals, and the OUT
The output current when the terminal was shorted to GND was plotted against temperature. In the conventional circuit (solid line), the current limit value of 5A at room temperature shows a change of ±43% with respect to a temperature change of ±75°C, whereas in the circuit of this embodiment (dotted line), the current limit value of 5A changes by ±43% with respect to a temperature change of ±75°C.
It is held down to 28%.

FIG. 5 is a sectional view of another embodiment of the invention.

FIG. 6 is a circuit diagram of another embodiment of the present invention. In this embodiment, a first transistor 1 and a second transistor 20
The back gates are commonly connected.

In this embodiment, since the P-well diffusion layer 6 forming the first transistor 1 and the second transistor 2 can be shared, the area of the current limiting circuit can be reduced.

〔Effect of the invention〕

As explained above, the present invention uses a horizontal MOS transistor whose threshold voltage temperature characteristic is equal to that of the vertical MOS transistor as a gate-source voltage limiting element of the vertical MOS transistor, thereby increasing the current limit value. This has the effect of minimizing changes in temperature.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a sectional view of an embodiment of the invention, Fig. 3 is an explanatory diagram of the operation of the current limiting circuit of the invention, and Fig. 4 is a conventional technique. FIG. 5 is a cross-sectional view of another embodiment of the present invention. Fig. 6 is a circuit diagram of another embodiment of the present invention, Fig. 7 is a circuit diagram of a conventional current limiting circuit using a Zener diode, and Fig. 8 is a conventional current limiting circuit using a forward voltage drop of a diode. FIG. DESCRIPTION OF SYMBOLS 1...First transistor, 2...Second transistor, 3...Vertical MOS transistor, 4...N+ substrate, 5... ...N-shrimp layer, 6...P well diffusion layer, 7...
P-base diffusion layer, 8... P-type region formed in the same process as the P-base diffusion layer, 9... Source of vertical MOS transistor, 10. Old... Vertical MOS transistor P+ region for fixing back gate potential, 11...
・P+ for fixing the back gate potential of the first transistor
Region, 12... Source of the first transistor,
13... Drain of first transistor, 14
... P+ region for fixing back gate potential of second transistor, 15 ... Source of second transistor, 16 ... Drain of second transistor, 17 ... ...Gate of vertical MOS transistor, 18 ...Gate of first transistor, 19
...Gate of second transistor, 20...
...field)' acid (tJ, 21...aluminum wiring, 22...drain of first transistor and source of second transistor, 23...
Zener diode for limiting gate-source voltage, 24
... Current limit value adjustment transistor, 25...
... Gate-source voltage limiting diode, 30
...VD, ) terminal, 31...Input terminal, 32...GND, 33...Boost circuit, 34...Vertical MOS transistor gate,
35...OUT, 36...Load. Agent Patent Attorney Uchihara Otodai 3rd Country GND Figure 4 Man 5 Figure

Claims (1)

[Claims] In a semiconductor device in which a vertical MOS transistor and a current limiting circuit are configured on the same substrate, the vertical MOS transistor has its source terminal as an output terminal, and the current limiting circuit has a first transistor and a second transistor. a drain terminal and a gate terminal of the first transistor are connected to a source terminal of the second transistor, a source terminal of the first transistor is connected to the source terminal of the vertical MOS transistor, The drain terminal of the second transistor is connected to the vertical MOS
a gate terminal of the second transistor; a gate terminal of the second transistor is connected to a drain terminal of the vertical MOS transistor; and the first transistor:
A semiconductor device characterized in that it has a diffusion layer formed on its source side in the same process as the base diffusion layer forming process of the vertical MOS transistor.