JPH03235368A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03235368A JPH03235368A JP2030905A JP3090590A JPH03235368A JP H03235368 A JPH03235368 A JP H03235368A JP 2030905 A JP2030905 A JP 2030905A JP 3090590 A JP3090590 A JP 3090590A JP H03235368 A JPH03235368 A JP H03235368A
- Authority
- JP
- Japan
- Prior art keywords
- fet
- gate
- film
- films
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims description 7
- 239000002344 surface layer Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 13
- 229920005591 polysilicon Polymers 0.000 abstract description 13
- 230000000630 rising effect Effects 0.000 abstract description 5
- 210000004027 cell Anatomy 0.000 description 12
- 239000010410 layer Substances 0.000 description 8
- 230000007257 malfunction Effects 0.000 description 7
- 210000001744 T-lymphocyte Anatomy 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000470 constituent Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
「発明の目的」
（産業上の利用分野）
本発明は、電力用ＭＯ３型電界効果トランジスタ（ＭＯ
Ｓ ＦＥＴと略記）や絶縁ゲート型バイポーラトラン
ジスタ（ＩＧＢＴと略記）等で構成された半導体装置に
関するもので、特に複数のＭＯＳ ＦＥＴ構体をモノ
リシックに搭載し、各ゲート配線膜か異なる抵抗値を有
する半導体装置に係るものである。Detailed Description of the Invention "Object of the Invention" (Industrial Field of Application) The present invention provides an MO3 type field effect transistor for power
It relates to semiconductor devices composed of S FET (abbreviated as S FET) and insulated gate bipolar transistors (abbreviated as IGBT), etc., and is particularly related to semiconductor devices that are monolithically mounted with multiple MOS FET structures and each gate wiring film has a different resistance value. It is related to the device.
（従来の技術）
複数のＭＯＳ ＦＥＴ等で構成された半導体装置の一
例として、−膜内なソース多出力電力用ＭＯ６ＦＥＴを
取り上げ、従来技術について説明する。 第６図に示す
半導体装置１旦は、１つの半導体基板に２つのＮチャネ
ル二重拡散縦型ＭＯ３ＦＥＴ（ＤＶ ＭＯＳ ＦＥ
Ｔ、本明細書では絶縁ゲート型トランジスタ構体とも呼
ぶ）Ａ及びＢを搭載し、共通のドレイン端子り及びゲー
ト端子Ｇと、２つのソース端子ＳＡ及びＳＢを有するい
わゆるソース多出力電力用ＭＯ３ＦＥＴＬ旦で、同図（
ａ ）はその平面概略図、同図（ｂ）は模式的なＸ−Ｘ
−線（同図（ａ ）参照）断面図、又同図（Ｃ）は、Ｆ
ＥＴ−Ａ又はＦＢＴ−Ｂを構成する単位ＦＥＴユニット
（セルと呼ぶ）１５の配置を模式的に示す部分平面図で
ある。 第６図（ａ ）において、符号上は半導体基板
、２はゲートボンディングパッド、３ａ及び３ｂはそれ
ぞれＦＥＴ−Ａ及びＦＥＴ−Ｂのゲート電極引き出し用
のゲート配線膜、４ａ及び４ｂはポリシリコンゲート電
極膜、５ａ及び５ｂはＦＥＴセル配置領域及びソース電
ｆ！膜を示す、 同図（ｂ）において、半導体基板１は
、ドレイン低抵抗領域（Ｎ”ドレイン領域）ｌａと、ド
レイン高抵抗領域（Ｎドレイン領域）ｌｂとから成る。(Prior Art) As an example of a semiconductor device constituted by a plurality of MOS FETs, etc., an in-film source multi-output power MO6FET will be taken up and the prior art will be described. The semiconductor device shown in FIG. 6 consists of two N-channel double-diffused vertical MO3FETs (DV MOS FE
A so-called MO3FETL for source multi-output power is equipped with transistors A and B (also referred to as an insulated gate transistor structure in this specification) and has a common drain terminal and gate terminal G, and two source terminals SA and SB. , the same figure (
a) is a schematic plan view, and (b) is a schematic diagram of
- line (see figure (a)) sectional view, and figure (c) is F
FIG. 2 is a partial plan view schematically showing the arrangement of unit FET units (referred to as cells) 15 constituting ET-A or FBT-B. In FIG. 6(a), the reference symbol is a semiconductor substrate, 2 is a gate bonding pad, 3a and 3b are gate wiring films for leading out the gate electrodes of FET-A and FET-B, respectively, and 4a and 4b are polysilicon gate electrodes. The films 5a and 5b are the FET cell arrangement area and the source voltage f! In FIG. 1B, which shows the film, the semiconductor substrate 1 consists of a low drain resistance region (N" drain region) la and a high drain resistance region (N" drain region) lb.
６はＮドレイン領域ｌｂ内に島状に形成されるＰベ
ース領域、７はＰベース領域６内に形成される環状のＮ
′″ソース領域、８はゲート酸化膜、９は眉間絶縁膜、
１１はカードリングの役割等を持つＰ領域である。6 is a P base region formed in an island shape within the N drain region lb, and 7 is an annular N base region formed within the P base region 6.
'''source region, 8 is a gate oxide film, 9 is a glabella insulating film,
Reference numeral 11 denotes a P area having the role of a card ring, etc.
ＦＥＴ−Ａ及びＦＥＴ−Ｂは、同図（Ｃ）に示すように
、複数のセル１５（１点鎖線で囲まれた部分）より構成
される。 同図（Ｃ）において、範囲ｌ、は、基板上の
主表面の露出平面図、範囲１２は、ゲート電極膜４ａを
露出したときの平面図、範囲ｉ３は、ソース電極ＷＡ５
ａを露出したときの平面図である。 なおゲート酸化膜
、眉間絶縁膜等は図示を省略する。The FET-A and the FET-B are each composed of a plurality of cells 15 (the portion surrounded by a dashed line), as shown in FIG. In the same figure (C), range l is an exposed plan view of the main surface on the substrate, range 12 is a plan view when the gate electrode film 4a is exposed, and range i3 is the source electrode WA5.
It is a top view when a is exposed. Note that the gate oxide film, glabellar insulating film, etc. are omitted from illustration.
一般に従来のソース多出力電力用ＭＯ３ＦＥＴｌ０では
、各ゲート配ｍ膜の抵抗は等しい値となっている。 こ
のような装置（デバイス）を、一端か接地された負荷の
ハイサイドスイッチとして使用する回路例を第７図に示
す。 即ちＰＥＴ−Ｂは、一端接地の負荷１６に電力を
出力するスイッチ素子とし、ＦＥＴ−Ａは電流検出用と
して用いる６ ＦＥＴ−Ａのソース端子ＳＡに接続され
る抵抗Ｒ１の値は、ＦＥＴ−Ａのオン抵抗より充分大き
な値に設定しておく。 この回路では、ゲート端子Ｇに
ゲート電圧■６が印加されていない場合、ＦＥＴ−Ａ及
びＦＥＴ−Ｂはオフ状態で、従って端子ＳＡ及びＳ、間
には電圧か発生しない。Generally, in the conventional source multi-output power MO3FET10, the resistance of each gate interconnection film is the same value. FIG. 7 shows an example of a circuit in which such a device is used as a high-side switch with one end of the load connected to ground. That is, PET-B is a switching element that outputs power to a load 16 whose one end is grounded, and FET-A is used for current detection.6 The value of resistor R1 connected to the source terminal SA of FET-A is Set it to a value that is sufficiently larger than the on-resistance of . In this circuit, when gate voltage 6 is not applied to gate terminal G, FET-A and FET-B are in an off state, and therefore no voltage is generated between terminals SA and S.
ゲート電圧■６が印加され、ＦＥＴ−Ａ及びＦＥＴ−Ｂ
がオンした場合、ＰＥＴ−Ａの端子ＳＡの電位（アース
を基準電位）はドレイン電位Ｖ。にほぼ等しくなるので
、端子ＳＡとＳＢとの間には、ＦＥＴ−Ｂのドレイン・
ソース間電圧■。５が発生する。 従って端子ＳＡ、３
Ｆ３間の電圧を使用して、ＦＥＴ−Ｂの保護回路（例え
はオン状態のとき出力用ＦＥＴ−８のドレイン・ソース
間電圧がある一定値を超えたらゲート電圧ＶＧをオフす
る等）を構成できる。Gate voltage ■6 is applied, FET-A and FET-B
When turned on, the potential of the terminal SA of PET-A (with the ground as reference potential) is the drain potential V. Therefore, there is a drain terminal of FET-B between terminals SA and SB.
Source-to-source voltage ■. 5 occurs. Therefore, terminal SA, 3
Using the voltage between F3, configure the protection circuit for FET-B (for example, turn off the gate voltage VG if the drain-source voltage of output FET-8 exceeds a certain value when it is in the on state) can.
このように、ソース多出力電力用ＭＯ８ＦＥＴを用いる
場合、製造工程のバラツキによる該ＦＥＴの特性の差異
により誤動作を招く可能性かある。 −例として、ＦＥ
Ｔ−Ａのしきい値電圧がＦＥＴ−８のしきい値電圧より
も低い場合を考える。 このとき、ゲート電圧ＶＧの立
ち上かり時に、ＦＥＴ−ＡがＦＥＴ−Ｂより先にオンし
、端子ＳＡ、Ｓｓ間に、−時的に大きな電圧が発生し、
前記保護回路が誤動作をする可能性がある。As described above, when using a source multi-output power MO8FET, there is a possibility that malfunctions may occur due to differences in the characteristics of the FET due to variations in the manufacturing process. - As an example, FE
Consider the case where the threshold voltage of TA is lower than the threshold voltage of FET-8. At this time, when the gate voltage VG rises, FET-A turns on before FET-B, and a temporally large voltage is generated between terminals SA and Ss.
There is a possibility that the protection circuit malfunctions.
（発明が解決しようとする課題）
従来のソース多出力電力用ＭＯ３ＦＥＴを使用する場合
、例えば第７図の回路例で述べたように、デバイスを構
成する複数のＦＥＴのしきい値電圧等の特性は、製造工
程のバラツキにより必すしも同一ではない。 従って同
じゲート電圧を印加してもソース出力端子の電圧の立ち
上がりにバラツキか発生し、不測の誤動作を招く可能性
があり、応用上の課題となっている。(Problems to be Solved by the Invention) When using a conventional source multi-output power MO3FET, for example, as described in the circuit example in FIG. are not necessarily the same due to variations in the manufacturing process. Therefore, even if the same gate voltage is applied, variations occur in the rise of the voltage at the source output terminal, which may lead to unexpected malfunctions, which is a problem in application.
他方、ソース多出力電力用ＭＯ８ＦＥＴ等の応用分野の
拡大に伴い、構成する複数のＦＥＴのそれぞれのゲート
電極電圧の立ち上がり特性を制御し、各ＦＥＴのスイッ
チング特性を変えたいという市場のニーズは大きい。On the other hand, with the expansion of application fields such as source multi-output power MO8FETs, there is a great need in the market to control the rise characteristics of the gate electrode voltages of each of the plurality of FETs to change the switching characteristics of each FET.
本発明の目的は、ソース多出力電力用ＭＯ８ＦＥＴ等に
おいて、構成する複数のＦＥＴのそれぞれのゲートを極
電圧の立ち上がり特性を制御することができ、それによ
りソース多出力電力用ＭＯ３ＦＥＴ等の応用範囲を著し
く拡大させることか可能な半導体装置を提供することで
ある。An object of the present invention is to be able to control the rise characteristics of the polar voltage of each gate of a plurality of FETs in a MO8FET for source multi-output power, thereby expanding the scope of application of MO3FET for source multi-output power, etc. It is an object of the present invention to provide a semiconductor device that can be expanded significantly.
「発明の構成」
（課題を解決するための手段）
本発明の半導体装置は、（ａ ）ドレイン領域と、ベー
ス領域と、ソース領域と、ドレイン、ソース両領域に挟
まれるベース領域の表面層上に絶縁体膜を介して積層さ
れるゲート電極膜と、ゲート電極膜に接続するゲート配
線膜と、ソース電極膜とを有する複数の絶縁ゲート型ト
ランジスタ構体と、（ｂ ）前記ゲート配線膜の複数と
接続するゲート引き出し用ボンディングパッドとを具備
し、且つ複数の前記ゲート配線膜の電気抵抗が異なるこ
とを特徴とするものである。"Structure of the Invention" (Means for Solving the Problems) A semiconductor device of the present invention includes (a) a drain region, a base region, a source region, and a surface layer of the base region sandwiched between both the drain and source regions. (b) a plurality of insulated gate type transistor structures having a gate electrode film stacked on top of each other via an insulating film, a gate wiring film connected to the gate electrode film, and a source electrode film; (b) a plurality of the gate wiring films; and a gate lead-out bonding pad connected to the gate wiring film, and the plurality of gate wiring films have different electrical resistances.
通常前記絶縁ゲート型トランジスタ構体は、多数のＦＥ
Ｔセルから成り、ＭＯＳ ＦＥＴ又はＩＧＢＴ等を形
成する。 本発明の半導体装置は、上記絶縁ゲート型ト
ランジスタ構体を１つの半導体基板に複数個搭載し、共
通のゲートホンティングパッドを有し、複数の異なるソ
ース＠’＃ｌを有するものである。Typically, the insulated gate transistor structure includes a large number of FEs.
It consists of T cells and forms MOS FETs, IGBTs, etc. A semiconductor device of the present invention has a plurality of the above insulated gate transistor structures mounted on one semiconductor substrate, has a common gate font pad, and has a plurality of different sources @'#l.
（作用）
本発明の半導体装置を構成する上記複数の絶縁ゲート型
トランジスタ構体は、それぞれにゲート配線膜を持って
いるので、これらゲート配線膜の抵抗値を変化させるこ
とにより、各トランジスタ構体のゲート電極膜の電圧立
ち上かり特性をそれぞれ所望特性とすることができる。(Function) Since each of the plurality of insulated gate type transistor structures constituting the semiconductor device of the present invention has a gate wiring film, the gate wiring film of each transistor structure can be changed by changing the resistance value of these gate wiring films. The voltage rise characteristics of the electrode films can be set to desired characteristics.
これにより例えば第７図の使用回路例において、ＦＥ
Ｔ−Ａのゲート電極膜の電圧の立ち上がりを、ＦＥＴＢ
の立ち上がりより遅らせて前記回路の誤動作を防止でき
るし、又各トランジスタ構体のスイッチング特性を容易
に異なる特性とすることかできる。As a result, for example, in the circuit example shown in Fig. 7, the FE
The voltage rise of the gate electrode film of T-A is
It is possible to prevent malfunction of the circuit by delaying the rise of the voltage, and it is also possible to easily make the switching characteristics of each transistor structure different.
（実施例）
本発明を、ポリシリコンゲート電極膜から成るソース多
出力ＤＶ ＭＯＳ ＦＥＴに適用した第１の実施例
について図面を参照して以下説明する。(Example) A first example in which the present invention is applied to a source multi-output DV MOS FET made of a polysilicon gate electrode film will be described below with reference to the drawings.
第１図（ａ ）はこのＤＶ ＭＯＳ ＦＥＴ５０の
平面概略図、同図（ｂ）は模式的なｘ−ｘ′線断面図で
ある。 本発明のＤＶ ＭＯＳ ＦＥＴ１旦は、デ
バイスを構成する複数のＭＯＳ ＦＥＴ構体５０ａ及
び５０ｂのそれぞれのゲート配線ｌＩ！１３ａ及び１３
ｂの抵抗値が互いに異なっていることが、従来の第６図
に示すＤＶ ＭＯＳ ＦＢＴ上ユと相異し、その他
の構成はほぼ等しい。FIG. 1(a) is a schematic plan view of this DV MOS FET 50, and FIG. 1(b) is a schematic cross-sectional view taken along line xx'. First, the DV MOS FET of the present invention is connected to each gate wiring lI! of each of the plurality of MOS FET structures 50a and 50b constituting the device. 13a and 13
This differs from the conventional DV MOS FBT upper unit shown in FIG. 6 in that the resistance values of b are different from each other, but the other configurations are almost the same.
従って第１図において、第６図と同符号は、同じ部分を
表わすので、説明を省略する。 又前記ＭＯ３ＦＢＴ構
体の要素であるＦＥＴセルの配置は、第６図（Ｃ）と等
しいので、記載を省略する。Therefore, in FIG. 1, the same reference numerals as in FIG. 6 represent the same parts, and the explanation will be omitted. Furthermore, the arrangement of the FET cells, which are the elements of the MO3FBT structure, is the same as that in FIG. 6(C), so the description thereof will be omitted.
第１図においてゲート配線膜１３ａ及び１３ｂは、それ
ぞれポリシリコンゲート電極膜４ａ及び４ｂの延在部分
で、ポリシリコンから成り、ＡＩ等から成るゲート引き
出し用ボンデイングパ・ンド１２に接続される。 この
実施例では、ＦＥＴ−Ａのゲート配線１１！１３ａの幅
が、ＰＥＴ−Ｂのゲート配線膜１３ｂの幅より狭くなる
ように形成される。 なお特許請求の範囲第１項記載の
絶縁ゲート型トランジスタ構体は、本実施例ではＭＯ３
ＦＥＴＯ３ＦＥＴ反体５０ａであって、例えばＭＯＳ
ＦＥＴ構体５０ａは、Ｎ’ソース領域７、Ｐベース領
域６、Ｎドレイン領域１ａ、ｌｂ、ゲート酸化膜８、ゲ
ート電極！４ａから成る多数のＦＥＴセル並びにこれら
のセルのソース領域にオーミック接触するソース電極膜
５ａ及びゲート配線１１！！！１３ａにより構成される
。 第１図＜ｂ ＞の−点鎖線Ｙ−Ｙ′はゲート電極１
ｌ１４ａとゲート配線膜１３ａとの境界面の概略の位！
を示す。 又Ｙ−Ｙ′線の右側（図面上）の領域はＦＥ
Ｔセルの配置領域である。In FIG. 1, gate wiring films 13a and 13b are extensions of polysilicon gate electrode films 4a and 4b, respectively, and are made of polysilicon and are connected to a gate lead-out bonding pad 12 made of AI or the like. In this embodiment, the width of the gate wiring film 11!13a of FET-A is formed to be narrower than the width of the gate wiring film 13b of PET-B. Note that the insulated gate type transistor structure described in claim 1 is composed of MO3 in this embodiment.
FETO3FET anti-body 50a, for example MOS
The FET structure 50a includes an N' source region 7, a P base region 6, an N drain region 1a, lb, a gate oxide film 8, a gate electrode! 4a, and a source electrode film 5a and gate wiring 11 that are in ohmic contact with the source regions of these cells. ! ! 13a. The -dotted chain line Y-Y' in Fig. 1<b> is the gate electrode 1.
The approximate location of the interface between l14a and gate wiring film 13a!
shows. Also, the area to the right of the Y-Y' line (on the drawing) is FE.
This is the arrangement area for T cells.
このＭＯＳ ＦＥＴ５０を第７図に示す回路例に使用
すると、従来技術の問題点として述べた誤動作はなくな
る。 この点について以下更に詳細に説明する。When this MOS FET 50 is used in the circuit example shown in FIG. 7, the malfunction mentioned as a problem of the prior art will be eliminated. This point will be explained in more detail below.
即ちゲート配線膜の幅を変えたので、ゲート配線膜１３
ａの抵抗ＲＧＡとゲート配線［１３ｂの抵抗ＲＧ６とは
その値が互いに異なる。 従って第７図の回路は、第２
図＜ａ ＞に示すように、ＦＥＴ−Ａ及びＦＥＴ−Ｂの
各ゲート電極膜４ａ及び４ｂに、互いに異なる値の抵抗
ＲＧＡ及びＲＧ６を直列に付加した回路と等価となる。That is, since the width of the gate wiring film was changed, the gate wiring film 13
The resistance RGA of the gate line a and the resistance RG6 of the gate line [13b] have different values. Therefore, the circuit of FIG.
As shown in Figure <a>, this is equivalent to a circuit in which resistors RGA and RG6 of different values are added in series to the respective gate electrode films 4a and 4b of FET-A and FET-B.
ゲート端子Ｇと接地端子ＧＮＤ間に同図（ｂ ）に示す
波形の直流電圧■Ｇ１を印加すると、ＦＥＴ−Ａ及びＢ
のゲート電極膜の電圧ｖＧＡ及びＶＧａは、同図（Ｃ）
に示す波形で立ち上がり、一定電圧（近似的にＶＧｌに
等しい）に達する。 なお同図（ｂ ）の縦軸はＶＧ、
同図（ｃ ）の縦軸はＶＧＡ及びＶｇＢを示し、横軸は
両図とも時間ｔを表わし、【、はＶＧの印加時刻を示す
。When a DC voltage G1 with the waveform shown in the same figure (b) is applied between the gate terminal G and the ground terminal GND, FET-A and B
The voltages vGA and VGa of the gate electrode film are as shown in the same figure (C).
It rises with the waveform shown in and reaches a constant voltage (approximately equal to VGl). In addition, the vertical axis of the same figure (b) is VG,
The vertical axis in FIG. 2(c) represents VGA and VgB, the horizontal axis represents time t in both figures, and [, represents the time of application of VG.
即ちゲート直列抵抗ＲＧＡ及びＲ６８の存在により、外
部からのゲート入力信号電圧Ｖ。に対して、ゲート電極
膜４ａ及び４ｂに加わる電圧■。４及びＶＧ８は時間的
に遅れる。 ス本実施例では、ＦＥＴ−Ａ及びＢのＦＥ
Ｔセル数は互いに等しく、且つＲＧＡ ＞ ＲＧ［！で
あるがら、同図（Ｃ）に示すように電圧Ｖ０゜の立ち上
がり波形ａは、電圧ＶＧ日の立ち上がり波形すに比較し
て遅い。 そのなめ、ＦＥＴ−Ａ及びＦＥＴ−Ｂに、製
造工程上のバラツキ程度のしきい値電圧のずれがあって
も、ＦＥＴＡのオンをＦＥＴ−８よりも確実に遅らせる
こと、が可能となり、誤動作がなくなる。That is, due to the presence of the gate series resistors RGA and R68, the gate input signal voltage V from the outside. In contrast, the voltage ■ applied to the gate electrode films 4a and 4b. 4 and VG8 are delayed in time. In this example, the FE of FET-A and B is
The numbers of T cells are equal to each other, and RGA > RG[! However, as shown in FIG. 5C, the rising waveform a of the voltage V0° is slower than the rising waveform a of the voltage VG. Therefore, even if there is a difference in threshold voltage between FET-A and FET-B due to manufacturing process variations, it is possible to reliably delay the turn-on of FETA compared to FET-8, thereby preventing malfunction. It disappears.
第３図は、本ｎ明（７）ＤＶ ＭＯＳ ＦＥＴＶ）
第２の実施例を示す平面概略図である。 前記第１図に
示す例は、ＦＥＴ−Ａ及びＦＥＴ−Ｂを構成するＦＥＴ
セル数が互いに等しい場合であった。Figure 3 shows the present invention (7) DV MOS FETV)
FIG. 7 is a schematic plan view showing a second embodiment. The example shown in FIG.
This was a case where the number of cells was equal to each other.
この第２実施例は、ＦＥＴ−Ａ及びＢを構成するセル数
が互いに興なる場合のＤＶ ＭＯＳ ＦＥＴ１旦の
例である。ＦＥＴ−Ａ及びＦＥＴ−８を構成するセル数
をそれぞれＮ４個及びＮ６個（Ｎａ ＞ＮＡ）とし、又
ゲート配線膜２３ａ及び２３ｂの抵抗をそれぞれＲＧＡ
及びＲＧＢとする。This second embodiment is an example of a DV MOS FET in which the numbers of cells constituting FET-A and FET-B are different from each other. The numbers of cells constituting FET-A and FET-8 are respectively N4 and N6 (Na > NA), and the resistances of gate wiring films 23a and 23b are RGA, respectively.
and RGB.
この場合、ＲＧＡ及びＲＧ８はＲＧＡ Ｎ Ａ＞ Ｒｃ
ａ Ｎ ａ ）ニーなるよう設計されている。 この関
係式は、ゲート電極膜の電圧立ち上がり特性に関係する
ＦＥＴＡ又はＢのゲート・ソース間等価静電容量ｃＡ又
は０日は、近似的にそれぞれのセル数ＮＡ又はＮ６に比
例すると考えられるからである。In this case, RGA and RG8 are RGA NA> Rc
a N a ) It is designed to be a knee. This relational expression is based on the fact that the gate-source equivalent capacitance cA or 0 days of FETA or B, which is related to the voltage rise characteristics of the gate electrode film, is considered to be approximately proportional to the number of cells NA or N6 of each. be.
このような構造を持った２つのＦＥＴでのスイッチング
特性は、ＦＥＴ−Ａの方が、ＦＥＴ−Ｂよりも遅くなっ
ており、第７図の回路での誤動作はなくなる。 なお第
３図において、符号２２はゲートボンデインクパッド、
２４ａ及び２４ｂはそれぞれＦＥＴ−Ａ及びＢのポリシ
リコンゲート電極膜、２５ａ及び２５ｂはセル配置領域
及びソース電極膜を示す。Regarding the switching characteristics of the two FETs having such a structure, FET-A is slower than FET-B, and the malfunction in the circuit shown in FIG. 7 is eliminated. In FIG. 3, reference numeral 22 indicates a gate bonding ink pad;
24a and 24b are polysilicon gate electrode films of FET-A and B, respectively, and 25a and 25b are cell arrangement regions and source electrode films.
ゲート配線膜の抵抗値は、第１実施例においてはその幅
を、又第２実施例においてはその幅と長さとを変えて所
望抵抗値を得ているが、その他厚さ、及びポリシリコン
配線膜の不純物添加量等を変えることにより抵抗値を制
御することができる。The resistance value of the gate wiring film is obtained by changing its width in the first embodiment, and by changing its width and length in the second embodiment, but other factors such as thickness and polysilicon wiring The resistance value can be controlled by changing the amount of impurities added to the film.
′第４図は上記ゲート配線膜の抵抗値制御の実施例を示
す部分断面図である。 同図（ａ ）の左端及び右端、
同図（ｂ）及び（Ｃ）の右端の一点鎖線Ｙ−Ｙ’は、セ
ル配置領域のゲート電極膜とゲート配線膜との境界の概
略位置を示すものである。'FIG. 4 is a partial cross-sectional view showing an example of controlling the resistance value of the gate wiring film. The left and right ends of the figure (a),
A dashed-dotted line Y-Y' at the right end of FIGS. 3B and 3C indicates the approximate position of the boundary between the gate electrode film and the gate wiring film in the cell arrangement region.
同図（ａ ）は、ＦＥＴ−Ａのゲート配線膜３３ａの長
さをＦＥＴ−Ｂのゲート配線ｌｌ３３ｂの長さより長く
して抵抗値を大きくした例である。 同図（ｂ）はゲー
ト配線膜４３ａの長さを長くし且つその一部の厚さを薄
くして、その抵抗値を制御する例である。 ス同図（Ｃ
）は酸化Ｍ８に段差を形成し、この段差膜を下地として
、ゲート配線膜５３ａを被着したもので、そのポリシリ
コン配線長を実質的に長くした例である。FIG. 3A shows an example in which the length of the gate wiring film 33a of FET-A is made longer than the length of gate wiring 113b of FET-B to increase the resistance value. FIG. 2B shows an example in which the resistance value of the gate wiring film 43a is controlled by increasing the length of the gate wiring film 43a and decreasing the thickness of a portion thereof. Same figure (C
) is an example in which a step is formed in oxide M8, and a gate wiring film 53a is deposited using this step film as a base, and the length of the polysilicon wiring is substantially increased.
又抵抗体を介してゲート配線を行ない、その抵抗値を制
御することもできる。 第５図はその一例を示す部分断
面図である。 ９層１１に不純物をドープして、Ｎ型拡
散抵抗層６１を形成する。Alternatively, the resistance value can be controlled by wiring the gate through a resistor. FIG. 5 is a partial sectional view showing one example. The nine layers 11 are doped with impurities to form an N-type diffused resistance layer 61.
符号６３ａはポリシリコン膜から成るゲート配線膜で、
６０は拡散抵抗層６１とポリシリコンゲート配ＲＨ６３
ａとを接続する金属配線である。Reference numeral 63a is a gate wiring film made of a polysilicon film;
60 is a diffused resistance layer 61 and a polysilicon gate interconnection RH 63
This is a metal wiring that connects a.
ゲート配線膜の抵抗値は拡散抵抗層６１とポリシリコン
ゲート配線膜６３ａのそれぞれの抵抗値の和となる。
この場合には、Ｎ型拡散抵抗層６１と９層１１との間に
接合容量が形成され、ゲート電極膜の電圧立ち上がりに
はこの接合容量の効果が加わり、ポリシリコン等のみで
形成した場合と比較し、ゲート配線膜の抵抗値が同一で
あっても、電圧立ち上がり時間（スイッチング暗部）を
更に遅らせることが可能である。The resistance value of the gate wiring film is the sum of the respective resistance values of the diffused resistance layer 61 and the polysilicon gate wiring film 63a.
In this case, a junction capacitance is formed between the N-type diffused resistance layer 61 and the 9-layer 11, and the effect of this junction capacitance is added to the voltage rise of the gate electrode film, which is different from the case where it is formed only of polysilicon or the like. In comparison, even if the resistance value of the gate wiring film is the same, it is possible to further delay the voltage rise time (switching dark part).
上記実施例では、すべてＮチャネルＤＶ ＭＯＳ
ＦＥＴについてのみ述べたが、構成半導体層の導電型を
逆にしたＰチャネルＤＶ ＭＯＳ ＦＥＴに対して
も本発明を適用できることは勿論である。 更にモノリ
シックに内蔵するＭＯＳ ＦＥＴ構体の数も、ＦＥＴ
−Ａ及びＢの２個に制限されることはない。In the above embodiment, all N-channel DV MOS
Although only the FET has been described, it goes without saying that the present invention can also be applied to a P-channel DV MOS FET in which the conductivity types of the constituent semiconductor layers are reversed. Furthermore, the number of monolithically built-in MOS FET structures is also
- It is not limited to two, A and B.
ＩＧＢＴの構成は、ＤＶ ＭＯＳ ＦＥＴのＭＯＳ
ＦＥＴ構体の他方の基板主面側の一導電型ドレイン
領域上に更に反対導電型層を積層した半導体装置である
。 従って本発明は、ＩＧＢＴに対しても容易に適用す
ることができる。 ス同様のＭＯＳ ＦＥＴ構体を有
する二重拡散横型ＭＯ８ＦＥＴ等に対しても本発明を適
用できることは勿論である。IGBT configuration is DV MOS FET MOS
This is a semiconductor device in which a layer of an opposite conductivity type is further laminated on a drain region of one conductivity type on the other substrate main surface side of the FET structure. Therefore, the present invention can be easily applied to IGBTs as well. It goes without saying that the present invention can also be applied to a double diffusion horizontal MO8FET having a MOS FET structure similar to that of the MO8FET.
上記実施例のソース多出力のＤＶ ＭＯＳ ＦＥＴ
ではドレイン電極は共通であるか、本発明の半導体装置
は必ずしもこれに限定されないで、複数の分離されたド
レイン電極を持っていても差し支えない。Source multi-output DV MOS FET of the above embodiment
Is the drain electrode common? The semiconductor device of the present invention is not necessarily limited to this, and may have a plurality of separated drain electrodes.
し発明の効果コ
本発明のソース多出力電力用ＭＯ３ＰＥＴ等においては
、構成する複数のＭＯＳ ＦＥＴ構体はそれぞれにゲ
ート配線膜を有し、これまで述べたようにその抵抗値を
個々に所望値とすることができるので、各ＦＥＴ！ｓ体
のそれぞれのゲート電極電圧の立ち上がり特性を制御し
、スイッチング特性等を容易に変えることができる。
本発明により、ソース多出力電力用ＭＯ３ＦＥＴ等の応
用範囲を著しく拡大させることが可能となった。Effects of the Invention In the MO3PET for source multi-output power of the present invention, each of the plurality of MOS FET structures has a gate wiring film, and as described above, the resistance value can be adjusted individually to a desired value. Because each FET can be! The rising characteristics of the gate electrode voltage of each s-body can be controlled, and the switching characteristics etc. can be easily changed.
The present invention has made it possible to significantly expand the range of applications of source multi-output power MO3FETs and the like.
第１図（ａ ）は本発明の半導体装！の第１実施例の平
面概略図、同図（ｂ）はその部分断面図、第２図は本発
明の詳細な説明する図で、同図（ａ）は応用回路例、同
図（ｂ）はゲート入力電圧波形図、同図（Ｃ）はゲート
電極膜の電圧波形図、第３図は本発明の半導体装置の第
２実施例の平面概略図、第４図及び第５図は本発明の半
導体装置のゲート配・線膜の実施例を示す部分断面図、
第６図＜ａ）は従来の半導体装置の平面概略図、同図（
ｂ）はその部分断面図、同図（Ｃ）は単位ＦＥＴセルの
配置を示す部分平面図、第７図は課題を説明するための
応用回路図である。
１・・・半導体基板、 １ａ・・・Ｎ４ドレイン領域
、１ｂ・・・Ｎドレイン領域、 ２，１２，２２，３
２゜４２．５２．６２・・・ゲート引き出し用ボンデイ
ンパット、 ３ａ、３ｂ、１３ａ、１３ｂ、２３ａ。
２３ｂ 、３３ａ 、３３ｂ 、４３ａ 、５３ａ 。
６３ ａ ＝−・ゲート配線膜、 ５ａ、５ｂ、２５ａ
。
２５ｂ・・・ソース電極膜、 ６・・・Ｐベース領域、
７・・・Ｎ１ンース領域、 ８・・・ゲート酸化膜、
９・・層間絶縁膜、 Σ旦１口・・・本発明のＤＶ
ＭＯＳ ＰＥＴ、 ５０ａ、５０ｂ−＃ｍゲート型
トランジスタ楕構体ＭＯＳ ＦＥＴ−Ａ又はＢ）、Ｙ
−Ｙ’線・・・ゲート配線膜とゲート酸化膜との境界。FIG. 1(a) shows the semiconductor device of the present invention! FIG. 2 is a schematic plan view of the first embodiment of the present invention, FIG. 2 is a partial sectional view thereof, FIG. 3 is a diagram of the gate input voltage waveform, FIG. A partial cross-sectional view showing an example of a gate wiring/wiring film of a semiconductor device,
FIG. 6<a) is a schematic plan view of a conventional semiconductor device;
b) is a partial sectional view thereof, FIG. 7(C) is a partial plan view showing the arrangement of unit FET cells, and FIG. 7 is an applied circuit diagram for explaining the problem. 1... Semiconductor substrate, 1a... N4 drain region, 1b... N drain region, 2, 12, 22, 3
2゜42.52.62...Bondein pad for gate extraction, 3a, 3b, 13a, 13b, 23a. 23b, 33a, 33b, 43a, 53a. 63 a =--gate wiring film, 5a, 5b, 25a
. 25b... Source electrode film, 6... P base region,
7...N1 base region, 8...Gate oxide film,
9...Interlayer insulating film, Σdan 1 mouth...DV of the present invention
MOS PET, 50a, 50b-#m gate type transistor elliptical structure MOS FET-A or B), Y
-Y' line: Boundary between gate wiring film and gate oxide film.
Claims (1)
一導電型ドレイン領域と、このドレイン領域の前記表面
層に選択的に形成される反対導電型ベース領域と、この
ベース領域の表面層に選択的に形成される一導電型ソー
ス領域と、このソース領域と前記ドレイン領域とに挟ま
れる前記ベース領域の露出面上に絶縁体膜を介して積層
されるゲート電極膜と、ゲート電極膜に接続するゲート
配線膜と、前記ソース領域とオーミック接触をするソー
ス電極膜とを有する複数の絶縁ゲート型トランジスタ構
体と、前記ゲート配線膜の複数と接続するゲート引き出
し用ボンディングパッドとを具備し、且つ複数の前記ゲ
ート配線膜の電気抵抗が異なることを特徴とする半導体
装置。a drain region of one conductivity type having a surface layer exposed on one main surface of one semiconductor substrate; a base region of an opposite conductivity type selectively formed on the surface layer of this drain region; a source region of one conductivity type selectively formed; a gate electrode film laminated via an insulating film on the exposed surface of the base region sandwiched between the source region and the drain region; A plurality of insulated gate transistor structures each having a connected gate wiring film and a source electrode film in ohmic contact with the source region, and a gate lead-out bonding pad connected to the plurality of gate wiring films, and A semiconductor device characterized in that the plurality of gate wiring films have different electrical resistances.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2030905A JPH03235368A (en) | 1990-02-10 | 1990-02-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2030905A JPH03235368A (en) | 1990-02-10 | 1990-02-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03235368A true JPH03235368A (en) | 1991-10-21 |
Family
ID=12316739
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2030905A Pending JPH03235368A (en) | 1990-02-10 | 1990-02-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03235368A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07240516A (en) * | 1994-02-28 | 1995-09-12 | Mitsubishi Electric Corp | Field effect type semiconductor device and its manufacture |
| JPH0832060A (en) * | 1994-07-13 | 1996-02-02 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
| JPH08227996A (en) * | 1995-02-20 | 1996-09-03 | Fuji Electric Co Ltd | Semiconductor device |
| JP2000012839A (en) * | 1998-06-25 | 2000-01-14 | Nec Kansai Ltd | Semiconductor device |
| EP1296378A1 (en) * | 2001-09-21 | 2003-03-26 | STMicroelectronics S.r.l. | MOS semiconductor device and manufacturing process thereof |
| CN104347693A (en) * | 2013-07-23 | 2015-02-11 | 北大方正集团有限公司 | Power semiconductor device and manufacturing method thereof |
| JP2016031964A (en) * | 2014-07-28 | 2016-03-07 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| WO2017029748A1 (en) * | 2015-08-20 | 2017-02-23 | 株式会社日立製作所 | Semiconductor device, power module, power converter, vehicle, and train carriage |
| JP2020074382A (en) * | 2018-01-09 | 2020-05-14 | ローム株式会社 | Semiconductor device |
| JP2021007165A (en) * | 2014-05-12 | 2021-01-21 | ローム株式会社 | Semiconductor device |
| JP2021122076A (en) * | 2017-01-17 | 2021-08-26 | 富士電機株式会社 | Semiconductor device |
| US11942531B2 (en) | 2014-05-12 | 2024-03-26 | Rohm Co., Ltd. | Semiconductor device including sense insulated-gate bipolar transistor |
-
1990
- 1990-02-10 JP JP2030905A patent/JPH03235368A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07240516A (en) * | 1994-02-28 | 1995-09-12 | Mitsubishi Electric Corp | Field effect type semiconductor device and its manufacture |
| JPH0832060A (en) * | 1994-07-13 | 1996-02-02 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
| JPH08227996A (en) * | 1995-02-20 | 1996-09-03 | Fuji Electric Co Ltd | Semiconductor device |
| JP2000012839A (en) * | 1998-06-25 | 2000-01-14 | Nec Kansai Ltd | Semiconductor device |
| US6919252B2 (en) | 2001-09-21 | 2005-07-19 | Stmicroelectronics S.R.L. | Process for manufacturing MOS semiconductor device having inactive zone with alternating thickness silicon oxide layer |
| US6750512B2 (en) | 2001-09-21 | 2004-06-15 | Stmicroelectronics S.R.L. | MOS semiconductor device having inactive zone with alternating thickness silicon oxide layer located between a semiconductor region and a conductive layer |
| EP1296378A1 (en) * | 2001-09-21 | 2003-03-26 | STMicroelectronics S.r.l. | MOS semiconductor device and manufacturing process thereof |
| CN104347693A (en) * | 2013-07-23 | 2015-02-11 | 北大方正集团有限公司 | Power semiconductor device and manufacturing method thereof |
| JP2021007165A (en) * | 2014-05-12 | 2021-01-21 | ローム株式会社 | Semiconductor device |
| US11942531B2 (en) | 2014-05-12 | 2024-03-26 | Rohm Co., Ltd. | Semiconductor device including sense insulated-gate bipolar transistor |
| JP2016031964A (en) * | 2014-07-28 | 2016-03-07 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| WO2017029748A1 (en) * | 2015-08-20 | 2017-02-23 | 株式会社日立製作所 | Semiconductor device, power module, power converter, vehicle, and train carriage |
| JP2021122076A (en) * | 2017-01-17 | 2021-08-26 | 富士電機株式会社 | Semiconductor device |
| JP2020074382A (en) * | 2018-01-09 | 2020-05-14 | ローム株式会社 | Semiconductor device |
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