JP3002096B2 - Output buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit used for a semiconductor integrated circuit. In particular, the present invention relates to an output buffer circuit including a plurality of transistors and capable of adjusting a driving capability and the like, which has improved resistance to electrostatic breakdown.

[0002]

2. Description of the Related Art A large number of semiconductor integrated circuits are constructed by a gate array system because they can quickly respond to a change or correction of a design logic.

In this gate array type semiconductor integrated circuit, circuits having various functions can be realized only by changing wiring for one kind of diffusion layout. This applies to any area regardless of whether it is an internal logic (memory) area or an input / output buffer area. In particular, in an input / output buffer circuit, since it is necessary to realize functions and characteristics for interfacing with an external device, it is necessary to provide many transistors in the area. Further functions recently required to output buffer circuits for a variety of interface methods, properties increasingly growing, the number of elements such as transistors master slice gate array in accordance with the it must provide the output buffer area There is a tendency to increase significantly.

[0004] For example, in an output buffer circuit of a gate array type semiconductor device, the driving capability is generally adjusted by combining transistors provided in the region. Therefore, the number of transistors required to obtain the largest driving force must be provided in advance.

FIG. 7 is an explanatory diagram schematically showing a layout of two transistors sharing one source in an input / output buffer circuit of a conventional gate array type semiconductor device. The output buffer circuit shown in FIG. 7 is configured in a region including a small diffusion region 10 and large diffusion regions 12a and 12b provided so as to sandwich the small diffusion region. Gate electrodes 14a and 14b are provided on the upper surface of the region between the respective regions, and form transistors 16a and 16b, respectively, as shown in FIG. 9 described later.

In FIG. 7, two drain regions (large diffusion regions 12a and 12b) are connected to metal wiring by contact holes, and both are connected to pads (not shown). In FIG. 7 and subsequent drawings, a symbol with a cross mark in a square means a contact hole. On the other hand, the small diffusion region 10
6a and 16b serve as a common source and are connected to the metal wiring layer by contact holes. The gate electrodes 14a, 14b is also connected, on both electrodes the same signal is marked pressurized. Thus, the two transistors 16a and 16b are completely connected in parallel.

FIG. 8 is a sectional view taken along line VIII-VIII of FIG. FIG. 9A is a circuit diagram showing a connection relationship between the two transistors shown in FIG.
This is shown in (b). In this way, if wiring is performed as shown in FIG. 7, the two transistors are connected in parallel (see FIGS. 9A and 9B), and the driving capability can be enhanced. Conversely, a small driving capability can be obtained by using only one transistor.

In the input / output buffer circuits of semiconductor devices, layout and circuit design are often devised to prevent electrostatic breakdown. For example, in the two transistors shown in FIG. 7, the distance D between the drain contact (the contact hole used for the drain) and the gate is sufficiently large. Increasing the distance D increases the diffusion resistance of the drain, thereby increasing the resistance to electrostatic breakdown. When the distance D is increased in this manner, electrostatic breakdown is prevented by two effects, such as the above-described effect due to the diffusion resistance of the drain and the effect of the drain parasitic diode due to the large area of the drain.

As described above, in the output buffer circuit of the gate array type semiconductor device, the driving capability is generally adjusted by combining the transistors provided in the region. That is, a high driving capability can be obtained by connecting a plurality of transistors in parallel, and a very low driving capability can be obtained by connecting a plurality of transistors in series. FIG.
The two transistors which are connected in parallel as shown in, to configure the buffer circuit very low driving capability are connected in series, for example, is also conceivable to perform the metal wiring as shown in Figure 10 .

[0010] FIG. 10 is a circuit diagram showing two transistors connected in series using the substrate having the diffusion region shown in FIG. 7 as it is.
FIG. 4 is a schematic diagram illustrating a layout in a case where an output buffer is formed by connecting the plurality of output buffers. As shown in FIG.
In (2), a desired circuit (two transistors are connected in series) can be obtained by newly using one of the diffusion layers used as a drain region as a source region.

FIG. 11 is a sectional view taken along the line XI-XI # shown in FIG. FIGS. 12A and 12B are circuit diagrams in the case of the configuration shown in FIG.

However, when the layout is as shown in FIG. 10, the total area of the drains connected to the pads is half of that in FIG. 7, and the area of the parasitic diode which has the effect of preventing electrostatic breakdown can be sufficiently secured. Will be gone. On the other hand, the portion of the region newly used as the source region (that is, the large diffusion region 12b) does not function as a parasitic diode against electrostatic breakdown, and thus a useless region is generated. That is, the large diffusion region 12b is too large in area to be used as a source, and on the other hand, unlike the case of FIG. 7, only the large diffusion region 12a plays the role of a parasitic diode or the like against electrostatic breakdown. Would. Therefore, the output buffer circuit shown in FIG. 10 is actually insufficient in resistance to electrostatic breakdown.

Therefore, in the case where the metal wiring as shown in FIG. 10 is actually performed to connect the transistors in series, as shown in FIG.
One drain region (large diffusion region 12a) must be provided with twice the area. In addition, XIV in FIG.
A cross-sectional view at -XIV} is shown in FIG.

[0014]

However, as shown in FIG. 13, arranging one drain with a particularly large layout is extremely disadvantageous from the viewpoint of high integration. Not desirable.

[0015] The present invention has been made in view of the problems of its objects, in the output buffer having a plurality of transistors, the transistor and connected in series, and the child prevents the unused space occurs It is to provide a possible output buffer circuit.

[0016]

According to the present invention, in order to solve the above-mentioned problems, a plurality of transistors are connected in parallel or in series.
Output buffer circuit with adjustable drive capability.
Te, the output buffer circuit, and two or more small diffusion region, before SL and two or more two large diffusion area provided across the small diffusion regions, wherein the two or more small diffusion regions and 2
And a gate electrode that control the channel region formed between pieces of a large diffusion region, the two large diffusion area, before
It has a parasitic diode with a larger area than the small diffusion region,
Commonly connected and connected to the output terminal of the output buffer circuit
At least one of the two or more small diffusion regions
Is connected to the ground or power supply of the output buffer circuit,
At least one gate electrode in the gate electrode group is
Is output buffer circuit you characterized in that it is used as an input terminal of the output buffer circuit.

[0017]

In the present invention, the large diffusion regions are connected in common, and both regions can serve as a parasitic diode against electrostatic breakdown. In addition, a large diffusion region that does not contribute to the enhancement of the driving capability can be separated from other diffusion regions by applying a predetermined potential to a gate electrode in contact with the large diffusion region.

In other words, a potential that turns off the transistor corresponding to the gate electrode is applied to the gate electrode. As a result, an output buffer circuit having resistance to electrostatic breakdown can be configured without generating useless regions.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram showing a layout when an output buffer circuit according to a preferred embodiment of the present invention is configured on a master slice. As shown in FIG. 1, in the output buffer according to the present embodiment, two small diffusion regions 100a and 100b are provided. The small diffusion regions 100a and 100b are regions that do not have a large diffusion resistance for providing resistance to electrostatic breakdown or a large area parasitic diode. On the other hand, two large diffusion regions 102a and 102b are provided so as to sandwich the two small diffusion regions 100a and 100b. The two large diffusion regions 102a and 102b are
Unlike a and 100b, it is a region occupying a large area and having a large diffusion resistance and a large area of parasitic diode.

Between these four areas, three gap areas are formed, and three gap areas are formed so as to cover the three gap areas.
The gate electrodes 104a, 104b, and 104c are provided, respectively. As shown in FIG.
a and 104b are electrically connected. Thus, the gate electrodes 1 04a, 104b, by 104c is provided, the region of the gap may form a channel region. That is, the output buffer of this embodiment is formed on the substrate including the three transistors arranged in series.

As shown in FIG. 1, by performing metal wiring, the large diffusion region 102a serves as a drain of the transistor, and the other large diffusion region 102b is connected to the large diffusion region 102a by metal. The connection by the wiring plays a role of increasing the resistance to the electrostatic breakdown in the large diffusion region 102a. It should be noted that in this embodiment, a transistor corresponding to the gate electrode 104c is
Signal for F operation is that it is marked pressurized. Thus, the large diffusion region 102b only functions as a large-area diffusion region forming a parasitic diode. In this embodiment, the large diffusion region 102b not used as a drain is referred to as a "dummy drain".

FIG. 2 is a sectional view taken along the line II-II in FIG. In this cross-sectional view, the wiring on each region is schematically shown. FIG. 3 shows a circuit diagram of the output buffer. As shown in FIG. 3, the present output buffer is formed in a region including three transistors, and a circuit as shown in FIG. Is formed. As described above, FIG. 3A also shows that the gate electrodes 104a and 104b are electrically connected. That is, in FIG. 3 (a), 2 pieces of transistors 106a, the gate of 106b is connected, the common signal is marked pressurized. Further, the gate of the third transistor 106c shown in FIG.
By ground potential is marked pressure "signal to turn OFF the gate" is realized in FIG. still,
In this embodiment, all the transistors use N-type transistors. Therefore, the ground potential corresponds to the “signal for turning off the gate”. of course,
In the case of using a P-type transistor, the “Gate OFF
The power supply potential (Vdd) or the like may be used as the “signal to be caused”.

FIG. 3 (b) is a circuit diagram operatively rewritten from the circuit diagram of FIG. 3 (a). This FIG. 3 (b)
As shown in FIG. 7, the transistor 106c that is turned off is connected between the pad and the ground, and can increase the resistance to static electricity that enters from the pad. .

The feature of this embodiment is that not only two regions which can be channel regions but also three regions exist, that is, three transistors are provided. Thus, even when two transistors are connected in series by providing three transistors, by turning off the remaining one transistor, a large-area diffusion region (drain region) of the remaining transistor is provided. Region) can be used as a region for a diffusion resistance against electrostatic breakdown and a region for a parasitic diode. Therefore, as shown in FIG. 13 of the related art, there is no useless large-area area, and an efficient circuit configuration is possible.

As described above, according to the present embodiment, even when transistors are connected in series to form an output buffer having a low driving capability, a large-area diffusion region can be replaced with a diffusion resistance region and a parasitic diode. Therefore, there is no need to increase the area of any of the large-area diffusion regions in advance as shown in FIG. 13 of the related art.

As described above, according to the present embodiment, when a transistor is connected in series to form an output buffer having a low driving capability, a wasteful unused area is not generated. Although resistance to destruction can be maintained, it is of course possible to configure an output buffer having a large driving capability by connecting transistors in parallel. That is, a circuit equivalent to the conventional circuit as shown in FIG. 7 can be formed.

FIG. 4 shows the arrangement of the metal wiring and the like when a plurality of transistors are connected in parallel by devising the metal wiring in order to increase the driving capability of the output buffer according to this embodiment. It is a schematic diagram showing the situation of. By providing metal wiring as shown in FIG. 4, it is possible to form a circuit in which two transistors are connected in parallel. By performing such wiring, a circuit similar to that shown in FIG. 7 can be formed. That is, the large diffusion regions 102a and 102b are both used as drains, and are commonly connected to a pad (not shown outside). That is, the large diffusion regions 102a, 1
02b plays the role of the drains of the transistors 106a and 106c, respectively.

The source for transistor 106b
Since both drains are connected to the ground, the transistor 106b is not operating. The source and the drain of the transistor 106b are the sources of the transistor 106a and the transistor 106c, respectively. That is, the transistor 106a and the transistor 106c are connected in parallel. Of course, the gate electrodes 104a, 104b, a common signal to 104c are marked pressurized.

FIG. 5 is a sectional view taken along the line VV in FIG.
Is shown in According to FIG. 5, all the gate electrodes 104
a, 104b, a common signal 104c is marked pressurized, it will be understood that a large diffusion region 102a as a drain, 102 b are commonly connected to the pad.

FIG. 6A is a circuit diagram showing a case where two transistors are connected in parallel as shown in FIG. As described above, one of the three transistors 106b does not operate as a transistor at all because the source and the drain are connected to the ground. And the transistor 10
6a, 106 and c are connected in parallel. as a result,
An equivalent circuit diagram of the output buffer circuit shown in FIG. 4 is as shown in FIG.

As described above, the transistor 106
b is unused. As a result, the circuit shown in FIG. 4 requires about 20 percent more area than the conventional circuit (FIG. 7 ). This is because, as described above, the central transistor 106b is in an unused state and does not contribute to the operation of the circuit.

As described above, when the transistors are connected in parallel, there is a slight disadvantage as compared with the related art. However, when the above-described transistors are connected in series, there is no area disadvantage compared with the related art. An output buffer circuit having resistance to electrostatic breakdown is obtained. That is,
In the conventional output buffer, the area of one of the drains had to be almost doubled as described above, whereas in the present embodiment, the unused large diffusion region 10 was not used.
Large diffusion region 102 using 2b as drain
Because it was connected to a, without increasing the area at all,
This enables realization of series connection of transistors.

In this embodiment, two large-area diffusion regions and two large-area diffusion regions are sandwiched between the two large-area diffusion regions.
Although the example of the output buffer circuit including the small area diffusion regions has been described, any number of small area diffusion regions may be used as long as the number is two or more. For example, in this embodiment, the description has been given of the series / parallel connection of two transistors. However, when performing the series / parallel connection of three transistors, three small-area diffusion regions are replaced with two large-area diffusion areas. May be provided between the diffusion regions.

Furthermore, according to the present embodiment, it is very easy to connect two or more transistors in series or in parallel, so that the present invention can be applied to any circuit requiring such a configuration. It is possible.

For example, recently, for reasons of low power consumption and the like, 5
Various ICs that operate at a power supply voltage of less than 3 volts, for example, about 3 volts, are manufactured. At the interface between the 3 volt system and the 5 volt system, for example, as shown in FIG. A configuration in which two transistors are connected in series is employed. According to the present invention, the configuration of a circuit in which such transistors are connected in series can be extremely easily performed.

[0037]

As described above, according to the present invention, 2
It includes a large diffusion region and a plurality of small diffusion regions sandwiched between these regions, so even if the driving capability is adjusted by connecting a plurality of transistors in series or in parallel, the An output buffer circuit capable of maintaining immunity is obtained.

Further, according to the present invention, it is very easy to connect two or more transistors in series or in parallel, so that a circuit for controlling an interface between signals having different voltages can be easily formed. Having.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a layout when an output buffer circuit according to a preferred embodiment of the present invention is configured by connecting transistors in series.

FIG. 2 is a sectional view taken along line II-II in FIG.

FIG. 3 is a circuit diagram of an output buffer according to the layout shown in FIG. 1;

FIG. 4 is a schematic diagram showing a layout when an output buffer circuit according to a preferred embodiment of the present invention is configured by connecting transistors in parallel;

FIG. 5 is a sectional view taken along line VV in FIG.

FIG. 6 is a circuit diagram of an output buffer according to the layout shown in FIG. 4;

FIG. 7 is a schematic diagram showing a layout when a conventional output buffer circuit is configured by connecting transistors in parallel.

8 is a sectional view taken along line VIII-VIII in FIG.

FIG. 9 is a circuit diagram of an output buffer according to the layout shown in FIG. 7;

FIG. 10 is a schematic diagram showing a layout of an output buffer circuit when transistors are connected in series using the substrate having the diffusion region shown in FIG. 7;

11 is a sectional view taken along the line XI-XI # in FIG.

12 is a circuit diagram of an output buffer according to the layout shown in FIG.

13 is a schematic diagram showing a layout in a case where the area of the large diffusion region 12a of the output buffer circuit shown in FIG. 10 is increased to increase resistance to electrostatic breakdown.

14 is a sectional view taken along line XIV-XIV # in FIG.

FIG. 15 is a circuit diagram of another embodiment of the present invention.

[Explanation of symbols]

100a, 100b Small diffusion region, 102a, 102b
Large diffusion region, 104a, 104b, 104c Gate electrode.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/82 H01L 27/118

Claims (1)

(57) [Claims] A plurality of transistors are connected in parallel or in series.
Output buffer circuit with adjustable drive capability.
The output buffer circuit comprises: two or more small diffusion regions ; two or more large diffusion regions provided with the two or more small diffusion regions interposed therebetween; including the gate electrodes to control each channel region formed between the small diffusion regions and two large diffusion region
In addition, the two large diffusion regions have a wider surface than the small diffusion region.
Product with a parasitic diode and a common connected output buffer
And at least one of the two or more small diffusion regions is an output terminal.
Connected to the ground or power supply of the power buffer circuit, and at least one gate electrode of the gate electrode group is
The output buffer circuit you characterized in that it is used as an input terminal of the output buffer circuit.