CN104347693A - Power semiconductor device and manufacturing method thereof - Google Patents
Power semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- CN104347693A CN104347693A CN201310311327.6A CN201310311327A CN104347693A CN 104347693 A CN104347693 A CN 104347693A CN 201310311327 A CN201310311327 A CN 201310311327A CN 104347693 A CN104347693 A CN 104347693A
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- China
- Prior art keywords
- insulating medium
- medium layer
- semiconductor substrate
- layer
- grid conducting
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 114
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 80
- 238000000034 method Methods 0.000 claims description 24
- 239000012535 impurity Substances 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 238000009279 wet oxidation reaction Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 155
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
Abstract
The invention provides a power semiconductor device and a manufacturing method thereof. The device includes: a semiconductor substrate; a first insulating medium layer are arranged on a set area of a surface of the semiconductor substrate; second insulating medium layers are arranged on a partial area on a surface of the first insulating medium layer and surfaces of partial areas on the surface of the semiconductor substrate which are close to the set area, and the second insulating medium layer on the surface of the semiconductor substrate is communicated with the second insulating medium layer on the surface of the first insulating medium layer; gate conducting layers are arranged on the second insulating medium layers; body areas are arranged at two sides of the first insulating medium layer in positions corresponding to partial areas of the second insulating medium layers in the semiconductor substrate; and source electrode areas are arranged in positions close to edges of the gate conducting layers in the body areas. The power semiconductor device provided by the embodiment of the invention effectively solves the technical problems of large switching delay and low switching frequency of power semiconductor devices in existing technology.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of power semiconductor and manufacture method thereof.
Background technology
Along with the development of microelectric technique, power semiconductor, because it is when switch transition, has the short open and close time and is widely used in high frequency environment.And device at work, the operating frequency of delay during devices switch to device plays a decisive role.
Adopt power semiconductor that process of the prior art manufactures as shown in Figure 1, comprising: Semiconductor substrate 101, oxide layer 102, grid conducting layer 103, tagma 104 and source area 105, usually using Semiconductor substrate as drain region.From Fig. 1, know to only have the oxide layer that one deck is very thin below its grid of existing power semiconductor, cause the input capacitance Ciss between grid and substrate comparatively large, increase the switching delay of device, and then reduce switching frequency.
Summary of the invention
The invention provides a kind of power semiconductor and manufacture method thereof, in order to solve the semiconductor power device that prior art manufactures, devices switch postpones large, the technical problem that switching frequency is low.
On the one hand, the embodiment of the present invention provides a kind of power semiconductor, comprising:
Semiconductor substrate;
The setting regions on the surface of described Semiconductor substrate is provided with the first insulating medium layer;
The surface of the subregion near described setting regions on the surface of described first subregion, insulating medium layer upper surface and described Semiconductor substrate is provided with the second insulating medium layer, and the second insulating medium layer on described semiconductor substrate surface is communicated with described second insulating medium layer on described first insulating medium layer surface;
Described second insulating medium layer is provided with grid conducting layer;
In described Semiconductor substrate, described first insulating medium layer both sides and the position corresponding with described second insulating medium layer subregion are provided with tagma;
Source area is provided with near described grid conducting layer edge in described tagma.
On the other hand, the embodiment of the present invention provides a kind of power semiconductor manufacture method, comprising:
At Surface Creation first insulating medium layer of Semiconductor substrate;
Described first insulating medium layer is etched, to retain described first insulating medium layer in the setting regions on the surface of described Semiconductor substrate;
Other region surface on the surface with the surface of described Semiconductor substrate except described setting regions of described first insulating medium layer generate the second insulating medium layer;
Described second insulating medium layer generates grid conducting layer;
Described second insulating medium layer and described grid conducting layer are etched, to retain described grid conducting layer on the surface in described first insulating medium layer upper part region and described Semiconductor substrate on the position that the subregion of described setting regions is corresponding, the second insulating medium layer on described semiconductor substrate surface is communicated with described second insulating medium layer on described first insulating medium layer surface;
At described semiconductor substrate surface, described first insulating medium layer both sides and the position corresponding with described second insulating medium layer subregion are injected the first impurity and are formed tagma;
Inject the second impurity at described body surface near described grid conducting layer edge and form source area.
Power semiconductor provided by the invention and manufacture method thereof, arrange the first insulating medium layer, to increase the distance between grid conducting layer and Semiconductor substrate on the surface of Semiconductor substrate and the second dielectric interlayer; The second insulating medium layer is formed in the first subregion, insulating medium layer upper surface, grid conducting layer is formed on the second insulating medium layer surface of this subregion, to reduce cross-sectional area corresponding between grid conducting layer with Semiconductor substrate, and then reduce the switching delay of device, improve switching frequency.
Accompanying drawing explanation
Fig. 1 is the structural representation of power semiconductor of the prior art;
The structural representation of the power semiconductor embodiment that Fig. 2 provides for the embodiment of the present invention;
Fig. 3 is the flow chart of a power semiconductor manufacture method provided by the invention embodiment.
Embodiment
The structural representation of the power semiconductor embodiment that Fig. 2 provides for the embodiment of the present invention.As shown in Figure 2, this power semiconductor specifically comprises: Semiconductor substrate 201, first insulating medium layer 202, second insulating medium layer 203, grid conducting layer 204, tagma 205 and source area 206.
Particularly, shown in the present embodiment, structure is as follows:
The setting regions on the surface of Semiconductor substrate 201 is provided with the first insulating medium layer 202;
Subregion on the first insulating medium layer 202 surface, as the position of fringe region, is provided with the second insulating medium layer 203 with the surface of the subregion near setting regions (this setting regions is the region that the first insulating medium layer 202 contacts with Semiconductor substrate) on the surface of Semiconductor substrate.Can be understood as the second insulating medium layer 203 periphery and cover the region comprising all first insulating medium layer 202 places, and with the first insulating medium layer 202 region on mutually close Semiconductor substrate 201 surface, only with the first insulating medium layer 202 relative position on exist and there is no the subregion of covering second insulating medium layer 203 (this subregion can be specifically a relatively independent region, or multiple isolated area not of uniform size, and the concrete shape in region does not limit); The second insulating medium layer be arranged on Semiconductor substrate 201 surface is communicated with the second insulating medium layer 203 on the first insulating medium layer 202 surface.
Second insulating medium layer 203 is provided with grid conducting layer 204;
In Semiconductor substrate 201, the position corresponding with the second insulating medium layer subregion, the first insulating medium layer 202 both sides is provided with tagma 205;
Source area 206 is provided with near grid conducting layer 204 edge in tagma 205;
Semiconductor substrate in this device architecture can be considered the drain region of device.
Optionally, the surface of the first subregion, insulating medium layer 202 upper surface and Semiconductor substrate 201 is provided with the second insulating medium layer 203 on the surface of the subregion of setting regions, the surface being specifically as follows region on the first insulating medium layer 202 surface beyond the central area (this central area can be circular, the centrosymmetric images such as rectangle) of setting and Semiconductor substrate 201 is provided with the second insulating medium layer 203 near the surface of the subregion of setting regions.Can be understood as this second insulating medium layer 203 is middle " windowing " (covering without the second edge dielectric layer 203 in the central area of the first insulating medium layer 202), surrounding be communicated with or middle " windowing " directly the second edge dielectric layer 203 is divided into two with the first insulating medium layer 202 on the surface central point for symmetrical structure.
Optionally, the first insulating medium layer 202 can be the field oxide adopting wet oxidation to generate, and its thickness is for being more than or equal to 0.5 micron; The oxide layer that second insulating medium layer can generate for dry oxidation.
Power semiconductor provided by the invention, arranges the first insulating medium layer, to increase the distance between grid conducting layer and Semiconductor substrate on the surface of Semiconductor substrate and the second dielectric interlayer; The second insulating medium layer is formed in the first subregion, insulating medium layer upper surface, grid conducting layer is formed on the second insulating medium layer surface of this subregion, to reduce cross-sectional area corresponding between grid conducting layer with Semiconductor substrate, and then reduce the switching delay of device, improve switching frequency.
Fig. 3 is the flow chart of a power semiconductor manufacture method provided by the invention embodiment, and the method can manufacture the power semiconductor device structure of embodiment as shown in Figure 1.As shown in Figure 3, this power semiconductor manufacture method specifically comprises:
S301, at Surface Creation first insulating medium layer of Semiconductor substrate;
This Semiconductor substrate can for having lightly doped semi-conducting material, as silicon, gallium nitride, GaAs etc.Have lightly doped semiconductor substrate surface generate the first insulating medium layer at this, this first insulating medium layer can be silicon dioxide, silicon nitride etc.
S302, etches above-mentioned first insulating medium layer, to retain the first insulating medium layer in the setting regions on the surface of Semiconductor substrate;
S303, other region surface on the surface with the surface of Semiconductor substrate except described setting regions of the first insulating medium layer generate the second insulating medium layer;
The the first insulating medium layer surface retained after completing etching generates the second insulating medium layer with the surface of Semiconductor substrate except in other region surface contacted with the first insulating medium layer, and this second insulating medium layer can be silicon dioxide, silicon nitride.
S304, the second insulating medium layer generates grid conducting layer; This grid conducting layer can be polysilicon, various metal.
S305, above-mentioned second insulating medium layer and grid conducting layer are etched, the surface of the subregion on the first insulating medium layer and Semiconductor substrate to retain on the position that the subregion of setting regions is corresponding grid conducting layer on second insulating medium layer and this part second insulating medium layer, the second insulating medium layer on this semiconductor substrate surface is communicated with the second insulating medium layer on the first insulating medium layer surface;
Wherein, the second insulating medium layer on semiconductor substrate surface and grid conducting layer, constitute the gate region structure of a power semiconductor, the second dielectric on the first insulating medium layer surface and grid conducting layer then can see the gate electrode structure that above-mentioned gate regions is drawn as.Under normal circumstances, as shown in Figure 1, the gate electrode structure that adjacent two gate regions are drawn is the overall structure of a surperficial all standing.But the overall structure of this surperficial all standing makes surface area just right between gate electrode and substrate excessive, thus adds input capacitance therebetween.Method described in this programme be on the subregion on the first insulating medium layer retain (subregion be etched can be specifically a relatively independent region, or multiple isolated area not of uniform size, and the concrete shape in region does not limit) grid conducting layer on the second insulating medium layer and this part second insulating medium layer, to reduce surface area just right between gate electrode and substrate, and then less input capacitance between the two.Simultaneously, consider the gate regions of device and the integrated connection relation of gate electrode, when etching the grid conducting layer on the second insulating medium layer and this second insulating medium layer, ensure that the second insulating medium layer on semiconductor substrate surface is communicated with the second insulating medium layer on the first insulating medium layer surface.
S306, at semiconductor substrate surface, the position corresponding with the second insulating medium layer subregion, the first insulating medium layer both sides is injected the first impurity and is formed tagma;
At semiconductor substrate surface, the tagma that first impurity contrary with substrate conduction type forms power semiconductor is injected in the position corresponding with the second insulating medium layer subregion, the first insulating medium layer both sides.
S307, injects the second impurity at body surface near grid conducting layer edge and forms source area;
The device formed body surface and inject second impurity identical with substrate conduction type near the position at grid conducting layer edge and form the source area of power semiconductor.And usually, the substrate of power semiconductor is the drain region of whole device.
Optionally, when etching above-mentioned second insulating medium layer and grid conducting layer, specifically can to the second insulating medium layer and the grid conducting layer position corresponding with the central area of the first insulating medium layer surface set, with the surface of the second insulating medium layer and grid conducting layer and Semiconductor substrate away from position corresponding to the subregion of above-mentioned setting regions, the second insulating medium layer that these two positions are corresponding and grid conducting layer etch.Can be understood as is " windowing " (covering without the second edge dielectric layer and grid conducting layer in the central area of the first insulating medium layer) with the second insulating medium layer on the first insulating medium layer surface relative position and the central area of grid conducting layer, surrounding be communicated with or middle " windowing " direct second edge dielectric layer and grid conducting layer are divided into two with the first insulating medium layer on the surface central point for symmetrical structure.Wherein, symmetry can etch centered by the central point of the first insulating medium layer away from the second insulating medium layer corresponding to the position that the subregion of above-mentioned setting regions is corresponding and grid conducting layer the surface of Semiconductor substrate.
Optionally, wet process oxidation technology can be adopted at the Surface Creation of Semiconductor substrate as the field oxide of the first insulating medium layer at Surface Creation first insulating medium layer of Semiconductor substrate; Other region surface on the surface with the surface of Semiconductor substrate except above-mentioned setting regions of first insulating medium layer generate the second insulating medium layer can adopt dry oxidation technique in other region surface on the surface with the surface of Semiconductor substrate except setting regions of the first insulating medium layer, generate oxide layer as the second insulating medium layer.
Power semiconductor manufacture method provided by the invention, arranges the first insulating medium layer, to increase the distance between grid conducting layer and Semiconductor substrate on the surface of Semiconductor substrate and the second dielectric interlayer; The second insulating medium layer is formed in the first subregion, insulating medium layer upper surface, grid conducting layer is formed on the second insulating medium layer surface of this subregion, to reduce cross-sectional area corresponding between grid conducting layer with Semiconductor substrate, and then reduce the switching delay of device, improve switching frequency.
One of ordinary skill in the art will appreciate that: all or part of step realizing above-mentioned each embodiment of the method can have been come by the hardware that program command is relevant.Aforesaid program can be stored in a computer read/write memory medium.This program, when performing, performs the step comprising above-mentioned each embodiment of the method; And aforesaid storage medium comprises: ROM, RAM, magnetic disc or CD etc. various can be program code stored medium.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (10)
1. a power semiconductor, is characterized in that, comprising:
Semiconductor substrate;
The setting regions on the surface of described Semiconductor substrate is provided with the first insulating medium layer;
The surface of the subregion near described setting regions on the surface of described first subregion, insulating medium layer upper surface and described Semiconductor substrate is provided with the second insulating medium layer, and the second insulating medium layer on described semiconductor substrate surface is communicated with described second insulating medium layer on described first insulating medium layer surface;
Described second insulating medium layer is provided with grid conducting layer;
In described Semiconductor substrate, the position corresponding with described second insulating medium layer subregion, described first insulating medium layer both sides is provided with tagma;
Source area is provided with near described grid conducting layer edge in described tagma.
2. power semiconductor according to claim 1, it is characterized in that, the region except the surperficial central area except setting of described first insulating medium layer and the surface of described Semiconductor substrate are provided with the second insulating medium layer near the surface of the subregion of described setting regions.
3. power semiconductor according to claim 2, is characterized in that, described second insulating medium layer is symmetrical centered by the central point of described first insulating medium layer.
4. the power semiconductor according to any one of claim 1-3, is characterized in that, the thickness of described first insulating medium layer is more than or equal to 0.5 micron.
5. the power semiconductor according to any one of claim 1-3, is characterized in that, described first insulating medium layer is the field oxide adopting wet oxidation to generate; And/or,
Described second insulating medium layer is the oxide layer that dry oxidation generates.
6. a power semiconductor manufacture method, is characterized in that, comprising:
At Surface Creation first insulating medium layer of Semiconductor substrate;
Described first insulating medium layer is etched, to retain described first insulating medium layer in the setting regions on the surface of described Semiconductor substrate;
Other region surface on the surface with the surface of described Semiconductor substrate except described setting regions of described first insulating medium layer generate the second insulating medium layer;
Described second insulating medium layer generates grid conducting layer;
Described second insulating medium layer and described grid conducting layer are etched, to retain described second insulating medium layer and described grid conducting layer on the surface in described first insulating medium layer upper part region and described Semiconductor substrate on the position that the subregion of described setting regions is corresponding, the described grid conducting layer on described semiconductor substrate surface is communicated with the described grid conducting layer on described first insulating medium layer surface;
At described semiconductor substrate surface, the position corresponding with described second insulating medium layer subregion, described first insulating medium layer both sides is injected the first impurity and is formed tagma;
Inject the second impurity at described body surface near described grid conducting layer edge and form source area.
7. power semiconductor manufacture method according to claim 6, is characterized in that, describedly etches described second insulating medium layer and described grid conducting layer, comprising:
To described second insulating medium layer and described grid conducting layer, etch away from described second insulating medium layer corresponding to the position that the subregion of described setting regions is corresponding and described grid conducting layer with the described central area of the first insulating medium layer surface set and the surface of described Semiconductor substrate.
8. power semiconductor manufacture method according to claim 7, it is characterized in that, the surface of described Semiconductor substrate is etched away from described second insulating medium layer corresponding to the position that the subregion of described setting regions is corresponding and described grid conducting layer, comprising:
To the surface of described Semiconductor substrate away from described second insulating medium layer corresponding to the position that the subregion of described setting regions is corresponding and described grid conducting layer, symmetrical etching centered by the central point of described first insulating medium layer.
9. the power semiconductor manufacture method according to any one of claim 6-8, is characterized in that, described Surface Creation first insulating medium layer in Semiconductor substrate, comprising:
Adopt wet process oxidation technology at the Surface Creation of described Semiconductor substrate as the field oxide of described first insulating medium layer.
10. the power semiconductor manufacture method according to any one of claim 6-8, it is characterized in that, describedly in other region surface on the surface with the surface of described Semiconductor substrate except described setting regions of described first insulating medium layer, generate the second insulating medium layer, comprising:
Adopt dry oxidation technique in other region surface on the surface with the surface of described Semiconductor substrate except described setting regions of described first insulating medium layer, generate oxide layer as described second insulating medium layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310311327.6A CN104347693A (en) | 2013-07-23 | 2013-07-23 | Power semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310311327.6A CN104347693A (en) | 2013-07-23 | 2013-07-23 | Power semiconductor device and manufacturing method thereof |
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| Publication Number | Publication Date |
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| CN104347693A true CN104347693A (en) | 2015-02-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310311327.6A Pending CN104347693A (en) | 2013-07-23 | 2013-07-23 | Power semiconductor device and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111354788A (en) * | 2020-03-24 | 2020-06-30 | 成都森未科技有限公司 | Deep trench insulated gate device and preparation method thereof |
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| JPS57103361A (en) * | 1980-10-29 | 1982-06-26 | Siemens Ag | Mis controlled semiconductor element |
| JPH03235368A (en) * | 1990-02-10 | 1991-10-21 | Toshiba Corp | Semiconductor device |
| JPH0475388A (en) * | 1990-07-18 | 1992-03-10 | Nec Corp | Semiconductor device and manufacture thereof |
| WO1998019344A1 (en) * | 1996-10-25 | 1998-05-07 | Siliconix Incorporated | Threshold adjust in vertical dmos transistor |
| CN1720622A (en) * | 2002-12-09 | 2006-01-11 | 半导体元件工业有限责任公司 | Vertical MOS power crystal |
-
2013
- 2013-07-23 CN CN201310311327.6A patent/CN104347693A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57103361A (en) * | 1980-10-29 | 1982-06-26 | Siemens Ag | Mis controlled semiconductor element |
| JPH03235368A (en) * | 1990-02-10 | 1991-10-21 | Toshiba Corp | Semiconductor device |
| JPH0475388A (en) * | 1990-07-18 | 1992-03-10 | Nec Corp | Semiconductor device and manufacture thereof |
| WO1998019344A1 (en) * | 1996-10-25 | 1998-05-07 | Siliconix Incorporated | Threshold adjust in vertical dmos transistor |
| CN1720622A (en) * | 2002-12-09 | 2006-01-11 | 半导体元件工业有限责任公司 | Vertical MOS power crystal |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111354788A (en) * | 2020-03-24 | 2020-06-30 | 成都森未科技有限公司 | Deep trench insulated gate device and preparation method thereof |
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