CN108807398B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN108807398B CN108807398B CN201810589348.7A CN201810589348A CN108807398B CN 108807398 B CN108807398 B CN 108807398B CN 201810589348 A CN201810589348 A CN 201810589348A CN 108807398 B CN108807398 B CN 108807398B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000003860 storage Methods 0.000 claims abstract description 77
- 230000005641 tunneling Effects 0.000 claims abstract description 46
- 230000003647 oxidation Effects 0.000 claims abstract description 43
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910014299 N-Si Inorganic materials 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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Abstract
The invention provides a semiconductor device and a method of manufacturing the same, the method including: firstly, forming a tunneling oxide layer, a floating gate layer, a control gate layer and a word line of a storage region on a substrate; secondly, etching the control gate layer and the floating gate layer to form a control gate, a floating gate and a control gate contact hole; thirdly, performing first rapid thermal oxidation on the tunneling oxide layer of the storage region to increase the thickness of the tunneling oxide layer; then, forming an oxide layer and a grid structure of a logic area on the substrate; and finally, carrying out second-time rapid thermal oxidation on the tunneling oxide layer of the storage region to increase the thickness of the tunneling oxide layer of the storage region again, and simultaneously carrying out rapid thermal oxidation on the oxide layer of the logic region to increase the thickness of the oxide layer of the logic region, so that the formed thickness of the tunneling oxide layer of the storage region is larger than that of the oxide layer of the logic region. The invention reduces the gate-induced drain leakage current and improves the performance of the semiconductor device.
Description
Technical Field
The present invention relates to the field of integrated circuit technology, and more particularly, to a semiconductor device and a method for manufacturing the same.
Background
The Gate induced Drain Leakage current (GIDL) of a semiconductor device occurs below the Gate-Drain overlap region. Taking an NMOS device as an example, an overlap region exists between a drain region and a gate, when a gate voltage is less than 0 and an operating voltage is applied to the drain region, the overlap region will accumulate depletion/deep depletion of original N-Si in the drain region under the overlap region, and a strong electric field of the drain region is applied to the depletion region to generate Carrier recombination (Trap-Assisted Carrier-Generation) of an auxiliary Trap, wherein the process is a process from a valence band to a Trap first and then from the Trap to a conduction band. The main factors responsible for GIDL are: and the thickness of the oxide layer between the overlapped region of the drain region and the grid electrode. For semiconductor devices such as single-chip microcomputers and programmable logic controllers having logic regions and storage regions, the fabrication process generally comprises the steps of forming the logic regions, then forming the storage regions, and then simultaneously performing rapid thermal oxidation on oxide layers on substrates of the logic regions and the storage regions to increase the thicknesses of the oxide layers of the logic regions and the storage regions, thereby reducing gate-induced drain leakage current. However, when the semiconductor device with the size of less than 90 nanometers is manufactured by the method, due to the small size of the device, the structures such as the oxide layers of the storage region and the logic region are correspondingly reduced in equal proportion, the tunneling oxide layer of the storage region and the oxide layer of the logic region are reduced, the GIDL is improved, and the tunneling oxide layer of the storage region is influenced by the electron tunneling effect, so that the storage performance of the storage region is influenced, and the overall performance of the semiconductor device is influenced. Therefore, how to improve a manufacturing method of a semiconductor device adapted to 90 nm in size to reduce the gate-induced drain leakage current is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, so as to reduce the gate-induced drain leakage current and improve the performance of the semiconductor device.
In order to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor device including a logic region and a memory region, comprising:
firstly, forming a tunneling oxide layer, a floating gate layer, a control gate layer and a word line of a storage region on a substrate;
secondly, etching the control gate layer and the floating gate layer to form a control gate, a floating gate and a control gate contact hole;
thirdly, performing first rapid thermal oxidation on the tunneling oxide layer of the storage region to increase the thickness of the tunneling oxide layer;
then, forming an oxide layer and a grid structure of a logic area on the substrate;
and finally, carrying out second-time rapid thermal oxidation on the tunneling oxide layer of the storage region to increase the thickness of the tunneling oxide layer of the storage region again, and simultaneously carrying out rapid thermal oxidation on the oxide layer of the logic region to increase the thickness of the oxide layer of the logic region, so that the formed thickness of the tunneling oxide layer of the storage region is larger than that of the oxide layer of the logic region.
Further, in the manufacturing method of the semiconductor device provided by the present invention, the step of performing a first rapid thermal oxidation on the tunneling oxide layer of the storage region includes: and carrying out rapid thermal oxidation on the tunneling oxide layer on one side of the storage region.
Further, in the manufacturing method of the semiconductor device provided by the present invention, the step of performing a first rapid thermal oxidation on the tunneling oxide layer of the storage region includes: and carrying out rapid thermal oxidation on the tunneling oxide layers on the two sides of the storage region.
Further, the manufacturing method of the semiconductor device provided by the invention comprises the step of depositing a hard mask to shield the logic region and expose the storage region before forming the control gate contact hole.
Further, in the manufacturing method of the semiconductor device provided by the invention, the etching is a photolithography process.
Furthermore, the manufacturing method of the semiconductor device provided by the invention further comprises the step of performing ion implantation on the storage region to form a lightly doped region before the step of performing the first rapid thermal oxidation on the tunneling oxide layer of the storage region.
Further, the invention provides a manufacturing method of the semiconductor device, and the storage area is a split-gate flash memory device.
Further, the manufacturing method of the semiconductor device provided by the invention is a process below 90 nm in size.
Furthermore, the manufacturing method of the semiconductor device provided by the invention further comprises a cleaning step before the rapid thermal oxidation step.
Compared with the prior art, the manufacturing method of the semiconductor device provided by the invention can be used for manufacturing the semiconductor device with the size of less than 90 nanometers, wherein a part of the storage region is formed firstly, then the tunneling oxide layer of the storage region is subjected to first rapid thermal oxidation, then a part of the logic region is formed, then the tunneling oxide layer of the storage region is subjected to second rapid thermal oxidation, and only one rapid thermal oxidation is performed on the oxide layer of the logic region, so that the thickness of the tunneling oxide layer of the storage region of the formed semiconductor device is larger than that of the oxide layer of the logic region, namely, the purpose of reducing the gate induced drain leakage current of the storage region is achieved by increasing the thickness of the tunneling oxide layer of the storage region. The logic area of the semiconductor device formed by the invention only has a primary rapid thermal oxidation process, and the tunneling oxide layer of the storage area has a secondary rapid thermal oxidation process, so that the oxide layer of the logic area of the semiconductor device is not influenced, and the device performance of the storage area of the semiconductor device is improved. Thereby improving the overall performance of the semiconductor device.
In order to solve the above technical problem, the present invention further provides a semiconductor device, which includes a storage region and a logic region, wherein a thickness of a tunneling oxide layer of the storage region is greater than a thickness of an oxide layer of the logic region.
Compared with the prior art, the semiconductor device provided by the invention changes the mode that the thicknesses of the tunneling oxide layer of the storage region and the oxide layer of the logic region of the semiconductor device in the prior art are equal, so that the thickness of the formed tunneling oxide layer of the storage region is larger than that of the oxide layer of the logic region, and the purpose of reducing the gate-induced drain leakage current of the storage region is achieved by increasing the thickness of the tunneling oxide layer of the storage region. The invention improves the performance of the semiconductor device.
Drawings
Fig. 1 to 5 are process diagrams of a manufacturing process of a semiconductor device according to an embodiment of the present invention;
fig. 6 to 9 are process diagrams of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Detailed Description
The invention is described in detail below with reference to the attached drawing figures:
example one
Referring to fig. 1 to 9, the method for manufacturing a semiconductor device having a memory area 110 and a logic area 120 according to an embodiment of the present invention is suitable for a semiconductor device having a size of less than 90 nm, and is also suitable for a semiconductor device having a size of more than 90 nm, such as a single chip microcomputer and an editable logic controller. The manufacturing method specifically comprises the following steps:
in step 201, referring to fig. 1, a tunnel oxide layer 111, a floating gate layer, a control gate layer and a word line 114 of a storage region 110 are formed on a substrate 100. The sidewalls 115 of the memory region 110 may also be formed at the same time. The memory region 110 is a split gate flash memory device.
Step 202, referring to fig. 2 and fig. 6, etching the control gate layer and the floating gate layer to form a control gate 113, a floating gate 112 and a control gate contact hole 116; the etching is a photolithographic process.
Step 203, please refer to fig. 2 and fig. 6, performing a first rapid thermal oxidation on the tunnel oxide layer 111 of the storage region 110 to increase the thickness of the tunnel oxide layer 111; in step 203, the thickness of the tunnel oxide layer 111 is increased for the first time, and the increased thickness of the tunnel oxide layer 111 is a.
In step 204, referring to fig. 3 and fig. 7, the oxide layer 121 and the gate structure 122 of the logic region 120 are formed on the substrate 100. The isolation structure 123 may also be formed at the same time.
Step 205, referring to fig. 4 and fig. 8, performing a second rapid thermal oxidation on the tunnel oxide layer 111 of the storage region 110 to increase the thickness of the tunnel oxide layer 111 of the storage region 110 again, and performing a rapid thermal oxidation on the oxide layer 121 of the logic region 120 to increase the thickness of the oxide layer 121 of the logic region 120, so that the thickness of the formed tunnel oxide layer 111 is greater than the thickness of the oxide layer 121 of the logic region. At this time, the tunnel oxide layer 111 of the storage region 110 is increased for the second time, i.e. the thickness is increased on the basis of the increased thickness a, the thickness of the tunnel oxide layer 111 increased for the second time is b, where b > a, and the thickness of the oxide layer 121 of the logic region increased is c, where b > c.
The method for manufacturing a semiconductor device provided by the embodiment of the invention can be used for manufacturing a semiconductor device with a size of less than 90 nanometers, and comprises the steps of firstly forming a part of the storage region 110, then carrying out first rapid thermal oxidation on the tunneling oxide layer 111 of the storage region 110, then forming a part of the logic region 120, then carrying out second rapid thermal oxidation on the tunneling oxide layer 111 of the storage region 110, and carrying out only one rapid thermal oxidation on the oxide layer 121 of the logic region 120, so that the thickness of the tunneling oxide layer 111 of the storage region 110 of the formed semiconductor device is larger than that of the oxide layer 121 of the logic region 120, namely, the purpose of reducing the gate-induced drain leakage current of the storage region 110 is achieved by increasing the thickness of the tunneling oxide layer 111 of the storage. The logic region 120 of the semiconductor device formed in the embodiment of the invention only has a primary rapid thermal oxidation process, and the tunneling oxide layer 11 of the storage region 110 has a secondary rapid thermal oxidation process, so that the performance of the logic region 120 of the semiconductor device is not affected, and the device performance of the storage region of the semiconductor device is improved. Thereby improving the overall performance of the semiconductor device.
Referring to fig. 1 to 5, in the method for manufacturing a semiconductor device according to the embodiment of the invention, during the rapid thermal oxidation process, the rapid thermal oxidation process is performed to the portion 100 below the tunnel oxide layer 111, so that the substrate 100 is recessed downward, thereby increasing the thickness of the tunnel oxide layer 111.
Referring to fig. 6 to 9, in the method for manufacturing a semiconductor device according to the embodiment of the invention, during the rapid thermal oxidation process, the tunnel oxide layer 111 is formed thereon, so that the floating gate 112 is thinned, thereby increasing the thickness of the tunnel oxide layer 111.
Referring to fig. 4, in the method for manufacturing a semiconductor device according to the embodiment of the invention, the step of performing a first rapid thermal oxidation on the tunnel oxide layer 111 of the storage region 110 is to perform a rapid thermal oxidation on the tunnel oxide layer 111 on one side of the storage region 110. Referring to fig. 5 and fig. 9, rapid thermal oxidation may also be performed on the tunnel oxide layer 111 on both sides of the storage region 110.
The method for manufacturing the semiconductor device according to the embodiment of the invention includes a step of depositing a hard mask to shield the logic region 120 and expose the storage region 110 before forming the contact hole for the control gate 113. The purpose is to form part of the memory area 110 and then part of the logic area 120.
The method for manufacturing a semiconductor device according to the embodiment of the present invention further includes, before the step of performing the first rapid thermal oxidation on the tunnel oxide layer 111 of the storage region 110, performing ion implantation on the storage region 110 to form a lightly doped region.
The manufacturing method of the semiconductor device provided by the embodiment of the invention further comprises a cleaning step before the rapid thermal oxidation step so as to ensure the cleanliness of the process manufacturing process.
The method for manufacturing the semiconductor device provided by the embodiment of the invention further comprises the steps of subsequent processes for forming the memory region 110 and the logic region 120 so as to form a complete semiconductor device.
Referring to fig. 4 and fig. 7, an embodiment of the invention further provides a semiconductor device, which includes a storage region 110 and a logic region 120, wherein a thickness of a tunneling oxide layer 111 of the storage region 110 is greater than a thickness of an oxide layer 121 of the logic region 120.
The semiconductor device provided by the embodiment of the invention changes the design mode that the thicknesses of the tunneling oxide layer 111 of the storage area 110 and the oxide layer 121 of the logic area 120 of the semiconductor device in the prior art are equal, so that the thickness of the formed tunneling oxide layer 111 of the storage area 110 is larger than that of the oxide layer 121 of the logic area 120, the purpose of reducing the gate-induced drain leakage current of the storage area 110 is achieved by increasing the thickness of the tunneling oxide layer 111 of the storage area 110, and the performance of the semiconductor device is improved.
The present invention is not limited to the above-described embodiments, and various changes and modifications within the scope of the present invention are within the scope of the present invention.
Claims (9)
1. A method of manufacturing a semiconductor device including a logic region and a storage region, comprising:
firstly, forming a tunneling oxide layer, a floating gate layer, a control gate layer and a word line of a storage region on a substrate;
secondly, etching the control gate layer and the floating gate layer to form a control gate, a floating gate and a control gate contact hole;
thirdly, performing first rapid thermal oxidation on the tunneling oxide layer of the storage region to increase the thickness of the tunneling oxide layer;
then, forming an oxide layer and a grid structure of a logic area on the substrate;
and finally, carrying out second-time rapid thermal oxidation on the tunneling oxide layer of the storage region to increase the thickness of the tunneling oxide layer of the storage region again, and simultaneously carrying out rapid thermal oxidation on the oxide layer of the logic region to increase the thickness of the oxide layer of the logic region, so that the formed thickness of the tunneling oxide layer of the storage region is larger than that of the oxide layer of the logic region.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of performing the first rapid thermal oxidation of the tunnel oxide layer of the storage region comprises: and carrying out rapid thermal oxidation on the tunneling oxide layer on one side of the storage region.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the step of performing the first rapid thermal oxidation of the tunnel oxide layer of the storage region comprises: and carrying out rapid thermal oxidation on the tunneling oxide layers on the two sides of the storage region.
4. The method of claim 1, further comprising depositing a hard mask to block the logic region and expose the storage region prior to forming the control gate contact hole.
5. The method for manufacturing a semiconductor device according to claim 1, wherein the etching is a photolithography process.
6. The method of manufacturing a semiconductor device according to claim 1, further comprising, before the step of performing the first rapid thermal oxidation of the tunnel oxide layer of the memory region, performing ion implantation into the memory region to form a lightly doped region.
7. The method for manufacturing a semiconductor device according to claim 1, wherein the memory region is a split gate flash memory device.
8. The method for manufacturing a semiconductor device according to claim 1, wherein the method for manufacturing a semiconductor device is a 90 nm-or-smaller-sized process.
9. A method for manufacturing a semiconductor device according to claim 1, further comprising a step of cleaning before the rapid thermal oxidation step.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040041792A (en) * | 2002-11-11 | 2004-05-20 | 주식회사 하이닉스반도체 | A method for manufacturing of merged memory logic in semiconductor device |
| CN104952804A (en) * | 2014-03-31 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Method for making embedded flash |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US10269822B2 (en) * | 2015-12-29 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to fabricate uniform tunneling dielectric of embedded flash memory cell |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040041792A (en) * | 2002-11-11 | 2004-05-20 | 주식회사 하이닉스반도체 | A method for manufacturing of merged memory logic in semiconductor device |
| CN104952804A (en) * | 2014-03-31 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Method for making embedded flash |
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