KR20040041792A - A method for manufacturing of merged memory logic in semiconductor device - Google Patents
A method for manufacturing of merged memory logic in semiconductor device Download PDFInfo
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- KR20040041792A KR20040041792A KR1020020069669A KR20020069669A KR20040041792A KR 20040041792 A KR20040041792 A KR 20040041792A KR 1020020069669 A KR1020020069669 A KR 1020020069669A KR 20020069669 A KR20020069669 A KR 20020069669A KR 20040041792 A KR20040041792 A KR 20040041792A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000005641 tunneling Effects 0.000 claims abstract description 6
- 239000002131 composite material Substances 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 abstract 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 5
- 229910021342 tungsten silicide Inorganic materials 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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Abstract
Description
본 발명은 복합 반도체 장치의 제조방방에 관한 것으로, 특히 산화막 하드 마스크를 이용하여 수직한 식각 프로파일을 갖는 복합 반도체 장치의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a composite semiconductor device, and more particularly, to a method for manufacturing a composite semiconductor device having a vertical etching profile using an oxide film hard mask.
일반적으로 메모리(Memory)와 로직(Logic) 등이 단일 칩에 형성되는 복합반도체(MML : Merged Memory Logic)가 최근에 들어 많은 관심을 보이면서 점차적으로 많이 사용하는 추세에 있으며, 이 MML 반도체 장치는 로직과 DRAM 및 SRAM 등의 메모리를 한 칩에서 단일한 공정으로 제조하는 것이 가능하므로 특별한 설계의 변경 없이도 기존의 칩들에 비하여 고속으로 동작하고, 저전력으로 사용하는 것이 가능한 장점을 지닌다.In general, composite semiconductors (MML: Merged Memory Logic), in which memory and logic are formed on a single chip, have been recently used with increasing interest, and MML semiconductor devices have been increasingly used. And memory such as DRAM and SRAM can be manufactured in a single process in one chip, and thus, it is possible to operate at a higher speed and use at lower power than existing chips without a special design change.
그러나 메모리 제품의 제조공정과 로직제품의 제조공정이 한 칩에서 동시에 제조되므로 단위 칩의 크기가 커지며, 이에 따라 제조공정을 진행하기에 많은 어려움을 요하는 단점도 지니고 있을 뿐만 아니라, 메모리에서의 트랜지스터는 높은 전류 구동력을 요하는 것보다 오히려 누설전류를 방지하는 것에 비중을 두고 있으나 로직제품은 높은 전류구동능력을 요구하는 등 양자의 특성을 모두 갖추어서 한 칩으로 제조하여야 하므로 제조상에 상당한 어려움이 수반된다.However, since the manufacturing process of the memory product and the manufacturing process of the logic product are manufactured on the same chip at the same time, the size of the unit chip is increased, and therefore, it has not only a disadvantage that requires a lot of difficulty in the manufacturing process, but also a transistor in the memory. Rather than requiring high current driving force, the emphasis is on preventing leakage current, but the logic products require a high current driving capability, so they have to be manufactured with one chip with both characteristics, which is a considerable difficulty in manufacturing. do.
이와 같이 다른 소자를 한 칩으로 제조하는 것이 상당히 어렵지만, 최근의 추세에 맞추어서 각종의 서로 다른 반도체 장치를 하나의 단일 칩으로 제조하는 방법이 점차적으로 다양화되고, 보편화되고 있다.As described above, it is quite difficult to manufacture different devices on one chip, but in accordance with the recent trend, methods of manufacturing various different semiconductor devices on one single chip are gradually diversified and become commonplace.
이하, 첨부된 도면을 참조하여 종래의 복합 반도체 장치의 제조방법에 대하여 설명하기로 한다.Hereinafter, a manufacturing method of a conventional composite semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1c는 종래의 복합 반도체장치 중에서 FML(Flash Merged Logic) 반도체 장치의 제조방법을 나타낸 공정 단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a FML (Flash Merged Logic) semiconductor device in a conventional composite semiconductor device.
종래의 FML 반도체장치의 제조방법은, 도 1a에 도시한 바와 같이, 플래쉬 메모리 영역과 로직영역을 갖는 반도체 기판(10)에 STI(Shallow Trench Isolation) 구조를 갖는 소자 격리막(11)을 형성한다.In the conventional method for manufacturing a FML semiconductor device, as shown in FIG. 1A, an element isolation film 11 having a shallow trench isolation (STI) structure is formed on a semiconductor substrate 10 having a flash memory region and a logic region.
이어, 상기 반도체 기판(10) 전면에 산화막(미도시)과 제 1 폴리 실리콘층(미도시)을 차례로 형성한 후, 상기 제 1폴리 실리콘층 상에 감광막을 도포하고 노광 및 현상하여 플래쉬 메모리영역에서의 플로팅 게이트 형성영역(미도시)을 덮는 제 1감광막 패턴(14)을 형성한다. 이어, 상기 제 1감광막 패턴(14)을 마스크로 하고 상기 막들을 식각하여 플래쉬 메모리 영역에 터널링 산화막(12), 플로팅 게이트(13a)를 형성한다.Subsequently, an oxide film (not shown) and a first polysilicon layer (not shown) are sequentially formed on the entire surface of the semiconductor substrate 10, and then a photosensitive film is coated on the first polysilicon layer, followed by exposure and development. A first photoresist pattern 14 is formed to cover a floating gate formation region (not shown). Subsequently, the first photoresist pattern 14 is used as a mask and the layers are etched to form a tunneling oxide layer 12 and a floating gate 13a in a flash memory region.
그런 다음, 상기 감광막 패턴을 제거한 후, 도 1b에 도시한 바와 같이, 상기 결과물 상에 ONO(Oxide-Nitride-Oxide)막(15), 제 2폴리 실리콘층(107) 및 텅스텐 실리사이드층(108)을 차례로 형성한다. 이 후, 상기 텅스텐 실리사이드층(108) 상에 플래쉬 메모리영역에서의 콘트롤 게이트 형성영역(미도시) 및 로직영역에서의 게이트 형성영역(미도시)을 덮는 제 2감광막 패턴(19)을 형성한다.After removing the photoresist pattern, an oxide-nitride-oxide (ONO) film 15, a second polysilicon layer 107, and a tungsten silicide layer 108 are formed on the resultant as shown in FIG. 1B. Form in turn. Thereafter, a second photoresist pattern 19 is formed on the tungsten silicide layer 108 to cover the control gate formation region (not shown) in the flash memory region and the gate formation region (not shown) in the logic region.
이어, 도 1c에 도시된 바와 같이, 상기 제 2감광막 패턴을 마스크로 하고 상기 텅스텐 실리사이드층, 제 2폴리실리콘층 및 ONO막을 식각하여 플래쉬 메모리영역의 플로팅 게이트(13a) 위에 콘트롤 게이트(21)를 형성함과 동시에 로직영역에 게이트(20)를 형성한다. 그런 다음, 제 2감광막 패턴을 제거한다.Subsequently, as shown in FIG. 1C, the tungsten silicide layer, the second polysilicon layer, and the ONO layer are etched using the second photoresist pattern as a mask, and the control gate 21 is disposed on the floating gate 13a of the flash memory region. At the same time, the gate 20 is formed in the logic region. Then, the second photoresist pattern is removed.
그러나 상기와 같은 종래의 복합 반도체 장치의 제조방법에 있어서는 다음과 같은 문제점이 있었다.However, the above-described conventional manufacturing method of the composite semiconductor device has the following problems.
텅스텐 실리사이드층, 폴리실리콘층 및 ONO막을 식각하여 동시에 플래쉬 메모리영역에서의 콘트롤 게이트 및 로직영역에서의 게이트를 형성하는 과정에서, 상기 식각 과정에서 플래쉬 메모리 영역과 로직영역의 단차로 인해 플로팅 게이트 측에 제 2폴리 실리콘층 및 텅스텐 실리사이드층 등의 식각 잔류물(17)이 발생되어 복합 반도체 장치의 신뢰성을 저하시킨다. 또한, 상기 식각 과정에서 오버 에치(over etch)로 인해 감광막 손실이 되며, 이 과정에서 로직영역의 활성영역에 데미지(damage)가 발생되는 문제점이 있었다.In the process of etching the tungsten silicide layer, the polysilicon layer, and the ONO film to form a gate in the control gate and the logic region in the flash memory region at the same time, due to the step difference between the flash memory region and the logic region in the etching process, Etch residues 17, such as a second polysilicon layer and a tungsten silicide layer, are generated to reduce the reliability of the composite semiconductor device. In addition, there is a problem in that the photoresist is lost due to over etch during the etching process, and damage occurs in the active region of the logic region.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로, 산화막으로 된 하드 마스크를 이용하여 로직영역의 활성영역에 데미지 없이 잔존하는 제 2폴리 실리콘층을 제거함으로써, 플로팅 게이트 측에 식각 잔류물이 발생되는 것을 방지할 수 있는 복합 반도체 장치의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, by using a hard mask of the oxide film to remove the remaining second polysilicon layer in the active region of the logic region without damage, the etching residue on the floating gate side It is an object of the present invention to provide a method for manufacturing a composite semiconductor device that can be prevented from occurring.
도 1a 내지 도 1c는 종래의 복합 반도체장치의 제조방법을 나타낸 공정 단면도1A to 1C are cross-sectional views illustrating a method of manufacturing a conventional composite semiconductor device.
도 2a 내지 도 2d는 본 발명의 일실시예에 따른 복합 반도체 장치의 제조방법을 나타낸 공정 단면도2A through 2D are cross-sectional views illustrating a method of manufacturing a composite semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
100 : 반도체 기판 101 : 소자 격리막100 semiconductor substrate 101 device isolation film
102 : 터널링 산화막 103a : 플로팅 게이트102 tunneling oxide film 103a floating gate
104 : 제 1 감광막 패턴 105 : ONO막104: first photosensitive film pattern 105: ONO film
106 : 게이트 절연막 107 : 폴리실리콘층106: gate insulating film 107: polysilicon layer
108 : 하드 마스크용 산화막 109 : 제 2감광막 패턴108: oxide film for hard mask 109: second photosensitive film pattern
110 : 게이트 전극 120 : 제 3감광막 패턴110 gate electrode 120 third photosensitive film pattern
112 : 컨트롤 게이트112: control gate
상기와 같은 목적을 달성하기 위한 본 발명의 복합 반도체 장치의 제조방법은 플래쉬 메모리 영역 및 로직영역이 정의된 반도체 기판을 제공하는 단계와, 플래쉬 메모리 영역에 터널링 산화막과 플로팅 게이트을 형성하는 단계와, 결과물 전면에 ONO막, 폴리실리콘층, 하드 마스크용 산화막을 차례로 형성하는 단계와, 하드 마스크용 산화막 위에 플래쉬 메모리영역 및 로직영역의 게이트 형성영역을 덮는제 1감광막 패턴을 형성하는 단계와, 제 1감광막 패턴을 마스크로 하고 하드 마스크용 산화막, 폴리실리콘층, ONO층을 식각하여 상기 로직영역에 게이트 전극을 형성하는 단계와, 제 1감광막 패턴을 제거하는 단계와, 상기 구조 전면에 로직영역 및 플래쉬 메모리영역의 콘트롤 게이트 형성영역을 덮는 제 2감광막 패턴을 형성하는 단계와, 제 2감광막 패턴을 마스크로 하고 잔류된 하드 마스크용 산화막, 폴리실리콘층, ONO층을 식각하여 플래쉬 메모리영역에 콘트롤 게이트를 형성하는 단계와, 제 2감광막 패턴을 제거하는 단계를 포함한 것을 특징으로 한다.In order to achieve the above object, there is provided a method of manufacturing a composite semiconductor device of the present invention, the method comprising: providing a semiconductor substrate having a flash memory region and a logic region defined therein; forming a tunneling oxide layer and a floating gate in the flash memory region; Forming an ONO film, a polysilicon layer, and an oxide film for hard mask on the entire surface, forming a first photoresist film pattern covering a gate memory region of a flash memory region and a logic region on the oxide mask for hard mask, and a first photosensitive film Forming a gate electrode in the logic region by etching the hard mask oxide film, the polysilicon layer, and the ONO layer using a pattern as a mask, removing the first photoresist pattern, and a logic region and a flash memory on the entire structure Forming a second photoresist pattern covering the control gate formation region of the region; And the characterized in that including the steps and, the step of removing the second photosensitive film pattern as a mask and etching the remaining oxide film, the polysilicon layer for the hard mask, the ONO layer to form the control gate the flash memory area.
또한, 상기 ONO막의 두께는 120∼160Å인 것이 바람직하다.Moreover, it is preferable that the thickness of the said ONO film | membrane is 120-160 GPa.
또한, 상기 폴리실리콘층의 두께는 2000∼3000Å이고, 상기 하드 마스크의 두께는 200∼300Å인 것이 바람직하다.Moreover, it is preferable that the thickness of the said polysilicon layer is 2000-3000 GPa, and the thickness of the said hard mask is 200-300 GPa.
또한, 상기 플로팅 게이트의 두께는 600∼1000Å인 것이 바람직하다.In addition, the thickness of the floating gate is preferably 600 to 1000 kPa.
이하, 첨부된 도면을 참조하여 본 발명의 복합 반도체 장치의 제조방법에 대하여 보다 상세히 설명하기로 한다.Hereinafter, a method of manufacturing a composite semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 일실시예에 따른 복합 반도체장치의 제조방법을 나타낸 공정 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a composite semiconductor device according to an embodiment of the present invention.
본 발명의 일실시예에 따른 복합 반도체장치의 제조방법은, 도 2a에 도시한 바와 같이, 먼저, 플래쉬 메모리 영역과 로직영역이 정의된 반도체 기판(100)을 제공한다. 이어, 상기 반도체 기판(100)에 활성영역과 필드영역을 한정하는 소자 격리막(101)을 형성한다.In the method of manufacturing a composite semiconductor device according to an embodiment of the present invention, as shown in FIG. 2A, first, a semiconductor substrate 100 in which a flash memory region and a logic region are defined is provided. Subsequently, an isolation layer 101 is formed on the semiconductor substrate 100 to define an active region and a field region.
이어, 상기 반도체 기판(100) 전면에 산화막(미도시)과 제 1 폴리 실리콘층(미도시)을 차례로 형성한 후, 상기 제 1폴리 실리콘층 상에 감광막을 도포하고 노광 및 현상하여 플래쉬 메모리영역에서의 플로팅 게이트 형성영역(미도시)을 덮는 제 1감광막 패턴(104)을 형성한다. 이어, 상기 제 1감광막 패턴(104)을 마스크로 하고 상기 막들을 식각하여 플래쉬 메모리 영역에 터널링 산화막(102), 플로팅 게이트(103a)를 형성한다. 이때, 상기 플로팅 게이트(103a)의 두께는 600∼1000Å이다.Subsequently, an oxide film (not shown) and a first polysilicon layer (not shown) are sequentially formed on the entire surface of the semiconductor substrate 100, and then a photosensitive film is coated on the first polysilicon layer, followed by exposure and development. The first photoresist pattern 104 is formed to cover the floating gate formation region (not shown). Subsequently, the first photoresist layer pattern 104 is used as a mask and the layers are etched to form a tunneling oxide layer 102 and a floating gate 103a in a flash memory region. At this time, the thickness of the floating gate 103a is 600 to 1000 kPa.
그런 다음, 도 2b에 도시된 바와 같이, 상기 감광막 패턴을 제거하고 나서, 상기 플로팅 게이트(103a)를 포함한 기판 전면에 ONO막(105), 제 2폴리 실리콘층(107) 및 하드 마스크용 산화막(108)을 차례로 형성한다. 이때, 상기 ONO막(105)은 120∼160Å 두께로, 제 2폴리실리콘층(107)은 2000∼3000Å 두께로 형성한다. 또한, 하드 마스크용 산화막(108)은 200∼300Å 두께로 형성한다.Then, as shown in FIG. 2B, after the photoresist pattern is removed, an ONO film 105, a second polysilicon layer 107, and an oxide film for a hard mask are formed on the entire surface of the substrate including the floating gate 103a. 108) are formed in sequence. In this case, the ONO film 105 is formed to a thickness of 120 to 160 kPa, and the second polysilicon layer 107 is formed to a thickness of 2000 to 3000 kPa. In addition, the oxide film 108 for hard masks is formed in the thickness of 200-300 micrometers.
이 후, 상기 하드 마스크용 산화막(108) 상에 플래쉬 메모리영역 및 로직영역에서의 게이트 형성영역(미도시)을 덮는 제 2감광막 패턴(109)을 형성한다.Thereafter, a second photoresist layer pattern 109 is formed on the hard mask oxide layer 108 to cover the gate formation region (not shown) in the flash memory region and the logic region.
이어, 도 2c에 도시된 바와 같이, 상기 제 2감광막 패턴을 마스크로 하고 상기 로직영역의 하드 마스크용 산화막, 제 2폴리실리콘층 및 ONO막을 식각하여 게이트 절연막(106) 및 게이트(110)를 형성한다. 이때,Next, as shown in FIG. 2C, the gate photoresist 106 and the gate 110 are formed by etching the second photoresist pattern as a mask and etching the hard mask oxide film, the second polysilicon layer, and the ONO film in the logic region. do. At this time,
그런 다음, 제 2감광막 패턴을 제거하고 나서, 상기 결과의 기판 전면에 로직영역 및 플래쉬 메모리영역의 콘트롤 게이트 형성영역(미도시)을 덮는 제 3감광막 패턴(120)을 형성한다.Then, after removing the second photoresist pattern, a third photoresist pattern 120 is formed on the entire surface of the substrate to cover the control gate formation region (not shown) of the logic region and the flash memory region.
이 후, 도 2d에 도시된 바와 같이, 상기 제 3감광막 패턴을 마스크로 하고상기 플래쉬 메모리영역의 하드 마스크용 산화막, 제 2폴리실리콘층 및 ONO막을 식각하여 콘트롤 게이트(112)를 형성한다. 이어, 제 3감광막 패턴을 제거한다. 이때, 상기 잔류된 하드 마스크용 산화막은 후속의 엘디디(Lightly Doped Drain) 식각과 세정 공정을 통해 자연 제거된다.2D, the control gate 112 is formed by etching the hard mask oxide film, the second polysilicon layer, and the ONO film of the flash memory area using the third photoresist pattern as a mask. Next, the third photosensitive film pattern is removed. At this time, the remaining oxide film for hard mask is naturally removed through a subsequent lightly doped drain etching and cleaning process.
이상에서 설명한 바와 같이 본 발명의 복합 반도체 장치의 제조방법에 의하면, 로직영역의 게이트와 플래쉬 메모리영역의 콘트롤 게이트를 각각 패터닝하기 때문에 식각 과정에서 단차에 의한 잔류물 제거를 위한 오버 에치 시 로직영역의 활성영역에 데미지가 발생되는 것을 막을 수 있다.As described above, according to the manufacturing method of the composite semiconductor device of the present invention, since the gate of the logic region and the control gate of the flash memory region are respectively patterned, the logic region of the logic region during over-etching to remove residues due to the step difference in the etching process. Damage to the active area can be prevented.
또한, 로직영역의 게이트와 플래쉬 메모리영역의 콘트롤 게이트 형성을 위한 식각 공정에서 하드 마스크용 산화막을 사용함으로써 감광막 마진을 충분히 확보할 수 있어 충분한 오버 에치를 실시할 수 있으므로 단차에 의한 잔류물 제거가 가능하다.In addition, in the etching process for forming the gate of the logic region and the control gate of the flash memory region, by using an oxide film for hard mask, sufficient margin of photoresist can be secured and sufficient over-etching can be performed to remove residues due to the step difference. Do.
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| KR100869748B1 (en) * | 2007-08-23 | 2008-11-21 | 주식회사 동부하이텍 | Complex semiconductor device and method of fabricating the same |
| CN108807398A (en) * | 2018-06-08 | 2018-11-13 | 上海华虹宏力半导体制造有限公司 | Semiconductor devices and its manufacturing method |
| CN111293120A (en) * | 2020-04-01 | 2020-06-16 | 上海华虹宏力半导体制造有限公司 | Split-gate flash memory and preparation method thereof |
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| KR101767112B1 (en) * | 2014-02-17 | 2017-08-11 | 매그나칩 반도체 유한회사 | Method for manufacturing non volatile memory device |
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| KR100273705B1 (en) * | 1997-12-22 | 2000-12-15 | 윤종용 | Method for fabricating of nonvolatile memory device and well structure thereof |
| KR100277873B1 (en) * | 1998-12-01 | 2001-01-15 | 김영환 | Manufacturing Method of Semiconductor Device |
| KR20010108988A (en) * | 2000-06-01 | 2001-12-08 | 박종섭 | Method of manufacturing flash memory device |
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| KR100869748B1 (en) * | 2007-08-23 | 2008-11-21 | 주식회사 동부하이텍 | Complex semiconductor device and method of fabricating the same |
| CN108807398A (en) * | 2018-06-08 | 2018-11-13 | 上海华虹宏力半导体制造有限公司 | Semiconductor devices and its manufacturing method |
| CN108807398B (en) * | 2018-06-08 | 2020-11-13 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN111293120A (en) * | 2020-04-01 | 2020-06-16 | 上海华虹宏力半导体制造有限公司 | Split-gate flash memory and preparation method thereof |
| CN111293120B (en) * | 2020-04-01 | 2023-05-26 | 上海华虹宏力半导体制造有限公司 | Split gate flash memory and preparation method thereof |
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