KR100408713B1 - Method for forming dual gate electrode of semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a dual gate electrode of a semiconductor device, the method of manufacturing a dual gate electrode of a transistor formed in a peripheral circuit region of a DRAM or logic device, each having a different thickness on the DRAM region and the logic region; In the case of forming the gate electrode, a polysilicon layer can be formed in a multi-layer on the logic region by using a thin film having a different etching selectivity as an etch stop layer, thereby improving process yield by preventing damage to the semiconductor substrate and device isolation insulating film. It is a technology that can improve the operation characteristics and reliability.

Description

Method for forming dual gate electrode of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a dual gate electrode of a semiconductor device, and more particularly, to manufacturing a dual gate of M.D.M. (MDL) in which logic and DRAM coexist. The present invention relates to a method of forming a dual gate electrode of a semiconductor device in which gate electrodes having different thicknesses are formed by using an etch stop layer having an etching selectivity difference in a process, thereby improving operation characteristics and reliability of the device.

The conventional method of manufacturing a dual gate electrode is a dual implant (implant) using a mask on the undoped polysilicon layer, or n + gate by an in-situ doping method The method of depositing and patterning the and p + gates respectively was mainly used.

However, the former method is easy to process, but high doping is difficult, and gate depletion is likely to occur due to the dopant profile.

In addition, the latter method requires the deposition of n + / p + polysilicon gates, so that each process has to be set up, and there is also a complexity of defining and patterning each gate after deposition.

Hereinafter, a method of forming a dual gate electrode of a semiconductor device according to the related art will be described with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating a method of forming a dual gate electrode of a semiconductor device according to a first embodiment of the prior art.

First, an isolation layer 101 is formed on a semiconductor substrate 100 having a DRAM region I and a logic region II.

Next, a first gate insulating film 103 and a first polysilicon layer 105 are sequentially formed on the semiconductor substrate 100.

Next, an etch stop layer 107 having a predetermined thickness is formed on the first polysilicon layer 105. (See Figure 1A)

Next, the etch stop layer 107, the first polysilicon layer 105, and the first gate insulating layer 103 on the logic region II of the semiconductor substrate 100 are removed to be etched on the DRAM region I. The prevention film pattern 108, the first polysilicon layer pattern 106, and the first gate insulating film pattern 104 are formed. (See FIG. 1B)

Next, a second gate insulating film 109 is formed on the exposed semiconductor substrate 100 on the logic region II, and a second polysilicon layer 111 is formed over the entire surface. In this case, the second gate insulating film 109 and the second polysilicon layer 111 are formed thicker than the first gate insulating film 103 and the first polysilicon layer 106 formed on the DRAM region (I). .

Next, the second polysilicon layer 111 on the DRAM region I is removed to form the second polysilicon layer pattern 112. In this case, the second polysilicon layer 111 is removed by an etching process using the etch barrier pattern 108 as an etch barrier. (See FIG. 1D)

Next, the etch stop layer pattern 108, the first polysilicon layer pattern 16, and the first gate insulating layer pattern of the DRAM region I are formed by using a gate electrode mask that protects a portion intended as a gate electrode as an etch mask. And the second polysilicon layer pattern 112 and the second gate insulating layer 109 of the logic region II are etched to form the first gate electrode 113 and the logic region on the DRAM region I. The second gate electrode 115 is formed on (II). (See Figure 1E)

2A to 2C are cross-sectional views illustrating a method of forming a dual gate electrode of a semiconductor device in accordance with a second embodiment of the prior art.

First, an isolation layer 121 is formed on a semiconductor substrate 120 having a DRAM region I and a logic region II.

Next, a first gate insulating film is formed in the DRAM region I of the semiconductor substrate 120, and a MOS field transistor including a gate electrode 123 and a source / drain region is formed.

Next, a first interlayer insulating film 124 is formed over the entire surface.

Next, a bit line 125 is formed to be connected to a portion of the source / drain area, which is to be a bit line contact.

Next, a second interlayer insulating film 126 is formed over the entire surface.

Next, a storage electrode connected to a predetermined portion of the source / drain region as a storage electrode contact is formed, and a dielectric film and a plate electrode are formed thereon to form a capacitor 127.

Next, a third interlayer insulating film 129 is formed over the entire surface. (See Figure 2A)

Next, the semiconductor substrate 120 is exposed by removing the third interlayer insulating film 129, the second interlayer insulating film 127, and the first interlayer insulating film 124 formed in the logic region II of the semiconductor substrate 120. . (See Figure 2b)

Next, a second gate insulating layer 131 and a polysilicon layer 133 are formed on the exposed semiconductor substrate 120. (See Figure 2c)

Thereafter, the polysilicon layer 133 and the second gate insulating layer 131 are etched using a gate electrode mask as an etch mask to form a gate electrode on the logic region II.

As described above, in the method of forming a dual gate electrode of a semiconductor device according to the related art, when a gate electrode having a different thickness is formed in a DRAM region and a logic region, a semiconductor substrate may be formed by an etching rate difference in an etching process defining a gate electrode. The active region and the device isolation insulating film may be damaged, and the gate insulating film forming process may be performed separately. Therefore, dopants implanted in the junction region of the DRAM region may be redistributed by a subsequent heat treatment process, resulting in deterioration of device operation characteristics and reliability. Can be. In addition, when the logic region is formed after completing the DRAM region, there is a problem in that the process is difficult due to the step difference.

The present invention is to solve the problems of the prior art, by forming a polysilicon layer in a multi-layer, a thin film having an etch selectivity different from the polysilicon layer is formed as an intermediate layer to be used as an etch barrier different from the DRAM region and the logic region It is an object of the present invention to provide a method for forming a dual gate electrode of a semiconductor device, which can form a gate electrode having a thickness, thereby simplifying a process and improving operating characteristics and reliability of the device.

1A to 1E are cross-sectional views illustrating a method of forming a dual gate electrode of a semiconductor device according to a first embodiment of the prior art;

2A to 2C are cross-sectional views illustrating a method of forming a dual gate electrode of a semiconductor device in accordance with a second embodiment of the prior art;

3A to 3D are cross-sectional views illustrating a method of forming a dual gate electrode of a semiconductor device according to the present invention.

<Description of Symbols for Major Parts of Drawings>

11, 100, 120: semiconductor substrate 13, 101, 121: device isolation insulating film

15 gate insulating film 17, 105 first polycrystalline silicon layer

19, 107: etch stopper 20, 108: etch stopper pattern

21, 111: second polycrystalline silicon layer 22, 112: second polycrystalline silicon layer pattern

23, 113, 123: first gate electrode 25, 115: second gate electrode

103: first gate insulating film 104: first gate insulating film pattern

106: first polysilicon layer pattern 109, 131: second gate insulating film

124: first interlayer insulating film 125: bit line

126: second interlayer insulating film 127: capacitor

129: third interlayer insulating film

Ⅰ: DRAM region Ⅱ: logic region

Dual gate electrode forming method of a semiconductor device according to the present invention for achieving the above object,

Forming a device isolation insulating film defining an active region in a semiconductor substrate comprising a DRAM region and a logic region;

Sequentially forming a gate insulating film, a first polysilicon layer, and an etch stop film on the semiconductor substrate;

Removing an etch stop layer on the logic region;

Cleaning the structure to remove the residual oxide film formed on the first polysilicon layer exposed on the logic region;

Forming a second polysilicon layer on the entire surface,

Etching the second polysilicon layer using an etching mask exposing the DRAM region, wherein the second polysilicon layer is etched using the etch barrier layer as an etch barrier;

The gate electrode mask is used as an etch mask to etch the etch stop layer, the first polysilicon layer and the gate insulating layer on the DRAM region, and the second polysilicon layer, the first polysilicon layer, and the gate insulating layer on the logic region to form a dual gate electrode. It is characterized by including the process of forming.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3A to 3D are cross-sectional views illustrating a method of forming a dual gate electrode of a semiconductor device according to the present invention.

First, an element isolation insulating film 13 defining an active region is formed in the semiconductor substrate 11 including the DRAM region I and the logic region II.

Next, the gate insulating film 15 is formed on the entire surface to have a predetermined thickness.

Next, a first polysilicon layer 17 is formed on the gate insulating layer 15.

Next, an etch stop layer 19 is formed on the first polysilicon layer 17. In this case, the etch stop layer 19 may be formed to form a thermal oxide (thermal oxide) of 100 ~ 1000Å thickness, or a TEOS film of 250 ~ 1200Å thickness, LP-nitride (low pressure nitride), PE-plasma enhanced nitride (plasma enhanced nitride) Or 50-600 mm thick with an oxy-nitride. (See Figure 3A)

Next, the etch stop layer 19 is etched using an etch mask that exposes the logic region II of the semiconductor substrate 11 to form an etch stop layer pattern 20 on the DRAM region I.

Thereafter, a cleaning process is performed using a mixed solution of HF and a buffered oxide etch (BOE), which is an oxide etching solution, so that a residual oxide film is not formed in the first polysilicon layer 17 exposed on the logic region (II). do.

Next, the second polysilicon layer 21 is formed on the entire surface. (See Figure 3b)

Next, the second polysilicon layer 21 is etched using an etching mask exposing the DRAM region I to form a second polysilicon layer pattern 22 on the logic region II.

Next, the etch stop layer pattern 20, the first polycrystalline silicon layer 17, the gate insulating layer 15, the second polycrystalline silicon layer pattern 22, and the first polycrystalline layer may be formed by using a gate electrode mask that defines a gate electrode as an etch mask. The silicon layer 17 and the gate insulating layer 15 are etched to form a first gate electrode 23 in the DRAM region I and a second gate electrode 25 in the logic region II. At this time, since the thickness of the gate electrode formed in the DRAM region (I) and the logic region (II) is different, the etching process is performed using a separate gate electrode mask so that the semiconductor substrate 11 and the device isolation insulating film 13 are formed. It can prevent damage. (See FIG. 3D)

Meanwhile, the process up to FIG. 3C may be performed, a MOS field effect transistor, a bit line, and a capacitor may be formed in the DRAM region (I), and then the gate electrode forming process of the logic region (II) may be performed.

As described above, in the method of forming the dual gate electrode of the semiconductor device according to the present invention, when the gate electrode having different thicknesses is formed in the DRAM region and the logic region, a thin film having a different etch selectivity is used as the etch stop layer on the logic region. Since the polysilicon layer can be formed in multiple layers, it is possible to prevent damage to the semiconductor substrate and the device isolation insulating film, thereby improving process yield and improving the operation characteristics and reliability of the device.

Claims (7)

Forming a device isolation insulating film defining an active region in a semiconductor substrate comprising a DRAM region and a logic region; Sequentially forming a gate insulating film, a first polysilicon layer, and an etch stop film on the semiconductor substrate; Removing an etch stop layer on the logic region; Cleaning the structure to remove the residual oxide film formed on the first polysilicon layer exposed on the logic region; Forming a second polysilicon layer on the entire surface, Etching the second polysilicon layer using an etching mask exposing the DRAM region, and etching using the etch barrier layer as an etching barrier; The dual gate electrode is formed by etching the etch stop layer, the first polysilicon layer and the gate insulating layer on the DRAM region, the second polysilicon layer, the first polysilicon layer and the gate insulating layer on the logic region by using a gate electrode mask as an etching mask. A dual gate electrode forming method of a semiconductor device comprising the step of forming. The method of claim 1, And the etch stop layer is formed to a thickness of 100 to 1000 kW using a thermal oxide film. The method of claim 1, The etch stop layer is a method of forming a dual gate electrode of a semiconductor device, characterized in that formed using a TEOS film of 250 ~ 1200Å thickness. The method of claim 1, The anti-etching film is a method of forming a dual gate electrode of a semiconductor device, characterized in that formed by 50 to 600Å thickness using one selected from the group consisting of LP-nitride film, PE-nitride film and oxynitride film. delete delete delete