KR100683491B1 - Method for fabricating semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to prevent the degradation of device reliability due to a low threshold voltage and to improve a device speed by using a nonuniform gate insulating layer. A semiconductor substrate(201) are defined with a fin transistor region and a planar transistor region. Pad oxide and nitride layers for opening an isolation region of the substrate are formed on the resultant structure. A trench is formed by etching selectively the substrate using the pad nitride layer as an etch mask. An isolation(205) is formed in the trench. An active region is opened by etching selectively the isolation layer of the fin transistor region. The pad nitride layer is removed. The pad oxide layer is removed from the planar transistor region. A dielectric film(206) is formed at both sidewalls of the active region of the fin transistor region, on the pad oxide layer and on the active region of the planar transistor region. A gate conductive layer(208) is formed on the resultant structure to enclose the dielectric film. The dielectric film and the pad oxide layer are used as a gate insulating layer, so that the gate insulating layer has a nonuniform thickness.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

1A to 1D are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

2A to 2E are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

3 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

201: semiconductor substrate

202a: active region of the pin transistor region

202b: active region of planar transistor region

203: pad oxide film 205: device isolation film

206 dielectric film 207 gate insulating film

208: gate conductive film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a manufacturing process of a three-gate fin cell transistor during a semiconductor device manufacturing process.

In the semiconductor industry, the more chips or dies that can be produced per wafer, the more competitive the cost will be. Can be. One of the most direct ways to implement this trend is to reduce the size of the device. In other words, the semiconductor industry is competing to reduce the line width of circuits. However, the shortcomings caused by reducing the line width included Short Channel Effect (SCE), Punch Through Breakdown (PTB), Drain Induced Barrier Lowering (DIBL), and Gate Induced Drain Leakage (GIDL).

In order to solve the above problems, it is a current trend to control the ion implantation concentration of impurities in the channel or source / drain junction portion of the transistor. However, the above solution has new problems to be overcome by bringing low channel current. Accordingly, in order to solve the above problem, a three-gate fin cell transistor is formed. The three-gate fin cell transistor has a new method of increasing the channel current but having a low threshold voltage. have.

In the conventional pin-type three-gate pin cell transistor, it is possible to simultaneously prevent high integration and characteristic deterioration of the device by securing a high channel current while having an excellent SCE prevention phenomenon. In particular, the BT Tid Transistor using the damascene method has been spotlighted as an easy etching process for forming a gate electrode.

When the thickness of the fin active region, which is the channel width of the three-gate fin cell transistor having the fin shape, becomes thin, the SS (Subthreshold Swing), DIBL, and GIDL characteristics are improved, thereby improving leakage current and SCE, but lowering the threshold voltage. Problems arise.

When a bias voltage is applied to a three-gate pin cell transistor according to the prior art, since an electric field is concentrated at an upper edge portion of the fin active region, a threshold voltage lower than a desired value is formed, and the low threshold voltage is reduced. Leakage current is increased.

In order to reduce the leakage current, the doping concentration of the channel is increased, which causes a problem of reducing the refresh time.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and solves the defect of the threshold voltage lowered by the electric field concentrated on both edge portions of the upper portion of the active region of the fin transistor, and pins in one semiconductor substrate. An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the low threshold voltage defect when forming a transistor and a planar transistor together.

According to an aspect of the present invention for achieving the above object, preparing a semiconductor substrate divided into a fin transistor region and a planar transistor region, forming a pad oxide film and a pad nitride film opening the device isolation region on the semiconductor substrate Forming a trench by etching the semiconductor substrate using the pad nitride layer as an etch barrier; forming a device isolation layer by filling the trench; selectively etching the device isolation layer of the fin transistor region to open an active region Removing the pad nitride layer, removing the pad oxide layer of the planar transistor region, both sidewalls of the active region of the fin transistor region, an upper portion of the pad oxide layer, and a dielectric layer on the active region of the planar transistor Forming a pin and the Forming a gate conductive film to surround the dielectric film of the transistor region, and forming a gate conductive film on the dielectric film of the planar transistor, wherein the dielectric film and the pad oxide film of the fin transistor region are a gate insulating film. A method of manufacturing a semiconductor device is provided, wherein the gate insulating film formed on the active region of the fin transistor region is thicker than the gate insulating film formed on the sidewall of the active region of the fin transistor region.

delete

delete

The method may further include preparing a semiconductor substrate divided into a fin transistor region and a planar transistor region, forming a pad layer to open an isolation region on the semiconductor substrate, and etching the semiconductor substrate using the pad layer as an etch barrier. Forming a trench, forming a device isolation layer by filling the trench, selectively etching the device isolation layer of the pin transistor region to open an active region, removing the pad layer of the planar transistor region, Forming a dielectric film on both sidewalls of the active region of the fin transistor region, an upper portion of the pad layer, and the active region of the planar transistor, and forming a gate conductive film to surround the dielectric layer of the fin transistor region, and the planar Gate on the dielectric film of a transistor And forming a coating film, wherein the dielectric film and the pad layer of the fin transistor region are gate insulating films, wherein the gate insulating film formed on the active region of the fin transistor region is formed on the active region of the fin transistor region. There is provided a method of manufacturing a semiconductor device, the thickness of which is thicker than the gate insulating film formed on the sidewalls.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

(First embodiment)

1A to 1D are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

In the semiconductor device manufacturing process according to the first embodiment of the present invention, first, as shown in FIG. 1A, a pad oxide film 103 and a pad nitride film 104 are formed on a predetermined region of a fin active region of a semiconductor substrate 101. To form.

At this time, the pad oxide film 103 is preferably 50 ~ 200Å thickness.

Subsequently, the semiconductor substrate 101 is etched using the pad oxide layer 103 and the pad nitride layer 104 as an etch barrier to form trenches at both sides of the fin active region 102 and the fin active region 102. .

Next, as shown in FIG. 1B, after forming the device isolation film 105 filling the trench, the device isolation film 105 is formed by performing a chemical mechanical polishing (CMP) process on the device isolation film 105. Flatten.

Subsequently, a portion of the isolation layer 105 in both sidewall portions of the fin active region 102 of the fin transistor region fin is etched to expose a portion of the sidewall surface of the fin active region 102. Thereafter, the pin transistor region fin and the pad nitride layer 104 are removed.

Next, as shown in FIG. 1C, a dielectric film 106 is formed on both sidewalls and the top surface of the exposed fin active region 102.

In this case, the pad oxide layer 103 and the dielectric layer 106 used as an etch barrier during the etching process of the semiconductor substrate 101 to form the fin active region 102 become a gate insulating layer 107.

In addition, the dielectric layer 106 and the pad oxide layer 103 may be formed of the same material.

Next, as shown in FIG. 1D, the gate conductive layer 108 is deposited on the substrate on which the gate insulating layer 107 is formed, and then selectively etched to form a gate pattern.

As described above, in the present invention, since the pad oxide film 103 and the dielectric film 106 become the gate insulating film 107, the pad oxide film 103 and the dielectric film 106 are formed on the upper surface of the fin active region 102 rather than on both side walls of the fin active region 102. The thickness of the gate insulating layer 107 is formed to solve the problem that the electric field is concentrated on both edge portions of the upper portion of the fin active region 102.

The pad nitride film 104, the pad oxide film 103, and the dielectric film 106 may be formed as the gate insulating film 107 by skipping the removal process of the pad nitride film 104.

(2nd Example)

2A through 2E are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

In the process of manufacturing a semiconductor device according to the second embodiment of the present invention, first, as shown in FIG. 2A, a device is separated into a semiconductor substrate 201 which is divided into a fin transistor region and a planar transistor region. In order to form a trench, a pad oxide film 203 and a pad nitride film 204 that open the device isolation region are sequentially formed.

At this time, the thickness of the pad oxide film 203 is preferably 50 ~ 200 50.

Subsequently, the semiconductor substrate 201 is etched using the pad oxide layer 203 and the pad nitride layer 204 as an etch barrier to form a trench, a fin active region 202a and a planar active region 202b.

Subsequently, the device isolation layer 205 filling the trench is formed and planarized by performing a chemical mechanical polishing (CMP) process.

Next, as shown in FIG. 2B, a portion of the device isolation layer 205 of both sidewalls of the fin active region 202a of the fin transistor region fin is etched to form the side of the fin active region 202a. Expose some of the walls. Thereafter, the pad nitride layer 204 of the fin transistor region fin and the planar transistor region planar is removed.

Next, as shown in FIG. 2C, only the pad oxide layer 203 of the planar transistor region planar is removed.

Next, as illustrated in FIG. 2D, both sidewalls of the active region of the planar transistor region planar, the fin active region 202a of the fin transistor region fin, and the upper portion of the pad oxide layer 203 may be formed. The dielectric film 206 is formed.

In this case, the pad oxide film 203 and the dielectric film 206 are preferably made of the same material.

In addition, the pad oxide layer 203 and the dielectric layer 206 of the fin transistor region fin become a gate insulating layer 207. In addition, the dielectric layer 206 of the planar transistor region also becomes a gate insulating layer 206.

Next, as illustrated in FIG. 2E, the gate conductive layer 208 is deposited on the entire structure of the substrate on which the dielectric layer 206 is formed, and then selectively etched to form the fin in the fin transistor region fin. A gate conductive layer 208 is formed around the active region 202a, and a gate pattern is formed on the planar active region 202b of the planar transistor region planar.

As described above, when the fin transistor and the planar transistor are formed in one semiconductor substrate 201, the present invention is directed to an electric field concentrated at both upper edges of the fin active region 202a of the conventional fin transistor. The gate insulating film 207 is formed of the pad oxide film 203 and the subsequent dielectric film 206 used as an etch barrier during the etching process for forming the fin active region 202a to solve the defect of lowering the threshold voltage. The thickness of the gate insulating layer 207 on the fin active region 202a is increased.

(Third Embodiment)

3 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention.

Referring to FIG. 3, a pad oxide film and a pad nitride film sequentially opening a device isolation region to form a device isolation trench in a semiconductor substrate 301 divided into a fin transistor region fin and a planar transistor region planar are sequentially formed. The pad layer 303 is formed by laminating.

Next, the semiconductor substrate 301 is etched using the pad layer 303 as an etch barrier to form a trench, a fin active region 302a and a planar active region 302b.

Subsequently, an isolation layer 305 filling the trench is formed.

Subsequently, a portion of the isolation layer 305 in both sidewalls of the fin active region 302a of the fin transistor region fin is etched to expose a portion of the sidewall surface of the fin active region 302a.

Subsequently, the pad layer 303 in the planar transistor region planar is removed.

Subsequently, the planar active region 302b of the dielectric layer 306 and the planar transistor region planar covering both sidewall surfaces of the fin active region 302a of the fin transistor region fin and the pad layer 303. The dielectric film 306 is formed.

In this case, the pad layer 303 and the dielectric layer 306 of the fin transistor region fin become the gate insulating layer 307. In addition, the dielectric layer 306 of the planar transistor region also becomes a gate insulating layer 306.

Subsequently, the gate conductive layer 308 is deposited on the entire structure of the substrate on which the dielectric layer 306 is formed, and then selectively etched to cover the portion of the fin active region 302a of the fin transistor region fin. A film 308 is formed, and a gate pattern is formed on the planar active region 302b of the planar transistor region planar.

As described above, when the fin transistor and the planar transistor are formed in one semiconductor substrate 301, the present invention is applied to an electric field concentrated at both upper edges of the fin active region 302a of the conventional fin transistor. The gate insulating layer 307 is formed of the pad layer 303 and the subsequent dielectric layer 306 used as an etch barrier during the etching process for forming the fin active region 302a to solve the defect of lowering the threshold voltage. The thickness of the gate insulating layer 307 on the fin active region 302a is increased.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

As described above, in order to solve a defect in which a low threshold voltage is formed by an electric field concentrated on both edge portions of the active region of the fin transistor, the thickness of the gate insulating layer on the upper portion of the active region may be increased. It is formed thicker than the thickness of the gate insulating film in both side wall portions of the region.

Therefore, the problem of the device's reliability deteriorated due to the low threshold voltage is solved, and when the pin transistor and the planner transistor are formed on one substrate, a thin gate insulating film (dielectric film) can be formed in the planar transistor to increase the speed of the device. It has the effect of raising.

Claims (10)

delete delete delete Preparing a semiconductor substrate divided into a fin transistor region and a planar transistor region; Forming a pad oxide film and a pad nitride film to open a device isolation region on the semiconductor substrate; Etching the semiconductor substrate using the pad nitride layer as an etch barrier to form a trench; Filling the trench to form an isolation layer; Selectively etching the device isolation layer in the fin transistor region to open an active region; Removing the pad nitride film; Removing the pad oxide layer in the planar transistor region; Forming a dielectric film on both sidewalls of the active region of the fin transistor region, on the pad oxide layer, and on the active region of the planar transistor; And Forming a gate conductive film to surround the dielectric film of the fin transistor region, and forming a gate conductive film on the dielectric film of the planar transistor, wherein the dielectric film and the pad oxide film of the fin transistor region are formed as a gate insulating film. And the gate insulating film formed on the active region of the fin transistor region is thicker than the gate insulating film formed on the sidewall of the active region of the fin transistor region. The method of claim 4, wherein The pad oxide film is a semiconductor device manufacturing method, characterized in that the thickness is 50 ~ 200Å. The method of claim 4, wherein And the dielectric film and the pad oxide film are made of the same material. delete delete Preparing a semiconductor substrate divided into a fin transistor region and a planar transistor region; Forming a pad layer to open the device isolation region on the semiconductor substrate; Etching the semiconductor substrate using the pad layer as an etch barrier to form a trench; Filling the trench to form an isolation layer; Selectively etching the device isolation layer in the fin transistor region to open an active region; Removing the pad layer of the planar transistor region; Forming a dielectric film on both sidewalls of the active region of the fin transistor region, on the pad layer, and on the active region of the planar transistor; And Forming a gate conductive film to surround the dielectric film of the fin transistor region, and forming a gate conductive film on the dielectric film of the planar transistor, wherein the dielectric film and the pad layer of the pin transistor region are gate insulating films, And the gate insulating film formed on the active region of the fin transistor region is thicker than the gate insulating film formed on the sidewall of the active region of the fin transistor region. The method of claim 9, The pad layer has a structure in which a pad oxide film and a pad nitride film are sequentially stacked.

Images